Merge commit 'v2.6.36-rc3' into x86/memblock

Conflicts:
	arch/x86/kernel/trampoline.c
	mm/memblock.c

Merge reason: Resolve the conflicts, update to latest upstream.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

11 files changed, 188 insertions, 117 deletions

diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h
index dfc73050e6b4..1de779f4f240 100644
--- a/arch/cris/include/arch-v32/arch/cache.h
+++ b/arch/cris/include/arch-v32/arch/cache.h
@@ -7,6 +7,8 @@
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_SHIFT 5
 
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
 void flush_dma_list(dma_descr_data *descr);
 void flush_dma_descr(dma_descr_data *descr, int flush_buf);
 
diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h
index 3674081389fd..61906153a9af 100644
--- a/arch/cris/include/arch-v32/arch/dma.h
+++ b/arch/cris/include/arch-v32/arch/dma.h
@@ -1,79 +1 @@
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS	10
-
-#define NETWORK_ETH0_TX_DMA_NBR 0	/* Ethernet 0 out. */
-#define NETWORK_ETH0 RX_DMA_NBR 1	/* Ethernet 0 in. */
-
-#define IO_PROC_DMA0_TX_DMA_NBR 2	/* IO processor DMA0 out. */
-#define IO_PROC_DMA0_RX_DMA_NBR 3	/* IO processor DMA0 in. */
-
-#define ATA_TX_DMA_NBR 2		/* ATA interface out. */
-#define ATA_RX_DMA_NBR 3		/* ATA interface in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 2		/* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 3		/* Asynchronous serial port 2 in. */
-
-#define IO_PROC_DMA1_TX_DMA_NBR 4	/* IO processor DMA1 out. */
-#define IO_PROC_DMA1_RX_DMA_NBR 5	/* IO processor DMA1 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4		/* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5		/* Asynchronous serial port 1 in. */
-
-#define SYNC_SER0_TX_DMA_NBR 4		/* Synchronous serial port 0 out. */
-#define SYNC_SER0_RX_DMA_NBR 5		/* Synchronous serial port 0 in. */
-
-#define EXTDMA0_TX_DMA_NBR 6		/* External DMA 0 out. */
-#define EXTDMA1_RX_DMA_NBR 7		/* External DMA 1 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 6		/* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 7		/* Asynchronous serial port 0 in. */
-
-#define SYNC_SER1_TX_DMA_NBR 6		/* Synchronous serial port 1 out. */
-#define SYNC_SER1_RX_DMA_NBR 7		/* Synchronous serial port 1 in. */
-
-#define NETWORK_ETH1_TX_DMA_NBR 6	/* Ethernet 1 out. */
-#define NETWORK_ETH1_RX_DMA_NBR 7	/* Ethernet 1 in. */
-
-#define EXTDMA2_TX_DMA_NBR 8		/* External DMA 2 out. */
-#define EXTDMA3_RX_DMA_NBR 9		/* External DMA 3 in. */
-
-#define STRCOP_TX_DMA_NBR 8		/* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 9		/* Stream co-processor in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 8		/* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 9		/* Asynchronous serial port 3 in. */
-
-enum dma_owner
-{
-  dma_eth0,
-  dma_eth1,
-  dma_iop0,
-  dma_iop1,
-  dma_ser0,
-  dma_ser1,
-  dma_ser2,
-  dma_ser3,
-  dma_sser0,
-  dma_sser1,
-  dma_ata,
-  dma_strp,
-  dma_ext0,
-  dma_ext1,
-  dma_ext2,
-  dma_ext3
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char * device_id,
-                        unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
+#include "mach/dma.h"
diff --git a/arch/cris/include/arch-v32/arch/io.h b/arch/cris/include/arch-v32/arch/io.h
index 72024452cea9..adc5484351bf 100644
--- a/arch/cris/include/arch-v32/arch/io.h
+++ b/arch/cris/include/arch-v32/arch/io.h
@@ -46,10 +46,12 @@ static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
 	unsigned long flags;
 	spin_lock_irqsave(&iopin->port->lock, flags);
 
-	if (val)
-		*iopin->port->data |= iopin->bit;
-	else
-		*iopin->port->data &= ~iopin->bit;
+	if (iopin->port->data) {
+		if (val)
+			*iopin->port->data |= iopin->bit;
+		else
+			*iopin->port->data &= ~iopin->bit;
+	}
 
 	spin_unlock_irqrestore(&iopin->port->lock, flags);
 }
@@ -60,10 +62,12 @@ static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
 	unsigned long flags;
 	spin_lock_irqsave(&iopin->port->lock, flags);
 
-	if (dir == crisv32_io_dir_in)
-		*iopin->port->oe &= ~iopin->bit;
-	else
-		*iopin->port->oe |= iopin->bit;
+	if (iopin->port->oe) {
+		if (dir == crisv32_io_dir_in)
+			*iopin->port->oe &= ~iopin->bit;
+		else
+			*iopin->port->oe |= iopin->bit;
+	}
 
 	spin_unlock_irqrestore(&iopin->port->lock, flags);
 }
diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h
index d29df5644d3e..81985c0a6789 100644
--- a/arch/cris/include/arch-v32/arch/memmap.h
+++ b/arch/cris/include/arch-v32/arch/memmap.h
@@ -1,24 +1 @@
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00020000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
+#include <mach/memmap.h>
diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h
index 08cb7ff7e4e7..c1051a8da33d 100644
--- a/arch/cris/include/arch-v32/arch/pgtable.h
+++ b/arch/cris/include/arch-v32/arch/pgtable.h
@@ -2,8 +2,16 @@
 #define _ASM_CRIS_ARCH_PGTABLE_H
 
 /* Define the kernels virtual memory area. */
+
+/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#define VMALLOC_START          KSEG_E
+#define VMALLOC_END            KSEG_F
+#else
 #define VMALLOC_START		KSEG_D
 #define VMALLOC_END		KSEG_E
+#endif
+
 #define VMALLOC_VMADDR(x)	((unsigned long)(x))
 
 #endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h
index 6b207f1b6622..3196019706cb 100644
--- a/arch/cris/include/arch-v32/arch/uaccess.h
+++ b/arch/cris/include/arch-v32/arch/uaccess.h
@@ -122,14 +122,14 @@ __do_strncpy_from_user(char *dst, const char *src, long count)
 	__asm__ __volatile__ (
 		"	move.d %3,%0\n"
 		"5:	move.b [%2+],$acr\n"
-		"1:	beq 2f\n"
+		"1:	beq 6f\n"
 		"	move.b $acr,[%1+]\n"
 
 		"	subq 1,%0\n"
 		"2:	bne 1b\n"
 		"	move.b [%2+],$acr\n"
 
-		"	sub.d %3,%0\n"
+		"6:	sub.d %3,%0\n"
 		"	neg.d %0,%0\n"
 		"3:\n"
 		"	.section .fixup,\"ax\"\n"
@@ -140,8 +140,7 @@ __do_strncpy_from_user(char *dst, const char *src, long count)
 		/* The address for a fault at the first move is trivial.
 		   The address for a fault at the second move is that of
 		   the preceding branch insn, since the move insn is in
-		   its delay-slot.  That address is also a branch
-		   target.  Just so you don't get confused...  */
+		   its delay-slot.  Just so you don't get confused...  */
 		"	.previous\n"
 		"	.section __ex_table,\"a\"\n"
 		"	.dword 5b,4b\n"
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
index 9e8eb13b601d..f01dca1ad108 100644
--- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h
+++ b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
@@ -5,6 +5,33 @@
 
 #define MAX_DMA_CHANNELS	12 /* 8 and 10 not used. */
 
+#define NETWORK_ETH_TX_DMA_NBR 0        /* Ethernet 0 out. */
+#define NETWORK_ETH_RX_DMA_NBR 1        /* Ethernet 0 in. */
+
+#define IO_PROC_DMA_TX_DMA_NBR 4        /* IO processor DMA0 out. */
+#define IO_PROC_DMA_RX_DMA_NBR 5        /* IO processor DMA0 in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 2         /* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 3         /* Asynchronous serial port 3 in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 6         /* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 7         /* Asynchronous serial port 2 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4         /* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5         /* Asynchronous serial port 1 in. */
+
+#define SYNC_SER_TX_DMA_NBR 6           /* Synchronous serial port 0 out. */
+#define SYNC_SER_RX_DMA_NBR 7           /* Synchronous serial port 0 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 0         /* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 1         /* Asynchronous serial port 0 in. */
+
+#define STRCOP_TX_DMA_NBR 2             /* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 3             /* Stream co-processor in. */
+
+#define dma_eth0 dma_eth
+#define dma_eth1 dma_eth
+
 enum dma_owner {
 	dma_eth,
 	dma_ser0,
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
index 2f23e5e16f4a..2d52bcc96ed5 100644
--- a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
+++ b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
@@ -1,9 +1,19 @@
+#ifndef STARTUP_INC_INCLUDED
+#define STARTUP_INC_INCLUDED
+
 #include <hwregs/asm/reg_map_asm.h>
 #include <hwregs/asm/gio_defs_asm.h>
 #include <hwregs/asm/pio_defs_asm.h>
 #include <hwregs/asm/clkgen_defs_asm.h>
 #include <hwregs/asm/pinmux_defs_asm.h>
 
+	.macro GIO_SET_P BITS, OUTREG
+	bmi	1f		; btstq: bit -> N flag
+	nop
+	or.d	\BITS, \OUTREG
+1:
+	.endm
+
 	.macro GIO_INIT
 	move.d	CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
 	move.d	REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
@@ -32,10 +42,23 @@
 	move.d	0xFFFFFFFF, $r0
 	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
 	move.d	$r0, [$r1]
-	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
-	move.d	$r0, [$r1]
 	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
 	move.d	$r0, [$r1]
+
+	;; If eth_mdio, eth, geth bits are set in hwprot, don't
+	;; set them to gpio, as this means they have been configured
+	;; earlier and shouldn't be changed.
+	move.d	0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth
+	move.d	REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1
+	move.d	[$r1], $r0
+	btstq	REG_BIT(pinmux, rw_hwprot, eth), $r0
+	GIO_SET_P 0x00FFFF00, $r2		;; pins 8..23 are eth
+	btstq	REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0
+	GIO_SET_P 0x03000000, $r2		;; pins 24..25 are eth_mdio
+	btstq	REG_BIT(pinmux, rw_hwprot, geth), $r0
+	GIO_SET_P 0x000000FF, $r2		;; pins 0..7 are geth
+	move.d	REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
+	move.d	$r2, [$r1]
 	.endm
 
 	.macro START_CLOCKS
@@ -58,3 +81,4 @@
 	move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
 	move.d $r1, [$r0]
 	.endm
+#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
new file mode 100644
index 000000000000..a8c59292586a
--- /dev/null
+++ b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS	10
+
+#define NETWORK_ETH0_TX_DMA_NBR 0	/* Ethernet 0 out. */
+#define NETWORK_ETH0 RX_DMA_NBR 1	/* Ethernet 0 in. */
+
+#define IO_PROC_DMA0_TX_DMA_NBR 2	/* IO processor DMA0 out. */
+#define IO_PROC_DMA0_RX_DMA_NBR 3	/* IO processor DMA0 in. */
+
+#define ATA_TX_DMA_NBR 2		/* ATA interface out. */
+#define ATA_RX_DMA_NBR 3		/* ATA interface in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 2		/* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 3		/* Asynchronous serial port 2 in. */
+
+#define IO_PROC_DMA1_TX_DMA_NBR 4	/* IO processor DMA1 out. */
+#define IO_PROC_DMA1_RX_DMA_NBR 5	/* IO processor DMA1 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4		/* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5		/* Asynchronous serial port 1 in. */
+
+#define SYNC_SER0_TX_DMA_NBR 4		/* Synchronous serial port 0 out. */
+#define SYNC_SER0_RX_DMA_NBR 5		/* Synchronous serial port 0 in. */
+
+#define EXTDMA0_TX_DMA_NBR 6		/* External DMA 0 out. */
+#define EXTDMA1_RX_DMA_NBR 7		/* External DMA 1 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 6		/* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 7		/* Asynchronous serial port 0 in. */
+
+#define SYNC_SER1_TX_DMA_NBR 6		/* Synchronous serial port 1 out. */
+#define SYNC_SER1_RX_DMA_NBR 7		/* Synchronous serial port 1 in. */
+
+#define NETWORK_ETH1_TX_DMA_NBR 6	/* Ethernet 1 out. */
+#define NETWORK_ETH1_RX_DMA_NBR 7	/* Ethernet 1 in. */
+
+#define EXTDMA2_TX_DMA_NBR 8		/* External DMA 2 out. */
+#define EXTDMA3_RX_DMA_NBR 9		/* External DMA 3 in. */
+
+#define STRCOP_TX_DMA_NBR 8		/* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 9		/* Stream co-processor in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 8		/* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 9		/* Asynchronous serial port 3 in. */
+
+enum dma_owner {
+  dma_eth0,
+  dma_eth1,
+  dma_iop0,
+  dma_iop1,
+  dma_ser0,
+  dma_ser1,
+  dma_ser2,
+  dma_ser3,
+  dma_sser0,
+  dma_sser1,
+  dma_ata,
+  dma_strp,
+  dma_ext0,
+  dma_ext1,
+  dma_ext2,
+  dma_ext3
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+			unsigned options, unsigned bandwidth,
+			enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
new file mode 100644
index 000000000000..d29df5644d3e
--- /dev/null
+++ b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_INTMEM_START (0x38000000)
+#define MEM_INTMEM_SIZE (0x00020000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
index 4a10ccbd6cc1..dd1abbdcbc7a 100644
--- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
+++ b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
@@ -1,3 +1,6 @@
+#ifndef STARTUP_INC_INCLUDED
+#define STARTUP_INC_INCLUDED
+
 #include <hwregs/asm/reg_map_asm.h>
 #include <hwregs/asm/bif_core_defs_asm.h>
 #include <hwregs/asm/gio_defs_asm.h>
@@ -75,3 +78,5 @@
 	move.d $r10, [$r11]
 #endif
 	.endm
+
+#endif