Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...

26 files changed, 0 insertions, 14033 deletions

diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
deleted file mode 100644
index 7d6a8b8926ba..000000000000
--- a/arch/blackfin/mach-bf609/Kconfig
+++ /dev/null
@@ -1,1684 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF60x
-	def_bool y
-	depends on (BF609)
-	select IRQ_PREFLOW_FASTEOI
-
-if (BF60x)
-
-source "arch/blackfin/mach-bf609/boards/Kconfig"
-
-menu "BF609 Specific Configuration"
-
-config SEC_IRQ_PRIORITY_LEVELS
-	int "SEC interrupt priority levels"
-	default 7
-	range 0 7
-	help
-	  Divide the total number of interrupt priority levels into sub-levels.
-	  There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
-
-config L1_PARITY_CHECK
-	bool "Enable L1 parity check"
-	default n
-	help
-	  Enable the L1 parity check in L1 sram. A fault event is raised
-	  when L1 parity error is found.
-
-comment "System Cross Bar Priority Assignment"
-
-config SCB_PRIORITY
-	bool "Init System Cross Bar Priority"
-	default n
-
-menuconfig	SCB0_MI0
-	bool "SCB0 Master Interface 0 (DDR)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	Core 0	-- 0
-	Core 1	-- 2
-	SCB1	-- 9
-	SCB2	-- 10
-	SCB3	-- 11
-	SCB4	-- 12
-	SCB5	-- 5
-	SCB6	-- 6
-	SCB7	-- 8
-	SCB8	-- 7
-	SCB9	-- 4
-	USB	-- 13
-
-if SCB0_MI0
-
-config SCB0_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI0_SLOT10
-	int "Slot 10 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI0_SLOT11
-	int "Slot 11 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI0_SLOT12
-	int "Slot 12 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI0_SLOT13
-	int "Slot 13 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI0_SLOT14
-	int "Slot 14 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI0_SLOT15
-	int "Slot 15 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI0_SLOT16
-	int "Slot 16 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI0_SLOT17
-	int "Slot 17 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI0_SLOT18
-	int "Slot 18 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI0_SLOT19
-	int "Slot 19 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI0_SLOT20
-	int "Slot 20 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI0_SLOT21
-	int "Slot 21 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI0_SLOT22
-	int "Slot 22 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI0_SLOT23
-	int "Slot 23 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI0_SLOT24
-	int "Slot 24 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI0_SLOT25
-	int "Slot 25 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI0_SLOT26
-	int "Slot 26 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI0_SLOT27
-	int "Slot 27 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI0_SLOT28
-	int "Slot 28 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI0_SLOT29
-	int "Slot 29 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI0_SLOT30
-	int "Slot 30 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI0_SLOT31
-	int "Slot 31 slave interface id"
-	default 13
-	range 0 13
-
-endif # SCB0_MI0
-
-menuconfig	SCB0_MI1
-	bool "SCB0 Master Interface 1 (SMC)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	Core 0	-- 0
-	Core 1	-- 2
-	SCB1	-- 9
-	SCB2	-- 10
-	SCB3	-- 11
-	SCB4	-- 12
-	SCB5	-- 5
-	SCB6	-- 6
-	SCB7	-- 8
-	SCB8	-- 7
-	SCB9	-- 4
-	USB	-- 13
-
-if SCB0_MI1
-
-config SCB0_MI1_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI1_SLOT1
-	int "Slot 1 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI1_SLOT2
-	int "Slot 2 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI1_SLOT3
-	int "Slot 3 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI1_SLOT4
-	int "Slot 4 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI1_SLOT5
-	int "Slot 5 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI1_SLOT6
-	int "Slot 6 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI1_SLOT7
-	int "Slot 7 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI1_SLOT8
-	int "Slot 8 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI1_SLOT9
-	int "Slot 9 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI1_SLOT10
-	int "Slot 10 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI1_SLOT11
-	int "Slot 11 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI1_SLOT12
-	int "Slot 12 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI1_SLOT13
-	int "Slot 13 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI1_SLOT14
-	int "Slot 14 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI1_SLOT15
-	int "Slot 15 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI1_SLOT16
-	int "Slot 16 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI1_SLOT17
-	int "Slot 17 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI1_SLOT18
-	int "Slot 18 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI1_SLOT19
-	int "Slot 19 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI1_SLOT20
-	int "Slot 20 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI1_SLOT21
-	int "Slot 21 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI1_SLOT22
-	int "Slot 22 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI1_SLOT23
-	int "Slot 23 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI1_SLOT24
-	int "Slot 24 slave interface id"
-	default 0
-	range 0 13
-
-config SCB0_MI1_SLOT25
-	int "Slot 25 slave interface id"
-	default 2
-	range 0 13
-
-config SCB0_MI1_SLOT26
-	int "Slot 26 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI1_SLOT27
-	int "Slot 27 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI1_SLOT28
-	int "Slot 28 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI1_SLOT29
-	int "Slot 29 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI1_SLOT30
-	int "Slot 30 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI1_SLOT31
-	int "Slot 31 slave interface id"
-	default 13
-	range 0 13
-
-endif # SCB0_MI1
-
-menuconfig	SCB0_MI2
-	bool "SCB0 Master Interface 2 (Data L2)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	Core 0	-- 0
-	Core 1	-- 2
-	SCB1	-- 9
-	SCB2	-- 10
-	SCB3	-- 11
-	SCB4	-- 12
-	SCB5	-- 5
-	SCB6	-- 6
-	SCB7	-- 8
-	SCB8	-- 7
-	SCB9	-- 4
-	USB	-- 13
-
-if SCB0_MI2
-
-config SCB0_MI2_SLOT0
-	int "Slot 0 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI2_SLOT1
-	int "Slot 1 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI2_SLOT2
-	int "Slot 2 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI2_SLOT3
-	int "Slot 3 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI2_SLOT4
-	int "Slot 4 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI2_SLOT5
-	int "Slot 5 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI2_SLOT6
-	int "Slot 6 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI2_SLOT7
-	int "Slot 7 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI2_SLOT8
-	int "Slot 8 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI2_SLOT9
-	int "Slot 9 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI2_SLOT10
-	int "Slot 10 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI2_SLOT11
-	int "Slot 11 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI2_SLOT12
-	int "Slot 12 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI2_SLOT13
-	int "Slot 13 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI2_SLOT14
-	int "Slot 14 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI2_SLOT15
-	int "Slot 15 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI2_SLOT16
-	int "Slot 16 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI2_SLOT17
-	int "Slot 17 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI2_SLOT18
-	int "Slot 18 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI2_SLOT19
-	int "Slot 19 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI2_SLOT20
-	int "Slot 20 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI2_SLOT21
-	int "Slot 21 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI2_SLOT22
-	int "Slot 22 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI2_SLOT23
-	int "Slot 23 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI2_SLOT24
-	int "Slot 24 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI2_SLOT25
-	int "Slot 25 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI2_SLOT26
-	int "Slot 26 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI2_SLOT27
-	int "Slot 27 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI2_SLOT28
-	int "Slot 28 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI2_SLOT29
-	int "Slot 29 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI2_SLOT30
-	int "Slot 30 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI2_SLOT31
-	int "Slot 31 slave interface id"
-	default 7
-	range 0 13
-
-endif # SCB0_MI2
-
-menuconfig	SCB0_MI3
-	bool "SCB0 Master Interface 3 (L1A)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	Core 0	-- 0
-	Core 1	-- 2
-	SCB1	-- 9
-	SCB2	-- 10
-	SCB3	-- 11
-	SCB4	-- 12
-	SCB5	-- 5
-	SCB6	-- 6
-	SCB7	-- 8
-	SCB8	-- 7
-	SCB9	-- 4
-	USB	-- 13
-
-if SCB0_MI3
-
-config SCB0_MI3_SLOT0
-	int "Slot 0 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI3_SLOT1
-	int "Slot 1 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI3_SLOT2
-	int "Slot 2 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI3_SLOT3
-	int "Slot 3 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI3_SLOT4
-	int "Slot 4 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI3_SLOT5
-	int "Slot 5 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI3_SLOT6
-	int "Slot 6 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI3_SLOT7
-	int "Slot 7 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI3_SLOT8
-	int "Slot 8 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI3_SLOT9
-	int "Slot 9 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI3_SLOT10
-	int "Slot 10 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI3_SLOT11
-	int "Slot 11 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI3_SLOT12
-	int "Slot 12 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI3_SLOT13
-	int "Slot 13 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI3_SLOT14
-	int "Slot 14 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI3_SLOT15
-	int "Slot 15 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI3_SLOT16
-	int "Slot 16 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI3_SLOT17
-	int "Slot 17 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI3_SLOT18
-	int "Slot 18 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI3_SLOT19
-	int "Slot 19 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI3_SLOT20
-	int "Slot 20 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI3_SLOT21
-	int "Slot 21 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI3_SLOT22
-	int "Slot 22 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI3_SLOT23
-	int "Slot 23 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI3_SLOT24
-	int "Slot 24 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI3_SLOT25
-	int "Slot 25 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI3_SLOT26
-	int "Slot 26 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI3_SLOT27
-	int "Slot 27 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI3_SLOT28
-	int "Slot 28 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI3_SLOT29
-	int "Slot 29 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI3_SLOT30
-	int "Slot 30 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI3_SLOT31
-	int "Slot 31 slave interface id"
-	default 7
-	range 0 13
-
-endif # SCB0_MI3
-
-menuconfig	SCB0_MI4
-	bool "SCB0 Master Interface 4 (L1B)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	Core 0	-- 0
-	Core 1	-- 2
-	SCB1	-- 9
-	SCB2	-- 10
-	SCB3	-- 11
-	SCB4	-- 12
-	SCB5	-- 5
-	SCB6	-- 6
-	SCB7	-- 8
-	SCB8	-- 7
-	SCB9	-- 4
-	USB	-- 13
-
-if SCB0_MI4
-
-config SCB0_MI4_SLOT0
-	int "Slot 0 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI4_SLOT1
-	int "Slot 1 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI4_SLOT2
-	int "Slot 2 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI4_SLOT3
-	int "Slot 3 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI4_SLOT4
-	int "Slot 4 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI4_SLOT5
-	int "Slot 5 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI4_SLOT6
-	int "Slot 6 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI4_SLOT7
-	int "Slot 7 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI4_SLOT8
-	int "Slot 8 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI4_SLOT9
-	int "Slot 9 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI4_SLOT10
-	int "Slot 10 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI4_SLOT11
-	int "Slot 11 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI4_SLOT12
-	int "Slot 12 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI4_SLOT13
-	int "Slot 13 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI4_SLOT14
-	int "Slot 14 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI4_SLOT15
-	int "Slot 15 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI4_SLOT16
-	int "Slot 16 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI4_SLOT17
-	int "Slot 17 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI4_SLOT18
-	int "Slot 18 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI4_SLOT19
-	int "Slot 19 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI4_SLOT20
-	int "Slot 20 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI4_SLOT21
-	int "Slot 21 slave interface id"
-	default 5
-	range 0 13
-
-config SCB0_MI4_SLOT22
-	int "Slot 22 slave interface id"
-	default 6
-	range 0 13
-
-config SCB0_MI4_SLOT23
-	int "Slot 23 slave interface id"
-	default 7
-	range 0 13
-
-config SCB0_MI4_SLOT24
-	int "Slot 24 slave interface id"
-	default 8
-	range 0 13
-
-config SCB0_MI4_SLOT25
-	int "Slot 25 slave interface id"
-	default 9
-	range 0 13
-
-config SCB0_MI4_SLOT26
-	int "Slot 26 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI4_SLOT27
-	int "Slot 27 slave interface id"
-	default 11
-	range 0 13
-
-config SCB0_MI4_SLOT28
-	int "Slot 28 slave interface id"
-	default 13
-	range 0 13
-
-config SCB0_MI4_SLOT29
-	int "Slot 29 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI4_SLOT30
-	int "Slot 30 slave interface id"
-	default 4
-	range 0 13
-
-config SCB0_MI4_SLOT31
-	int "Slot 31 slave interface id"
-	default 7
-	range 0 13
-
-endif # SCB0_MI4
-
-menuconfig	SCB0_MI5
-	bool "SCB0 Master Interface 5 (SMMR)"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	MMR0	-- 1
-	MMR1	-- 3
-	SCB2	-- 10
-	SCB4	-- 12
-
-if SCB0_MI5
-
-config SCB0_MI5_SLOT0
-	int "Slot 0 slave interface id"
-	default 1
-	range 0 13
-
-config SCB0_MI5_SLOT1
-	int "Slot 1 slave interface id"
-	default 3
-	range 0 13
-
-config SCB0_MI5_SLOT2
-	int "Slot 2 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI5_SLOT3
-	int "Slot 3 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI5_SLOT4
-	int "Slot 4 slave interface id"
-	default 1
-	range 0 13
-
-config SCB0_MI5_SLOT5
-	int "Slot 5 slave interface id"
-	default 3
-	range 0 13
-
-config SCB0_MI5_SLOT6
-	int "Slot 6 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI5_SLOT7
-	int "Slot 7 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI5_SLOT8
-	int "Slot 8 slave interface id"
-	default 1
-	range 0 13
-
-config SCB0_MI5_SLOT9
-	int "Slot 9 slave interface id"
-	default 3
-	range 0 13
-
-config SCB0_MI5_SLOT10
-	int "Slot 10 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI5_SLOT11
-	int "Slot 11 slave interface id"
-	default 12
-	range 0 13
-
-config SCB0_MI5_SLOT12
-	int "Slot 12 slave interface id"
-	default 1
-	range 0 13
-
-config SCB0_MI5_SLOT13
-	int "Slot 13 slave interface id"
-	default 3
-	range 0 13
-
-config SCB0_MI5_SLOT14
-	int "Slot 14 slave interface id"
-	default 10
-	range 0 13
-
-config SCB0_MI5_SLOT15
-	int "Slot 15 slave interface id"
-	default 12
-	range 0 13
-
-endif # SCB0_MI5
-
-menuconfig	SCB1_MI0
-	bool "SCB1 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	SPORT0A	-- 0
-	SPORT0B	-- 1
-	SPORT1A	-- 2
-	SPORT1B	-- 3
-	SPORT2A	-- 4
-	SPORT2B	-- 5
-	SPI0TX	-- 6
-	SPI0RX	-- 7
-	SPI1TX	-- 8
-	SPI1RX	-- 9
-
-if SCB1_MI0
-
-config SCB1_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 9
-
-config SCB1_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 9
-
-config SCB1_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 9
-
-config SCB1_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 9
-
-config SCB1_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 4
-	range 0 9
-
-config SCB1_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 5
-	range 0 9
-
-config SCB1_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 6
-	range 0 9
-
-config SCB1_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 7
-	range 0 9
-
-config SCB1_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 8
-	range 0 9
-
-config SCB1_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 9
-	range 0 9
-
-config SCB1_MI0_SLOT10
-	int "Slot 10 slave interface id"
-	default 0
-	range 0 9
-
-config SCB1_MI0_SLOT11
-	int "Slot 11 slave interface id"
-	default 1
-	range 0 9
-
-config SCB1_MI0_SLOT12
-	int "Slot 12 slave interface id"
-	default 2
-	range 0 9
-
-config SCB1_MI0_SLOT13
-	int "Slot 13 slave interface id"
-	default 3
-	range 0 9
-
-config SCB1_MI0_SLOT14
-	int "Slot 14 slave interface id"
-	default 4
-	range 0 9
-
-config SCB1_MI0_SLOT15
-	int "Slot 15 slave interface id"
-	default 5
-	range 0 9
-
-config SCB1_MI0_SLOT16
-	int "Slot 16 slave interface id"
-	default 6
-	range 0 13
-
-config SCB1_MI0_SLOT17
-	int "Slot 17 slave interface id"
-	default 7
-	range 0 13
-
-config SCB1_MI0_SLOT18
-	int "Slot 18 slave interface id"
-	default 8
-	range 0 13
-
-config SCB1_MI0_SLOT19
-	int "Slot 19 slave interface id"
-	default 9
-	range 0 13
-
-endif # SCB1_MI0
-
-menuconfig	SCB2_MI0
-	bool "SCB2 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	RSI	-- 0
-	SDU DMA	-- 1
-	SDU	-- 2
-	EMAC0	-- 3
-	EMAC1	-- 4
-
-if SCB2_MI0
-
-config SCB2_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 4
-
-config SCB2_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 4
-
-config SCB2_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 4
-
-config SCB2_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 4
-
-config SCB2_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 4
-	range 0 4
-
-config SCB2_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 0
-	range 0 4
-
-config SCB2_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 1
-	range 0 4
-
-config SCB2_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 2
-	range 0 4
-
-config SCB2_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 3
-	range 0 4
-
-config SCB2_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 4
-	range 0 4
-
-endif # SCB2_MI0
-
-menuconfig	SCB3_MI0
-	bool "SCB3 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	LP0	-- 0
-	LP1	-- 1
-	LP2	-- 2
-	LP3	-- 3
-	UART0TX	-- 4
-	UART0RX	-- 5
-	UART1TX	-- 4
-	UART1RX	-- 5
-
-if SCB3_MI0
-
-config SCB3_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 7
-
-config SCB3_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 7
-
-config SCB3_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 7
-
-config SCB3_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 7
-
-config SCB3_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 4
-	range 0 7
-
-config SCB3_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 5
-	range 0 7
-
-config SCB3_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 6
-	range 0 7
-
-config SCB3_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 7
-	range 0 7
-
-config SCB3_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 0
-	range 0 7
-
-config SCB3_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 1
-	range 0 7
-
-config SCB3_MI0_SLOT10
-	int "Slot 10 slave interface id"
-	default 2
-	range 0 7
-
-config SCB3_MI0_SLOT11
-	int "Slot 11 slave interface id"
-	default 3
-	range 0 7
-
-config SCB3_MI0_SLOT12
-	int "Slot 12 slave interface id"
-	default 4
-	range 0 7
-
-config SCB3_MI0_SLOT13
-	int "Slot 13 slave interface id"
-	default 5
-	range 0 7
-
-config SCB3_MI0_SLOT14
-	int "Slot 14 slave interface id"
-	default 6
-	range 0 7
-
-config SCB3_MI0_SLOT15
-	int "Slot 15 slave interface id"
-	default 7
-	range 0 7
-
-endif # SCB3_MI0
-
-menuconfig	SCB4_MI0
-	bool "SCB4 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	MDA21	-- 0
-	MDA22	-- 1
-	MDA23	-- 2
-	MDA24	-- 3
-	MDA25	-- 4
-	MDA26	-- 5
-	MDA27	-- 6
-	MDA28	-- 7
-
-if SCB4_MI0
-
-config SCB4_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 7
-
-config SCB4_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 7
-
-config SCB4_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 7
-
-config SCB4_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 7
-
-config SCB4_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 4
-	range 0 7
-
-config SCB4_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 5
-	range 0 7
-
-config SCB4_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 6
-	range 0 7
-
-config SCB4_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 7
-	range 0 7
-
-config SCB4_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 0
-	range 0 7
-
-config SCB4_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 1
-	range 0 7
-
-config SCB4_MI0_SLOT10
-	int "Slot 10 slave interface id"
-	default 2
-	range 0 7
-
-config SCB4_MI0_SLOT11
-	int "Slot 11 slave interface id"
-	default 3
-	range 0 7
-
-config SCB4_MI0_SLOT12
-	int "Slot 12 slave interface id"
-	default 4
-	range 0 7
-
-config SCB4_MI0_SLOT13
-	int "Slot 13 slave interface id"
-	default 5
-	range 0 7
-
-config SCB4_MI0_SLOT14
-	int "Slot 14 slave interface id"
-	default 6
-	range 0 7
-
-config SCB4_MI0_SLOT15
-	int "Slot 15 slave interface id"
-	default 7
-	range 0 7
-
-endif # SCB4_MI0
-
-menuconfig	SCB5_MI0
-	bool "SCB5 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	PPI0 MDA29	-- 0
-	PPI0 MDA30	-- 1
-	PPI2 MDA31	-- 2
-	PPI2 MDA32	-- 3
-
-if SCB5_MI0
-
-config SCB5_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 3
-
-config SCB5_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 3
-
-config SCB5_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 3
-
-config SCB5_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 3
-
-config SCB5_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 0
-	range 0 3
-
-config SCB5_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 1
-	range 0 3
-
-config SCB5_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 2
-	range 0 3
-
-config SCB5_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 3
-	range 0 3
-
-endif # SCB5_MI0
-
-menuconfig	SCB6_MI0
-	bool "SCB6 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	PPI1 MDA33	-- 0
-	PPI1 MDA34	-- 1
-
-if SCB6_MI0
-
-config SCB6_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 1
-
-config SCB6_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 1
-
-config SCB6_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 0
-	range 0 1
-
-config SCB6_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 1
-	range 0 1
-
-endif # SCB6_MI0
-
-menuconfig	SCB7_MI0
-	bool "SCB7 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	PIXC0	-- 0
-	PIXC1	-- 1
-	PIXC2	-- 2
-
-if SCB7_MI0
-
-config SCB7_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 2
-
-config SCB7_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 2
-
-config SCB7_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 2
-
-config SCB7_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 0
-	range 0 2
-
-config SCB7_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 1
-	range 0 2
-
-config SCB7_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 2
-	range 0 2
-
-endif # SCB7_MI0
-
-menuconfig	SCB8_MI0
-	bool "SCB8 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	PVP CPDOB	-- 0
-	PVP CPDOC	-- 1
-	PVP CPCO	-- 2
-	PVP CPCI	-- 3
-
-if SCB8_MI0
-
-config SCB8_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 3
-
-config SCB8_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 3
-
-config SCB8_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 3
-
-config SCB8_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 3
-
-config SCB8_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 0
-	range 0 3
-
-config SCB8_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 1
-	range 0 3
-
-config SCB8_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 2
-	range 0 3
-
-config SCB8_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 3
-	range 0 3
-
-endif # SCB8_MI0
-
-menuconfig	SCB9_MI0
-	bool "SCB9 Master Interface 0"
-	default n
-	depends on SCB_PRIORITY
-	help
-	The slave interface id of each slot should be set according following table.
-	PVP MPDO	-- 0
-	PVP MPDI	-- 1
-	PVP MPCO	-- 2
-	PVP MPCI	-- 3
-	PVP CPDOA	-- 4
-
-if SCB9_MI0
-
-config SCB9_MI0_SLOT0
-	int "Slot 0 slave interface id"
-	default 0
-	range 0 4
-
-config SCB9_MI0_SLOT1
-	int "Slot 1 slave interface id"
-	default 1
-	range 0 4
-
-config SCB9_MI0_SLOT2
-	int "Slot 2 slave interface id"
-	default 2
-	range 0 4
-
-config SCB9_MI0_SLOT3
-	int "Slot 3 slave interface id"
-	default 3
-	range 0 4
-
-config SCB9_MI0_SLOT4
-	int "Slot 4 slave interface id"
-	default 4
-	range 0 4
-
-config SCB9_MI0_SLOT5
-	int "Slot 5 slave interface id"
-	default 0
-	range 0 4
-
-config SCB9_MI0_SLOT6
-	int "Slot 6 slave interface id"
-	default 1
-	range 0 4
-
-config SCB9_MI0_SLOT7
-	int "Slot 7 slave interface id"
-	default 2
-	range 0 4
-
-config SCB9_MI0_SLOT8
-	int "Slot 8 slave interface id"
-	default 3
-	range 0 4
-
-config SCB9_MI0_SLOT9
-	int "Slot 9 slave interface id"
-	default 4
-	range 0 4
-
-endif # SCB9_MI0
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
deleted file mode 100644
index 60ffaf85d303..000000000000
--- a/arch/blackfin/mach-bf609/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# arch/blackfin/mach-bf609/Makefile
-#
-
-obj-y := dma.o clock.o ints-priority.o
-obj-$(CONFIG_PM) += pm.o dpm.o
-obj-$(CONFIG_SCB_PRIORITY) += scb.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
deleted file mode 100644
index 350154b2a3ee..000000000000
--- a/arch/blackfin/mach-bf609/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
-	prompt "System type"
-	default BFIN609_EZKIT
-	help
-	  Select your board!
-
-config BFIN609_EZKIT
-	bool "BF609-EZKIT"
-	help
-	  BFIN609-EZKIT board support.
-	  
-endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
deleted file mode 100644
index 11f98b0882ea..000000000000
--- a/arch/blackfin/mach-bf609/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf609/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN609_EZKIT)            += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
deleted file mode 100644
index 51157a255824..000000000000
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ /dev/null
@@ -1,2191 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *                2005 National ICT Australia (NICTA)
- *                      Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF609-EZKIT";
-
-/*
- *  Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
-	[0] = {
-		.start  = 0x2C0C0000,
-		.end    = 0x2C0C0000 + 0xfffff,
-		.flags  = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start  = IRQ_PG7,
-		.end    = IRQ_PG7,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-static struct isp1760_platform_data isp1760_priv = {
-	.is_isp1761 = 0,
-	.bus_width_16 = 1,
-	.port1_otg = 0,
-	.analog_oc = 0,
-	.dack_polarity_high = 0,
-	.dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
-	.name           = "isp1760",
-	.id             = 0,
-	.dev = {
-		.platform_data = &isp1760_priv,
-	},
-	.num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
-	.resource       = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
-	/*.rotary_up_key     = KEY_UP,*/
-	/*.rotary_down_key   = KEY_DOWN,*/
-	.rotary_rel_code   = REL_WHEEL,
-	.rotary_button_key = KEY_ENTER,
-	.debounce	   = 10,	/* 0..17 */
-	.mode		   = ROT_QUAD_ENC | ROT_DEBE,
-};
-
-static struct resource bfin_rotary_resources[] = {
-	{
-		.start = CNT_CONFIG,
-		.end   = CNT_CONFIG + 0xff,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_CNT,
-		.end = IRQ_CNT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_rotary_device = {
-	.name		= "bfin-rotary",
-	.id		= -1,
-	.num_resources 	= ARRAY_SIZE(bfin_rotary_resources),
-	.resource 	= bfin_rotary_resources,
-	.dev		= {
-		.platform_data = &bfin_rotary_data,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-#include <linux/stmmac.h>
-#include <linux/phy.h>
-
-static struct stmmac_mdio_bus_data phy_private_data = {
-	.phy_mask = 1,
-};
-
-static struct stmmac_dma_cfg eth_dma_cfg = {
-	.pbl	= 2,
-};
-
-int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
-{
-	bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
-	return 0;
-}
-
-static struct plat_stmmacenet_data eth_private_data = {
-	.has_gmac = 1,
-	.bus_id   = 0,
-	.enh_desc = 1,
-	.phy_addr = 1,
-	.mdio_bus_data = &phy_private_data,
-	.dma_cfg  = &eth_dma_cfg,
-	.force_thresh_dma_mode = 1,
-	.interface = PHY_INTERFACE_MODE_RMII,
-	.init = stmmac_ptp_clk_init,
-};
-
-static struct platform_device bfin_eth_device = {
-	.name           = "stmmaceth",
-	.id             = 0,
-	.num_resources  = 2,
-	.resource       = (struct resource[]) {
-		{
-			.start  = EMAC0_MACCFG,
-			.end    = EMAC0_MACCFG + 0x1274,
-			.flags  = IORESOURCE_MEM,
-		},
-		{
-			.name   = "macirq",
-			.start  = IRQ_EMAC0_STAT,
-			.end    = IRQ_EMAC0_STAT,
-			.flags  = IORESOURCE_IRQ,
-		},
-	},
-	.dev = {
-		.power.can_wakeup = 1,
-		.platform_data = &eth_private_data,
-	}
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
-	.x_axis_offset = 0,
-	.y_axis_offset = 0,
-	.z_axis_offset = 0,
-	.tap_threshold = 0x31,
-	.tap_duration = 0x10,
-	.tap_latency = 0x60,
-	.tap_window = 0xF0,
-	.tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
-	.act_axis_control = 0xFF,
-	.activity_threshold = 5,
-	.inactivity_threshold = 3,
-	.inactivity_time = 4,
-	.free_fall_threshold = 0x7,
-	.free_fall_time = 0x20,
-	.data_rate = 0x8,
-	.data_range = ADXL_FULL_RES,
-
-	.ev_type = EV_ABS,
-	.ev_code_x = ABS_X,		/* EV_REL */
-	.ev_code_y = ABS_Y,		/* EV_REL */
-	.ev_code_z = ABS_Z,		/* EV_REL */
-
-	.ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/*	.ev_code_ff = KEY_F,*/		/* EV_KEY */
-/*	.ev_code_act_inactivity = KEY_A,*/	/* EV_KEY */
-	.power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
-	.fifo_mode = ADXL_FIFO_STREAM,
-	.orientation_enable = ADXL_EN_ORIENTATION_3D,
-	.deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
-	.divisor_length = ADXL_LP_FILTER_DIVISOR_16,
-	/* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
-	.ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
-	.name = "rtc-bfin",
-	.id   = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
-	{
-		.start = UART0_REVID,
-		.end = UART0_RXDIV+4,
-		.flags = IORESOURCE_MEM,
-	},
-#ifdef CONFIG_EARLY_PRINTK
-	{
-		.start = PORTD_FER,
-		.end = PORTD_FER+2,
-		.flags = IORESOURCE_REG,
-	},
-	{
-		.start = PORTD_MUX,
-		.end = PORTD_MUX+3,
-		.flags = IORESOURCE_REG,
-	},
-#endif
-	{
-		.start = IRQ_UART0_TX,
-		.end = IRQ_UART0_TX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_UART0_RX,
-		.end = IRQ_UART0_RX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_UART0_STAT,
-		.end = IRQ_UART0_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_UART0_TX,
-		.end = CH_UART0_TX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_UART0_RX,
-		.end = CH_UART0_RX,
-		.flags = IORESOURCE_DMA,
-	},
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-	{	/* CTS pin -- 0 means not supported */
-		.start = GPIO_PD10,
-		.end = GPIO_PD10,
-		.flags = IORESOURCE_IO,
-	},
-	{	/* RTS pin -- 0 means not supported */
-		.start = GPIO_PD9,
-		.end = GPIO_PD9,
-		.flags = IORESOURCE_IO,
-	},
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
-	P_UART0_TX, P_UART0_RX,
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-	P_UART0_RTS, P_UART0_CTS,
-#endif
-	0
-};
-
-static struct platform_device bfin_uart0_device = {
-	.name = "bfin-uart",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
-	.resource = bfin_uart0_resources,
-	.dev = {
-		.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
-	},
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
-	{
-		.start = UART1_REVID,
-		.end = UART1_RXDIV+4,
-		.flags = IORESOURCE_MEM,
-	},
-#ifdef CONFIG_EARLY_PRINTK
-	{
-		.start = PORTG_FER_SET,
-		.end = PORTG_FER_SET+2,
-		.flags = IORESOURCE_REG,
-	},
-#endif
-	{
-		.start = IRQ_UART1_TX,
-		.end = IRQ_UART1_TX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_UART1_RX,
-		.end = IRQ_UART1_RX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_UART1_STAT,
-		.end = IRQ_UART1_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_UART1_TX,
-		.end = CH_UART1_TX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_UART1_RX,
-		.end = CH_UART1_RX,
-		.flags = IORESOURCE_DMA,
-	},
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-	{	/* CTS pin -- 0 means not supported */
-		.start = GPIO_PG13,
-		.end = GPIO_PG13,
-		.flags = IORESOURCE_IO,
-	},
-	{	/* RTS pin -- 0 means not supported */
-		.start = GPIO_PG10,
-		.end = GPIO_PG10,
-		.flags = IORESOURCE_IO,
-	},
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
-	P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-	P_UART1_RTS, P_UART1_CTS,
-#endif
-	0
-};
-
-static struct platform_device bfin_uart1_device = {
-	.name = "bfin-uart",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
-	.resource = bfin_uart1_resources,
-	.dev = {
-		.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
-	},
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
-	{
-		.start = 0xFFC00400,
-		.end = 0xFFC004FF,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_UART0_TX,
-		.end = IRQ_UART0_TX+1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_UART0_TX,
-		.end = CH_UART0_TX+1,
-		.flags = IORESOURCE_DMA,
-	},
-};
-static struct platform_device bfin_sir0_device = {
-	.name = "bfin_sir",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
-	.resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
-	{
-		.start = 0xFFC02000,
-		.end = 0xFFC020FF,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_UART1_TX,
-		.end = IRQ_UART1_TX+1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_UART1_TX,
-		.end = CH_UART1_TX+1,
-		.flags = IORESOURCE_DMA,
-	},
-};
-static struct platform_device bfin_sir1_device = {
-	.name = "bfin_sir",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
-	.resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
-	[0] = {
-		.start	= 0xFFCC1000,
-		.end	= 0xFFCC1398,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {	/* general IRQ */
-		.start	= IRQ_USB_STAT,
-		.end	= IRQ_USB_STAT,
-		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-		.name	= "mc"
-	},
-	[2] = {	/* DMA IRQ */
-		.start	= IRQ_USB_DMA,
-		.end	= IRQ_USB_DMA,
-		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-		.name	= "dma"
-	},
-};
-
-static struct musb_hdrc_config musb_config = {
-	.multipoint	= 1,
-	.dyn_fifo	= 0,
-	.dma		= 1,
-	.num_eps	= 16,
-	.dma_channels	= 8,
-	.clkin          = 48,           /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
-	.mode		= MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
-	.mode		= MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
-	.mode		= MUSB_PERIPHERAL,
-#endif
-	.config		= &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
-	.name		= "musb-blackfin",
-	.id		= 0,
-	.dev = {
-		.dma_mask		= &musb_dmamask,
-		.coherent_dma_mask	= 0xffffffff,
-		.platform_data		= &musb_plat,
-	},
-	.num_resources	= ARRAY_SIZE(musb_resources),
-	.resource	= musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
-	{
-		.start = SPORT0_TCR1,
-		.end = SPORT0_MRCS3+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_SPORT0_RX,
-		.end = IRQ_SPORT0_RX+1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_SPORT0_ERROR,
-		.end = IRQ_SPORT0_ERROR,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
-	P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-	P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
-	.name = "bfin-sport-uart",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
-	.resource = bfin_sport0_uart_resources,
-	.dev = {
-		.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
-	},
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
-	{
-		.start = SPORT1_TCR1,
-		.end = SPORT1_MRCS3+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_SPORT1_RX,
-		.end = IRQ_SPORT1_RX+1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_SPORT1_ERROR,
-		.end = IRQ_SPORT1_ERROR,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
-	P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-	P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
-	.name = "bfin-sport-uart",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
-	.resource = bfin_sport1_uart_resources,
-	.dev = {
-		.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
-	},
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
-	{
-		.start = SPORT2_TCR1,
-		.end = SPORT2_MRCS3+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_SPORT2_RX,
-		.end = IRQ_SPORT2_RX+1,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_SPORT2_ERROR,
-		.end = IRQ_SPORT2_ERROR,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
-	P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
-	P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
-	.name = "bfin-sport-uart",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
-	.resource = bfin_sport2_uart_resources,
-	.dev = {
-		.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
-	},
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
-	P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
-	{
-		.start = 0xFFC00A00,
-		.end = 0xFFC00FFF,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_CAN0_RX,
-		.end = IRQ_CAN0_RX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_CAN0_TX,
-		.end = IRQ_CAN0_TX,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_CAN0_STAT,
-		.end = IRQ_CAN0_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_can0_device = {
-	.name = "bfin_can",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_can0_resources),
-	.resource = bfin_can0_resources,
-	.dev = {
-		.platform_data = &bfin_can0_peripherals, /* Passed to driver */
-	},
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
-	{
-		.name = "bootloader(nand)",
-		.offset = 0,
-		.size = 0x80000,
-	}, {
-		.name = "linux kernel(nand)",
-		.offset = MTDPART_OFS_APPEND,
-		.size = 4 * 1024 * 1024,
-	},
-	{
-		.name = "file system(nand)",
-		.offset = MTDPART_OFS_APPEND,
-		.size = MTDPART_SIZ_FULL,
-	},
-};
-
-static struct bf5xx_nand_platform bfin_nand_platform = {
-	.data_width = NFC_NWIDTH_8,
-	.partitions = partition_info,
-	.nr_partitions = ARRAY_SIZE(partition_info),
-	.rd_dly = 3,
-	.wr_dly = 3,
-};
-
-static struct resource bfin_nand_resources[] = {
-	{
-		.start = 0xFFC03B00,
-		.end = 0xFFC03B4F,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = CH_NFC,
-		.end = CH_NFC,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_nand_device = {
-	.name = "bfin-nand",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_nand_resources),
-	.resource = bfin_nand_resources,
-	.dev = {
-		.platform_data = &bfin_nand_platform,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
-	.dma_chan = CH_RSI,
-	.irq_int0 = IRQ_RSI_INT0,
-	.pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bfin_sdh_device = {
-	.name = "bfin-sdh",
-	.id = 0,
-	.dev = {
-		.platform_data = &bfin_sdh_data,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
-	{
-		.name       = "bootloader(nor)",
-		.size       = 0x80000,
-		.offset     = 0,
-	}, {
-		.name       = "linux kernel(nor)",
-		.size       = 0x400000,
-		.offset     = MTDPART_OFS_APPEND,
-	}, {
-		.name       = "file system(nor)",
-		.size       = 0x1000000 - 0x80000 - 0x400000,
-		.offset     = MTDPART_OFS_APPEND,
-	},
-};
-
-int bf609_nor_flash_init(struct platform_device *pdev)
-{
-#define CONFIG_SMC_GCTL_VAL     0x00000010
-
-	bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
-	bfin_write32(SMC_B0CTL, 0x01002011);
-	bfin_write32(SMC_B0TIM, 0x08170977);
-	bfin_write32(SMC_B0ETIM, 0x00092231);
-	return 0;
-}
-
-void bf609_nor_flash_exit(struct platform_device *pdev)
-{
-	bfin_write32(SMC_GCTL, 0);
-}
-
-static struct physmap_flash_data ezkit_flash_data = {
-	.width      = 2,
-	.parts      = ezkit_partitions,
-	.init       = bf609_nor_flash_init,
-	.exit       = bf609_nor_flash_exit,
-	.nr_parts   = ARRAY_SIZE(ezkit_partitions),
-#ifdef CONFIG_ROMKERNEL
-	.probe_type = "map_rom",
-#endif
-};
-
-static struct resource ezkit_flash_resource = {
-	.start = 0xb0000000,
-	.end   = 0xb0ffffff,
-	.flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
-	.name          = "physmap-flash",
-	.id            = 0,
-	.dev = {
-		.platform_data = &ezkit_flash_data,
-	},
-	.num_resources = 1,
-	.resource      = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (w25q32) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
-	{
-		.name = "bootloader(spi)",
-		.size = 0x00080000,
-		.offset = 0,
-		.mask_flags = MTD_CAP_ROM
-	}, {
-		.name = "linux kernel(spi)",
-		.size = 0x00180000,
-		.offset = MTDPART_OFS_APPEND,
-	}, {
-		.name = "file system(spi)",
-		.size = MTDPART_SIZ_FULL,
-		.offset = MTDPART_OFS_APPEND,
-	}
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
-	.name = "m25p80",
-	.parts = bfin_spi_flash_partitions,
-	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
-	.type = "w25q32",
-};
-
-static struct adi_spi3_chip spi_flash_chip_info = {
-	.enable_dma = true,         /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-static struct adi_spi3_chip spidev_chip_info = {
-	.enable_dma = true,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-static struct platform_device bfin_pcm = {
-	.name = "bfin-i2s-pcm-audio",
-	.id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-#include <asm/bfin_sport3.h>
-static struct resource bfin_snd_resources[] = {
-	{
-		.start = SPORT0_CTL_A,
-		.end = SPORT0_CTL_A,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = SPORT0_CTL_B,
-		.end = SPORT0_CTL_B,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = CH_SPORT0_TX,
-		.end = CH_SPORT0_TX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_SPORT0_RX,
-		.end = CH_SPORT0_RX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = IRQ_SPORT0_TX_STAT,
-		.end = IRQ_SPORT0_TX_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = IRQ_SPORT0_RX_STAT,
-		.end = IRQ_SPORT0_RX_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static const unsigned short bfin_snd_pin[] = {
-	P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
-	P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static struct bfin_snd_platform_data bfin_snd_data = {
-	.pin_req = bfin_snd_pin,
-};
-
-static struct platform_device bfin_i2s = {
-	.name = "bfin-i2s",
-	.num_resources = ARRAY_SIZE(bfin_snd_resources),
-	.resource = bfin_snd_resources,
-	.dev = {
-		.platform_data = &bfin_snd_data,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
-	"bfin-i2s.0",
-	"spi0.76",
-};
-static struct platform_device bfin_ad1836_machine = {
-	.name = "bfin-snd-ad1836",
-	.id = -1,
-	.dev = {
-		.platform_data = (void *)ad1836_link,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-static struct platform_device adau1761_device = {
-	.name = "bfin-eval-adau1x61",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-#include <sound/adau17x1.h>
-static struct adau1761_platform_data adau1761_info = {
-	.lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
-	.headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
-	P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
-	P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
-	P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
-	P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
-	P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
-	P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
-#endif
-	P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
-	0,
-};
-
-static const struct ppi_info ppi_info = {
-	.type = PPI_TYPE_EPPI3,
-	.dma_ch = CH_EPPI0_CH0,
-	.irq_err = IRQ_EPPI0_STAT,
-	.base = (void __iomem *)EPPI0_STAT,
-	.pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
-	{
-		.index = 0,
-		.name = "Camera",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.std = V4L2_STD_UNKNOWN,
-	},
-};
-
-static struct bcap_route vs6624_routes[] = {
-	{
-		.input = 0,
-		.output = 0,
-	},
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PE4;
-
-static struct bfin_capture_config bfin_capture_data = {
-	.card_name = "BF609",
-	.inputs = vs6624_inputs,
-	.num_inputs = ARRAY_SIZE(vs6624_inputs),
-	.routes = vs6624_routes,
-	.i2c_adapter_id = 0,
-	.board_info = {
-		.type = "vs6624",
-		.addr = 0x10,
-		.platform_data = (void *)&vs6624_ce_pin,
-	},
-	.ppi_info = &ppi_info,
-	.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
-			| EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
-	.blank_pixels = 4,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-#include <media/i2c/adv7842.h>
-
-static struct v4l2_input adv7842_inputs[] = {
-	{
-		.index = 0,
-		.name = "Composite",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.std = V4L2_STD_ALL,
-		.capabilities = V4L2_IN_CAP_STD,
-	},
-	{
-		.index = 1,
-		.name = "S-Video",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.std = V4L2_STD_ALL,
-		.capabilities = V4L2_IN_CAP_STD,
-	},
-	{
-		.index = 2,
-		.name = "Component",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.capabilities = V4L2_IN_CAP_DV_TIMINGS,
-	},
-	{
-		.index = 3,
-		.name = "VGA",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.capabilities = V4L2_IN_CAP_DV_TIMINGS,
-	},
-	{
-		.index = 4,
-		.name = "HDMI",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.capabilities = V4L2_IN_CAP_DV_TIMINGS,
-	},
-};
-
-static struct bcap_route adv7842_routes[] = {
-	{
-		.input = 3,
-		.output = 0,
-		.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
-				| EPPI_CTL_ACTIVE656),
-	},
-	{
-		.input = 4,
-		.output = 0,
-	},
-	{
-		.input = 2,
-		.output = 0,
-	},
-	{
-		.input = 1,
-		.output = 0,
-	},
-	{
-		.input = 0,
-		.output = 1,
-		.ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
-				| EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
-				| EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
-	},
-};
-
-static struct adv7842_output_format adv7842_opf[] = {
-	{
-		.op_ch_sel = ADV7842_OP_CH_SEL_BRG,
-		.op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
-		.blank_data = 1,
-		.insert_av_codes = 1,
-	},
-	{
-		.op_ch_sel = ADV7842_OP_CH_SEL_RGB,
-		.op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
-		.blank_data = 1,
-	},
-};
-
-static struct adv7842_platform_data adv7842_data = {
-	.opf = adv7842_opf,
-	.num_opf = ARRAY_SIZE(adv7842_opf),
-	.ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
-	.prim_mode = ADV7842_PRIM_MODE_SDP,
-	.vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
-	.hdmi_free_run_enable = 1,
-	.sdp_free_run_auto = 1,
-	.llc_dll_phase = 0x10,
-	.i2c_sdp_io = 0x40,
-	.i2c_sdp = 0x41,
-	.i2c_cp = 0x42,
-	.i2c_vdp = 0x43,
-	.i2c_afe = 0x44,
-	.i2c_hdmi = 0x45,
-	.i2c_repeater = 0x46,
-	.i2c_edid = 0x47,
-	.i2c_infoframe = 0x48,
-	.i2c_cec = 0x49,
-	.i2c_avlink = 0x4a,
-};
-
-static struct bfin_capture_config bfin_capture_data = {
-	.card_name = "BF609",
-	.inputs = adv7842_inputs,
-	.num_inputs = ARRAY_SIZE(adv7842_inputs),
-	.routes = adv7842_routes,
-	.i2c_adapter_id = 0,
-	.board_info = {
-		.type = "adv7842",
-		.addr = 0x20,
-		.platform_data = (void *)&adv7842_data,
-	},
-	.ppi_info = &ppi_info,
-	.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
-			| EPPI_CTL_ACTIVE656),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
-	.name = "bfin_capture",
-	.dev = {
-		.platform_data = &bfin_capture_data,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_display.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req_disp[] = {
-	P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
-	P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
-	P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
-	P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-	P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
-	0,
-};
-
-static const struct ppi_info ppi_info = {
-	.type = PPI_TYPE_EPPI3,
-	.dma_ch = CH_EPPI0_CH0,
-	.irq_err = IRQ_EPPI0_STAT,
-	.base = (void __iomem *)EPPI0_STAT,
-	.pin_req = ppi_req_disp,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-#include <media/i2c/adv7511.h>
-
-static struct v4l2_output adv7511_outputs[] = {
-	{
-		.index = 0,
-		.name = "HDMI",
-		.type = V4L2_INPUT_TYPE_CAMERA,
-		.capabilities = V4L2_OUT_CAP_DV_TIMINGS,
-	},
-};
-
-static struct disp_route adv7511_routes[] = {
-	{
-		.output = 0,
-	},
-};
-
-static struct adv7511_platform_data adv7511_data = {
-	.edid_addr = 0x7e,
-};
-
-static struct bfin_display_config bfin_display_data = {
-	.card_name = "BF609",
-	.outputs = adv7511_outputs,
-	.num_outputs = ARRAY_SIZE(adv7511_outputs),
-	.routes = adv7511_routes,
-	.i2c_adapter_id = 0,
-	.board_info = {
-		.type = "adv7511",
-		.addr = 0x39,
-		.platform_data = (void *)&adv7511_data,
-	},
-	.ppi_info = &ppi_info,
-	.ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
-			| EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
-			| EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
-			| EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
-#include <media/i2c/adv7343.h>
-
-static struct v4l2_output adv7343_outputs[] = {
-	{
-		.index = 0,
-		.name = "Composite",
-		.type = V4L2_OUTPUT_TYPE_ANALOG,
-		.std = V4L2_STD_ALL,
-		.capabilities = V4L2_OUT_CAP_STD,
-	},
-	{
-		.index = 1,
-		.name = "S-Video",
-		.type = V4L2_OUTPUT_TYPE_ANALOG,
-		.std = V4L2_STD_ALL,
-		.capabilities = V4L2_OUT_CAP_STD,
-	},
-	{
-		.index = 2,
-		.name = "Component",
-		.type = V4L2_OUTPUT_TYPE_ANALOG,
-		.std = V4L2_STD_ALL,
-		.capabilities = V4L2_OUT_CAP_STD,
-	},
-
-};
-
-static struct disp_route adv7343_routes[] = {
-	{
-		.output = ADV7343_COMPOSITE_ID,
-	},
-	{
-		.output = ADV7343_SVIDEO_ID,
-	},
-	{
-		.output = ADV7343_COMPONENT_ID,
-	},
-};
-
-static struct adv7343_platform_data adv7343_data = {
-	.mode_config = {
-		.sleep_mode = false,
-		.pll_control = false,
-		.dac_1 = true,
-		.dac_2 = true,
-		.dac_3 = true,
-		.dac_4 = true,
-		.dac_5 = true,
-		.dac_6 = true,
-	},
-	.sd_config = {
-		.sd_dac_out1 = false,
-		.sd_dac_out2 = false,
-	},
-};
-
-static struct bfin_display_config bfin_display_data = {
-	.card_name = "BF609",
-	.outputs = adv7343_outputs,
-	.num_outputs = ARRAY_SIZE(adv7343_outputs),
-	.routes = adv7343_routes,
-	.i2c_adapter_id = 0,
-	.board_info = {
-		.type = "adv7343",
-		.addr = 0x2b,
-		.platform_data = (void *)&adv7343_data,
-	},
-	.ppi_info = &ppi_info_disp,
-	.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
-			| EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
-			| EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-static struct platform_device bfin_display_device = {
-	.name = "bfin_display",
-	.dev = {
-		.platform_data = &bfin_display_data,
-	},
-};
-#endif
-
-#if defined(CONFIG_FB_BF609_NL8048) \
-	|| defined(CONFIG_FB_BF609_NL8048_MODULE)
-static struct resource nl8048_resources[] = {
-	{
-		.start = EPPI2_STAT,
-		.end = EPPI2_STAT,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = CH_EPPI2_CH0,
-		.end = CH_EPPI2_CH0,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = IRQ_EPPI2_STAT,
-		.end = IRQ_EPPI2_STAT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-static struct platform_device bfin_fb_device = {
-	.name = "bf609_nl8048",
-	.num_resources = ARRAY_SIZE(nl8048_resources),
-	.resource = nl8048_resources,
-	.dev = {
-		.platform_data = (void *)GPIO_PC15,
-	},
-};
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-#define BFIN_CRC_NAME "bfin-crc"
-
-static struct resource bfin_crc0_resources[] = {
-	{
-		.start = REG_CRC0_CTL,
-		.end = REG_CRC0_REVID+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_CRC0_DCNTEXP,
-		.end = IRQ_CRC0_DCNTEXP,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_MEM_STREAM0_SRC_CRC0,
-		.end = CH_MEM_STREAM0_SRC_CRC0,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_MEM_STREAM0_DEST_CRC0,
-		.end = CH_MEM_STREAM0_DEST_CRC0,
-		.flags = IORESOURCE_DMA,
-	},
-};
-
-static struct platform_device bfin_crc0_device = {
-	.name = BFIN_CRC_NAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_crc0_resources),
-	.resource = bfin_crc0_resources,
-};
-
-static struct resource bfin_crc1_resources[] = {
-	{
-		.start = REG_CRC1_CTL,
-		.end = REG_CRC1_REVID+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_CRC1_DCNTEXP,
-		.end = IRQ_CRC1_DCNTEXP,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_MEM_STREAM1_SRC_CRC1,
-		.end = CH_MEM_STREAM1_SRC_CRC1,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_MEM_STREAM1_DEST_CRC1,
-		.end = CH_MEM_STREAM1_DEST_CRC1,
-		.flags = IORESOURCE_DMA,
-	},
-};
-
-static struct platform_device bfin_crc1_device = {
-	.name = BFIN_CRC_NAME,
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_crc1_resources),
-	.resource = bfin_crc1_resources,
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-#define BFIN_CRYPTO_CRC_NAME		"bfin-hmac-crc"
-#define BFIN_CRYPTO_CRC_POLY_DATA	0x5c5c5c5c
-
-static struct resource bfin_crypto_crc_resources[] = {
-	{
-		.start = REG_CRC0_CTL,
-		.end = REG_CRC0_REVID+4,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_CRC0_DCNTEXP,
-		.end = IRQ_CRC0_DCNTEXP,
-		.flags = IORESOURCE_IRQ,
-	},
-	{
-		.start = CH_MEM_STREAM0_SRC_CRC0,
-		.end = CH_MEM_STREAM0_SRC_CRC0,
-		.flags = IORESOURCE_DMA,
-	},
-};
-
-static struct platform_device bfin_crypto_crc_device = {
-	.name = BFIN_CRYPTO_CRC_NAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
-	.resource = bfin_crypto_crc_resources,
-	.dev = {
-		.platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
-	.model			= 7877,
-	.vref_delay_usecs	= 50,	/* internal, no capacitor */
-	.x_plate_ohms		= 419,
-	.y_plate_ohms		= 486,
-	.pressure_max		= 1000,
-	.pressure_min		= 0,
-	.stopacq_polarity 	= 1,
-	.first_conversion_delay = 3,
-	.acquisition_time 	= 1,
-	.averaging 		= 1,
-	.pen_down_acc_interval 	= 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
-	.name = ADI_PINCTRL_DEVNAME,
-	.id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
-	{
-		.start = PINT0_MASK_SET,
-		.end = PINT0_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT0,
-		.end = IRQ_PINT0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint0_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_pint0_resources),
-	.resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
-	{
-		.start = PINT1_MASK_SET,
-		.end = PINT1_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT1,
-		.end = IRQ_PINT1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint1_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_pint1_resources),
-	.resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
-	{
-		.start = PINT2_MASK_SET,
-		.end = PINT2_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT2,
-		.end = IRQ_PINT2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint2_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 2,
-	.num_resources = ARRAY_SIZE(bfin_pint2_resources),
-	.resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
-	{
-		.start = PINT3_MASK_SET,
-		.end = PINT3_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT3,
-		.end = IRQ_PINT3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint3_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 3,
-	.num_resources = ARRAY_SIZE(bfin_pint3_resources),
-	.resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_pint4_resources[] = {
-	{
-		.start = PINT4_MASK_SET,
-		.end = PINT4_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT4,
-		.end = IRQ_PINT4,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint4_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 4,
-	.num_resources = ARRAY_SIZE(bfin_pint4_resources),
-	.resource = bfin_pint4_resources,
-};
-
-static struct resource bfin_pint5_resources[] = {
-	{
-		.start = PINT5_MASK_SET,
-		.end = PINT5_LATCH + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PINT5,
-		.end = IRQ_PINT5,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device bfin_pint5_device = {
-	.name = ADI_PINT_DEVNAME,
-	.id = 5,
-	.num_resources = ARRAY_SIZE(bfin_pint5_resources),
-	.resource = bfin_pint5_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
-	{
-		.start = PORTA_FER,
-		.end = PORTA_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{	/* optional */
-		.start = IRQ_PA0,
-		.end = IRQ_PA0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
-	.port_pin_base	= GPIO_PA0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 0,		/* PINT0 */
-	.pint_assign	= true,		/* PINT upper 16 bit */
-	.pint_map	= 0,		/* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_gpa_resources),
-	.resource = bfin_gpa_resources,
-	.dev = {
-		.platform_data = &bfin_gpa_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpb_resources[] = {
-	{
-		.start = PORTB_FER,
-		.end = PORTB_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PB0,
-		.end = IRQ_PB0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
-	.port_pin_base	= GPIO_PB0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 0,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpb_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_gpb_resources),
-	.resource = bfin_gpb_resources,
-	.dev = {
-		.platform_data = &bfin_gpb_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpc_resources[] = {
-	{
-		.start = PORTC_FER,
-		.end = PORTC_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PC0,
-		.end = IRQ_PC0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
-	.port_pin_base	= GPIO_PC0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 1,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpc_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 2,
-	.num_resources = ARRAY_SIZE(bfin_gpc_resources),
-	.resource = bfin_gpc_resources,
-	.dev = {
-		.platform_data = &bfin_gpc_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpd_resources[] = {
-	{
-		.start = PORTD_FER,
-		.end = PORTD_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PD0,
-		.end = IRQ_PD0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
-	.port_pin_base	= GPIO_PD0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 2,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpd_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 3,
-	.num_resources = ARRAY_SIZE(bfin_gpd_resources),
-	.resource = bfin_gpd_resources,
-	.dev = {
-		.platform_data = &bfin_gpd_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpe_resources[] = {
-	{
-		.start = PORTE_FER,
-		.end = PORTE_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PE0,
-		.end = IRQ_PE0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
-	.port_pin_base	= GPIO_PE0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 3,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpe_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 4,
-	.num_resources = ARRAY_SIZE(bfin_gpe_resources),
-	.resource = bfin_gpe_resources,
-	.dev = {
-		.platform_data = &bfin_gpe_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpf_resources[] = {
-	{
-		.start = PORTF_FER,
-		.end = PORTF_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PF0,
-		.end = IRQ_PF0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
-	.port_pin_base	= GPIO_PF0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 4,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpf_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 5,
-	.num_resources = ARRAY_SIZE(bfin_gpf_resources),
-	.resource = bfin_gpf_resources,
-	.dev = {
-		.platform_data = &bfin_gpf_pdata, /* Passed to driver */
-	},
-};
-
-static struct resource bfin_gpg_resources[] = {
-	{
-		.start = PORTG_FER,
-		.end = PORTG_MUX + 3,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = IRQ_PG0,
-		.end = IRQ_PG0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
-	.port_pin_base	= GPIO_PG0,
-	.port_width	= GPIO_BANKSIZE,
-	.pint_id	= 5,
-	.pint_assign	= false,
-	.pint_map	= 1,
-};
-
-static struct platform_device bfin_gpg_device = {
-	.name = ADI_GPIO_DEVNAME,
-	.id = 6,
-	.num_resources = ARRAY_SIZE(bfin_gpg_resources),
-	.resource = bfin_gpg_resources,
-	.dev = {
-		.platform_data = &bfin_gpg_pdata, /* Passed to driver */
-	},
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
-	{BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
-	{BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
-	.buttons        = bfin_gpio_keys_table,
-	.nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
-	.name      = "gpio-keys",
-	.dev = {
-		.platform_data = &bfin_gpio_keys_data,
-	},
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-	{
-		/* the modalias must be the same as spi device driver name */
-		.modalias = "m25p80", /* Name of spi_driver for this device */
-		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-		.bus_num = 0, /* Framework bus number */
-		.chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
-		.platform_data = &bfin_spi_flash_data,
-		.controller_data = &spi_flash_chip_info,
-		.mode = SPI_MODE_3,
-	},
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-	{
-		.modalias		= "ad7877",
-		.platform_data		= &bfin_ad7877_ts_info,
-		.irq			= IRQ_PD9,
-		.max_speed_hz		= 12500000,     /* max spi clock (SCK) speed in HZ */
-		.bus_num		= 0,
-		.chip_select		= MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
-	},
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-	{
-		.modalias = "spidev",
-		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-		.bus_num = 0,
-		.chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
-		.controller_data = &spidev_chip_info,
-	},
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
-	{
-		.modalias		= "adxl34x",
-		.platform_data		= &adxl34x_info,
-		.irq			= IRQ_PC5,
-		.max_speed_hz		= 5000000,     /* max spi clock (SCK) speed in HZ */
-		.bus_num		= 1,
-		.chip_select  		= 2,
-		.mode = SPI_MODE_3,
-	},
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
-	{
-		.start = SPI0_REGBASE,
-		.end   = SPI0_REGBASE + 0xFF,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = CH_SPI0_TX,
-		.end   = CH_SPI0_TX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_SPI0_RX,
-		.end   = CH_SPI0_RX,
-		.flags = IORESOURCE_DMA,
-	},
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
-	{
-		.start = SPI1_REGBASE,
-		.end   = SPI1_REGBASE + 0xFF,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = CH_SPI1_TX,
-		.end   = CH_SPI1_TX,
-		.flags = IORESOURCE_DMA,
-	},
-	{
-		.start = CH_SPI1_RX,
-		.end   = CH_SPI1_RX,
-		.flags = IORESOURCE_DMA,
-	},
-
-};
-
-/* SPI controller data */
-static struct adi_spi3_master bf60x_spi_master_info0 = {
-	.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
-	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master0 = {
-	.name = "adi-spi3",
-	.id = 0, /* Bus number */
-	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
-	.resource = bfin_spi0_resource,
-	.dev = {
-		.platform_data = &bf60x_spi_master_info0, /* Passed to driver */
-	},
-};
-
-static struct adi_spi3_master bf60x_spi_master_info1 = {
-	.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
-	.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master1 = {
-	.name = "adi-spi3",
-	.id = 1, /* Bus number */
-	.num_resources = ARRAY_SIZE(bfin_spi1_resource),
-	.resource = bfin_spi1_resource,
-	.dev = {
-		.platform_data = &bf60x_spi_master_info1, /* Passed to driver */
-	},
-};
-#endif  /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
-	[0] = {
-		.start = TWI0_CLKDIV,
-		.end   = TWI0_CLKDIV + 0xFF,
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = IRQ_TWI0,
-		.end   = IRQ_TWI0,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
-	.name = "i2c-bfin-twi",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
-	.resource = bfin_twi0_resource,
-	.dev = {
-		.platform_data = &bfin_twi0_pins,
-	},
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
-	[0] = {
-		.start = TWI1_CLKDIV,
-		.end   = TWI1_CLKDIV + 0xFF,
-		.flags = IORESOURCE_MEM,
-	},
-	[1] = {
-		.start = IRQ_TWI1,
-		.end   = IRQ_TWI1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
-	.name = "i2c-bfin-twi",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(bfin_twi1_resource),
-	.resource = bfin_twi1_resource,
-	.dev = {
-		.platform_data = &bfin_twi1_pins,
-	},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
-	.base = 120,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
-	.base = 130,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
-	.base = 140,
-};
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
-	.base = 150,
-};
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
-	.base = 160,
-};
-# endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
-	{
-		I2C_BOARD_INFO("adxl34x", 0x53),
-		.irq = IRQ_PC5,
-		.platform_data = (void *)&adxl34x_info,
-	},
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-	{
-		I2C_BOARD_INFO("adau1761", 0x38),
-		.platform_data = (void *)&adau1761_info
-	},
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
-	{
-		I2C_BOARD_INFO("ssm2602", 0x1b),
-	},
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-	{
-		I2C_BOARD_INFO("mcp23017", 0x21),
-		.platform_data = (void *)&bfin_mcp23s08_soft_switch0
-	},
-	{
-		I2C_BOARD_INFO("mcp23017", 0x22),
-		.platform_data = (void *)&bfin_mcp23s08_soft_switch1
-	},
-	{
-		I2C_BOARD_INFO("mcp23017", 0x23),
-		.platform_data = (void *)&bfin_mcp23s08_soft_switch2
-	},
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-	{
-		I2C_BOARD_INFO("mcp23017", 0x26),
-		.platform_data = (void *)&bfin_adv7842_soft_switch
-	},
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-	{
-		I2C_BOARD_INFO("mcp23017", 0x25),
-		.platform_data = (void *)&bfin_adv7511_soft_switch
-	},
-# endif
-#endif
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
-	VRPAIR(VLEV_085, 150000000),
-	VRPAIR(VLEV_090, 250000000),
-	VRPAIR(VLEV_110, 276000000),
-	VRPAIR(VLEV_115, 301000000),
-	VRPAIR(VLEV_120, 525000000),
-	VRPAIR(VLEV_125, 550000000),
-	VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
-	.tuple_tab = cclk_vlev_datasheet,
-	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
-	.vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
-	.name = "bfin dpmc",
-	.dev = {
-		.platform_data = &bfin_dmpc_vreg_data,
-	},
-};
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
-	&bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
-	&bfin_pinctrl_device,
-	&bfin_pint0_device,
-	&bfin_pint1_device,
-	&bfin_pint2_device,
-	&bfin_pint3_device,
-	&bfin_pint4_device,
-	&bfin_pint5_device,
-	&bfin_gpa_device,
-	&bfin_gpb_device,
-	&bfin_gpc_device,
-	&bfin_gpd_device,
-	&bfin_gpe_device,
-	&bfin_gpf_device,
-	&bfin_gpg_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-	&rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-	&bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-	&bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-	&bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
-	&bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-	&bfin_eth_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-	&musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-	&bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-	&bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-	&bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-	&bfin_sport2_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-	&bfin_can0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-	&bfin_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-	&bfin_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-	&bf60x_spi_master0,
-	&bf60x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-	&bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-	&i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
-	&i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-	&bfin_crc0_device,
-	&bfin_crc1_device,
-#endif
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-	&bfin_crypto_crc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-	&bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-	&ezkit_flash_device,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-	&bfin_pcm,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-	&bfin_i2s,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-	&bfin_ad1836_machine,
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-	&adau1761_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-	&bfin_capture_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-	&bfin_display_device,
-#endif
-
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
-	/* per-device maps */
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0",  "pinctrl-adi2.0", NULL, "uart0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1",  "pinctrl-adi2.0", NULL, "uart1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0",  "pinctrl-adi2.0", NULL, "uart0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1",  "pinctrl-adi2.0", NULL, "uart1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0",  "pinctrl-adi2.0", NULL, "rsi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0",  "pinctrl-adi2.0", NULL, "eth0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0",  "pinctrl-adi2.0", NULL, "spi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1",  "pinctrl-adi2.0", NULL, "spi1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0",  "pinctrl-adi2.0", NULL, "twi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1",  "pinctrl-adi2.0", NULL, "twi1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary",  "pinctrl-adi2.0", NULL, "rotary"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0",  "pinctrl-adi2.0", NULL, "can0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0",  "pinctrl-adi2.0", NULL, "smc0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
-	PIN_MAP_MUX_GROUP("bfin_display.0", "8bit",  "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
-	PIN_MAP_MUX_GROUP("bfin_display.0", "16bit",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
-	PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit",  "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
-	PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
-	PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit",  "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0",  "pinctrl-adi2.0", NULL, "sport0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0",  "pinctrl-adi2.0", NULL, "sport0"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1",  "pinctrl-adi2.0", NULL, "sport1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1",  "pinctrl-adi2.0", NULL, "sport1"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2",  "pinctrl-adi2.0", NULL, "sport2"),
-	PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2",  "pinctrl-adi2.0", NULL, "sport2"),
-};
-
-static int __init ezkit_init(void)
-{
-	printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-	/* Initialize pinmuxing */
-	pinctrl_register_mappings(bfin_pinmux_map,
-				ARRAY_SIZE(bfin_pinmux_map));
-
-	i2c_register_board_info(0, bfin_i2c_board_info0,
-				ARRAY_SIZE(bfin_i2c_board_info0));
-	i2c_register_board_info(1, bfin_i2c_board_info1,
-				ARRAY_SIZE(bfin_i2c_board_info1));
-
-	platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
-	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
-	return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-	&bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-	&bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
-	printk(KERN_INFO "register early platform devices\n");
-	early_platform_add_devices(ezkit_early_devices,
-		ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
deleted file mode 100644
index 16e0b09e2197..000000000000
--- a/arch/blackfin/mach-bf609/clock.c
+++ /dev/null
@@ -1,409 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <asm/clocks.h>
-
-#define CGU0_CTL_DF (1 << 0)
-
-#define CGU0_CTL_MSEL_SHIFT 8
-#define CGU0_CTL_MSEL_MASK (0x7f << 8)
-
-#define CGU0_STAT_PLLEN (1 << 0)
-#define CGU0_STAT_PLLBP (1 << 1)
-#define CGU0_STAT_PLLLK (1 << 2)
-#define CGU0_STAT_CLKSALGN (1 << 3)
-#define CGU0_STAT_CCBF0 (1 << 4)
-#define CGU0_STAT_CCBF1 (1 << 5)
-#define CGU0_STAT_SCBF0 (1 << 6)
-#define CGU0_STAT_SCBF1 (1 << 7)
-#define CGU0_STAT_DCBF (1 << 8)
-#define CGU0_STAT_OCBF (1 << 9)
-#define CGU0_STAT_ADDRERR (1 << 16)
-#define CGU0_STAT_LWERR (1 << 17)
-#define CGU0_STAT_DIVERR (1 << 18)
-#define CGU0_STAT_WDFMSERR (1 << 19)
-#define CGU0_STAT_WDIVERR (1 << 20)
-#define CGU0_STAT_PLOCKERR (1 << 21)
-
-#define CGU0_DIV_CSEL_SHIFT 0
-#define CGU0_DIV_CSEL_MASK 0x0000001F
-#define CGU0_DIV_S0SEL_SHIFT 5
-#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
-#define CGU0_DIV_SYSSEL_SHIFT 8
-#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
-#define CGU0_DIV_S1SEL_SHIFT 13
-#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
-#define CGU0_DIV_DSEL_SHIFT 16
-#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
-#define CGU0_DIV_OSEL_SHIFT 22
-#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
-
-#define CLK(_clk, _devname, _conname)                   \
-	{                                               \
-		.clk    = &_clk,                  \
-		.dev_id = _devname,                     \
-		.con_id = _conname,                     \
-	}
-
-#define NEEDS_INITIALIZATION 0x11
-
-static LIST_HEAD(clk_list);
-
-static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
-{
-	u32 val2;
-
-	val2 = bfin_read32(reg);
-	val2 &= ~mask;
-	val2 |= val;
-	bfin_write32(reg, val2);
-}
-
-int wait_for_pll_align(void)
-{
-	int i = 10000;
-	while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
-
-	if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
-		printk(KERN_CRIT "fail to align clk\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
-	int ret = -EIO;
-	if (clk->ops && clk->ops->enable)
-		ret = clk->ops->enable(clk);
-	return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	if (clk->ops && clk->ops->disable)
-		clk->ops->disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long ret = 0;
-	if (clk->ops && clk->ops->get_rate)
-		ret = clk->ops->get_rate(clk);
-	return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	long ret = 0;
-	if (clk->ops && clk->ops->round_rate)
-		ret = clk->ops->round_rate(clk, rate);
-	return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret = -EIO;
-	if (clk->ops && clk->ops->set_rate)
-		ret = clk->ops->set_rate(clk, rate);
-	return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long vco_get_rate(struct clk *clk)
-{
-	return clk->rate;
-}
-
-unsigned long pll_get_rate(struct clk *clk)
-{
-	u32 df;
-	u32 msel;
-	u32 ctl = bfin_read32(CGU0_CTL);
-	u32 stat = bfin_read32(CGU0_STAT);
-	if (stat & CGU0_STAT_PLLBP)
-		return 0;
-	msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
-	df = (ctl &  CGU0_CTL_DF);
-	clk->parent->rate = clk_get_rate(clk->parent);
-	return clk->parent->rate / (df + 1) * msel * 2;
-}
-
-unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
-{
-	u32 div;
-	div = rate / clk->parent->rate;
-	return clk->parent->rate * div;
-}
-
-int pll_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 msel;
-	u32 stat = bfin_read32(CGU0_STAT);
-	if (!(stat & CGU0_STAT_PLLEN))
-		return -EBUSY;
-	if (!(stat & CGU0_STAT_PLLLK))
-		return -EBUSY;
-	if (wait_for_pll_align())
-		return -EBUSY;
-	msel = rate / clk->parent->rate / 2;
-	clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
-		CGU0_CTL_MSEL_MASK);
-	clk->rate = rate;
-	return 0;
-}
-
-unsigned long cclk_get_rate(struct clk *clk)
-{
-	if (clk->parent)
-		return clk->parent->rate;
-	else
-		return 0;
-}
-
-unsigned long sys_clk_get_rate(struct clk *clk)
-{
-	unsigned long drate;
-	u32 msel;
-	u32 df;
-	u32 ctl = bfin_read32(CGU0_CTL);
-	u32 div = bfin_read32(CGU0_DIV);
-	div = (div & clk->mask) >> clk->shift;
-	msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
-	df = (ctl &  CGU0_CTL_DF);
-
-	if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
-		drate = clk->parent->rate / (df + 1);
-		drate *=  msel;
-		drate /= div;
-		return drate;
-	} else {
-		clk->parent->rate = clk_get_rate(clk->parent);
-		return clk->parent->rate / div;
-	}
-}
-
-unsigned long dummy_get_rate(struct clk *clk)
-{
-	clk->parent->rate = clk_get_rate(clk->parent);
-	return clk->parent->rate;
-}
-
-unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long max_rate;
-	unsigned long drate;
-	int i;
-	u32 msel;
-	u32 df;
-	u32 ctl = bfin_read32(CGU0_CTL);
-
-	msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
-	df = (ctl &  CGU0_CTL_DF);
-	max_rate = clk->parent->rate / (df + 1) * msel;
-
-	if (rate > max_rate)
-		return 0;
-
-	for (i = 1; i < clk->mask; i++) {
-		drate = max_rate / i;
-		if (rate >= drate)
-			return drate;
-	}
-	return 0;
-}
-
-int sys_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	u32 div = bfin_read32(CGU0_DIV);
-	div = (div & clk->mask) >> clk->shift;
-
-	rate = clk_round_rate(clk, rate);
-
-	if (!rate)
-		return -EINVAL;
-
-	div = (clk_get_rate(clk) * div) / rate;
-
-	if (wait_for_pll_align())
-		return -EBUSY;
-	clk_reg_write_mask(CGU0_DIV, div << clk->shift,
-			clk->mask);
-	clk->rate = rate;
-	return 0;
-}
-
-static struct clk_ops vco_ops = {
-	.get_rate = vco_get_rate,
-};
-
-static struct clk_ops pll_ops = {
-	.get_rate = pll_get_rate,
-	.set_rate = pll_set_rate,
-};
-
-static struct clk_ops cclk_ops = {
-	.get_rate = cclk_get_rate,
-};
-
-static struct clk_ops sys_clk_ops = {
-	.get_rate = sys_clk_get_rate,
-	.set_rate = sys_clk_set_rate,
-	.round_rate = sys_clk_round_rate,
-};
-
-static struct clk_ops dummy_clk_ops = {
-	.get_rate = dummy_get_rate,
-};
-
-static struct clk sys_clkin = {
-	.name       = "SYS_CLKIN",
-	.rate       = CONFIG_CLKIN_HZ,
-	.ops        = &vco_ops,
-};
-
-static struct clk pll_clk = {
-	.name       = "PLLCLK",
-	.rate       = 500000000,
-	.parent     = &sys_clkin,
-	.ops = &pll_ops,
-	.flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk = {
-	.name       = "CCLK",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_CSEL_MASK,
-	.shift      = CGU0_DIV_CSEL_SHIFT,
-	.parent     = &sys_clkin,
-	.ops	    = &sys_clk_ops,
-	.flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk0 = {
-	.name       = "CCLK0",
-	.parent     = &cclk,
-	.ops	    = &cclk_ops,
-};
-
-static struct clk cclk1 = {
-	.name       = "CCLK1",
-	.parent     = &cclk,
-	.ops	    = &cclk_ops,
-};
-
-static struct clk sysclk = {
-	.name       = "SYSCLK",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_SYSSEL_MASK,
-	.shift      = CGU0_DIV_SYSSEL_SHIFT,
-	.parent     = &sys_clkin,
-	.ops	    = &sys_clk_ops,
-	.flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk sclk0 = {
-	.name       = "SCLK0",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_S0SEL_MASK,
-	.shift      = CGU0_DIV_S0SEL_SHIFT,
-	.parent     = &sysclk,
-	.ops	    = &sys_clk_ops,
-};
-
-static struct clk sclk1 = {
-	.name       = "SCLK1",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_S1SEL_MASK,
-	.shift      = CGU0_DIV_S1SEL_SHIFT,
-	.parent     = &sysclk,
-	.ops	    = &sys_clk_ops,
-};
-
-static struct clk dclk = {
-	.name       = "DCLK",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_DSEL_MASK,
-	.shift       = CGU0_DIV_DSEL_SHIFT,
-	.parent     = &sys_clkin,
-	.ops	    = &sys_clk_ops,
-};
-
-static struct clk oclk = {
-	.name       = "OCLK",
-	.rate       = 500000000,
-	.mask       = CGU0_DIV_OSEL_MASK,
-	.shift      = CGU0_DIV_OSEL_SHIFT,
-	.parent     = &pll_clk,
-};
-
-static struct clk ethclk = {
-	.name       = "stmmaceth",
-	.parent     = &sclk0,
-	.ops	    = &dummy_clk_ops,
-};
-
-static struct clk ethpclk = {
-	.name       = "pclk",
-	.parent     = &sclk0,
-	.ops	    = &dummy_clk_ops,
-};
-
-static struct clk spiclk = {
-	.name       = "spi",
-	.parent     = &sclk1,
-	.ops        = &dummy_clk_ops,
-};
-
-static struct clk_lookup bf609_clks[] = {
-	CLK(sys_clkin, NULL, "SYS_CLKIN"),
-	CLK(pll_clk, NULL, "PLLCLK"),
-	CLK(cclk, NULL, "CCLK"),
-	CLK(cclk0, NULL, "CCLK0"),
-	CLK(cclk1, NULL, "CCLK1"),
-	CLK(sysclk, NULL, "SYSCLK"),
-	CLK(sclk0, NULL, "SCLK0"),
-	CLK(sclk1, NULL, "SCLK1"),
-	CLK(dclk, NULL, "DCLK"),
-	CLK(oclk, NULL, "OCLK"),
-	CLK(ethclk, NULL, "stmmaceth"),
-	CLK(ethpclk, NULL, "pclk"),
-	CLK(spiclk, NULL, "spi"),
-};
-
-int __init clk_init(void)
-{
-	int i;
-	struct clk *clkp;
-	for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
-		clkp = bf609_clks[i].clk;
-		if (clkp->flags & NEEDS_INITIALIZATION)
-			clk_get_rate(clkp);
-	}
-	clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
-	return 0;
-}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
deleted file mode 100644
index 1da4b38ac22c..000000000000
--- a/arch/blackfin/mach-bf609/dma.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
-	(struct dma_register *) DMA0_NEXT_DESC_PTR,
-	(struct dma_register *) DMA1_NEXT_DESC_PTR,
-	(struct dma_register *) DMA2_NEXT_DESC_PTR,
-	(struct dma_register *) DMA3_NEXT_DESC_PTR,
-	(struct dma_register *) DMA4_NEXT_DESC_PTR,
-	(struct dma_register *) DMA5_NEXT_DESC_PTR,
-	(struct dma_register *) DMA6_NEXT_DESC_PTR,
-	(struct dma_register *) DMA7_NEXT_DESC_PTR,
-	(struct dma_register *) DMA8_NEXT_DESC_PTR,
-	(struct dma_register *) DMA9_NEXT_DESC_PTR,
-	(struct dma_register *) DMA10_NEXT_DESC_PTR,
-	(struct dma_register *) DMA11_NEXT_DESC_PTR,
-	(struct dma_register *) DMA12_NEXT_DESC_PTR,
-	(struct dma_register *) DMA13_NEXT_DESC_PTR,
-	(struct dma_register *) DMA14_NEXT_DESC_PTR,
-	(struct dma_register *) DMA15_NEXT_DESC_PTR,
-	(struct dma_register *) DMA16_NEXT_DESC_PTR,
-	(struct dma_register *) DMA17_NEXT_DESC_PTR,
-	(struct dma_register *) DMA18_NEXT_DESC_PTR,
-	(struct dma_register *) DMA19_NEXT_DESC_PTR,
-	(struct dma_register *) DMA20_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
-	(struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
-	(struct dma_register *) DMA29_NEXT_DESC_PTR,
-	(struct dma_register *) DMA30_NEXT_DESC_PTR,
-	(struct dma_register *) DMA31_NEXT_DESC_PTR,
-	(struct dma_register *) DMA32_NEXT_DESC_PTR,
-	(struct dma_register *) DMA33_NEXT_DESC_PTR,
-	(struct dma_register *) DMA34_NEXT_DESC_PTR,
-	(struct dma_register *) DMA35_NEXT_DESC_PTR,
-	(struct dma_register *) DMA36_NEXT_DESC_PTR,
-	(struct dma_register *) DMA37_NEXT_DESC_PTR,
-	(struct dma_register *) DMA38_NEXT_DESC_PTR,
-	(struct dma_register *) DMA39_NEXT_DESC_PTR,
-	(struct dma_register *) DMA40_NEXT_DESC_PTR,
-	(struct dma_register *) DMA41_NEXT_DESC_PTR,
-	(struct dma_register *) DMA42_NEXT_DESC_PTR,
-	(struct dma_register *) DMA43_NEXT_DESC_PTR,
-	(struct dma_register *) DMA44_NEXT_DESC_PTR,
-	(struct dma_register *) DMA45_NEXT_DESC_PTR,
-	(struct dma_register *) DMA46_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
-	int ret_irq = -1;
-
-	switch (channel) {
-	case CH_SPORT0_RX:
-		ret_irq = IRQ_SPORT0_RX;
-		break;
-	case CH_SPORT0_TX:
-		ret_irq = IRQ_SPORT0_TX;
-		break;
-	case CH_SPORT1_RX:
-		ret_irq = IRQ_SPORT1_RX;
-		break;
-	case CH_SPORT1_TX:
-		ret_irq = IRQ_SPORT1_TX;
-		break;
-	case CH_SPORT2_RX:
-		ret_irq = IRQ_SPORT2_RX;
-		break;
-	case CH_SPORT2_TX:
-		ret_irq = IRQ_SPORT2_TX;
-		break;
-	case CH_SPI0_TX:
-		ret_irq = IRQ_SPI0_TX;
-		break;
-	case CH_SPI0_RX:
-		ret_irq = IRQ_SPI0_RX;
-		break;
-	case CH_SPI1_TX:
-		ret_irq = IRQ_SPI1_TX;
-		break;
-	case CH_SPI1_RX:
-		ret_irq = IRQ_SPI1_RX;
-		break;
-	case CH_RSI:
-		ret_irq = IRQ_RSI;
-		break;
-	case CH_SDU:
-		ret_irq = IRQ_SDU;
-		break;
-	case CH_LP0:
-		ret_irq = IRQ_LP0;
-		break;
-	case CH_LP1:
-		ret_irq = IRQ_LP1;
-		break;
-	case CH_LP2:
-		ret_irq = IRQ_LP2;
-		break;
-	case CH_LP3:
-		ret_irq = IRQ_LP3;
-		break;
-	case CH_UART0_RX:
-		ret_irq = IRQ_UART0_RX;
-		break;
-	case CH_UART0_TX:
-		ret_irq = IRQ_UART0_TX;
-		break;
-	case CH_UART1_RX:
-		ret_irq = IRQ_UART1_RX;
-		break;
-	case CH_UART1_TX:
-		ret_irq = IRQ_UART1_TX;
-		break;
-	case CH_EPPI0_CH0:
-		ret_irq = IRQ_EPPI0_CH0;
-		break;
-	case CH_EPPI0_CH1:
-		ret_irq = IRQ_EPPI0_CH1;
-		break;
-	case CH_EPPI1_CH0:
-		ret_irq = IRQ_EPPI1_CH0;
-		break;
-	case CH_EPPI1_CH1:
-		ret_irq = IRQ_EPPI1_CH1;
-		break;
-	case CH_EPPI2_CH0:
-		ret_irq = IRQ_EPPI2_CH0;
-		break;
-	case CH_EPPI2_CH1:
-		ret_irq = IRQ_EPPI2_CH1;
-		break;
-	case CH_PIXC_CH0:
-		ret_irq = IRQ_PIXC_CH0;
-		break;
-	case CH_PIXC_CH1:
-		ret_irq = IRQ_PIXC_CH1;
-		break;
-	case CH_PIXC_CH2:
-		ret_irq = IRQ_PIXC_CH2;
-		break;
-	case CH_PVP_CPDOB:
-		ret_irq = IRQ_PVP_CPDOB;
-		break;
-	case CH_PVP_CPDOC:
-		ret_irq = IRQ_PVP_CPDOC;
-		break;
-	case CH_PVP_CPSTAT:
-		ret_irq = IRQ_PVP_CPSTAT;
-		break;
-	case CH_PVP_CPCI:
-		ret_irq = IRQ_PVP_CPCI;
-		break;
-	case CH_PVP_MPDO:
-		ret_irq = IRQ_PVP_MPDO;
-		break;
-	case CH_PVP_MPDI:
-		ret_irq = IRQ_PVP_MPDI;
-		break;
-	case CH_PVP_MPSTAT:
-		ret_irq = IRQ_PVP_MPSTAT;
-		break;
-	case CH_PVP_MPCI:
-		ret_irq = IRQ_PVP_MPCI;
-		break;
-	case CH_PVP_CPDOA:
-		ret_irq = IRQ_PVP_CPDOA;
-		break;
-	case CH_MEM_STREAM0_SRC:
-	case CH_MEM_STREAM0_DEST:
-		ret_irq = IRQ_MDMAS0;
-		break;
-	case CH_MEM_STREAM1_SRC:
-	case CH_MEM_STREAM1_DEST:
-		ret_irq = IRQ_MDMAS1;
-		break;
-	case CH_MEM_STREAM2_SRC:
-	case CH_MEM_STREAM2_DEST:
-		ret_irq = IRQ_MDMAS2;
-		break;
-	case CH_MEM_STREAM3_SRC:
-	case CH_MEM_STREAM3_DEST:
-		ret_irq = IRQ_MDMAS3;
-		break;
-	}
-	return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
deleted file mode 100644
index fcb8f688a8b2..000000000000
--- a/arch/blackfin/mach-bf609/dpm.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#include <asm/context.S>
-
-#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
-	/* switch stack to L1 scratch, prepare for ddr srfr */
-	P0.H = HI(PM_STACK);
-	P0.L = LO(PM_STACK);
-	SP = P0;
-
-	call _bf609_ddr_sr;
-	call _bfin_hibernate_syscontrol;
-
-	P0.H = HI(DPM0_RESTORE4);
-	P0.L = LO(DPM0_RESTORE4);
-	P1.H = _bf609_pm_data;
-	P1.L = _bf609_pm_data;
-	[P0] = P1;
-
-	P0.H = HI(DPM0_CTL);
-	P0.L = LO(DPM0_CTL);
-	R3.H = HI(0x00000010);
-	R3.L = LO(0x00000010);
-
-	bfin_init_pm_bench_cycles;
-
-	[P0] = R3;
-
-	SSYNC;
-ENDPROC(_enter_hibernate)
-
-/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
- * is disabled. This behavior differ from bf5xx serial processor.
- */
-ENTRY(_dummy_deepsleep)
-	[--sp] = SYSCFG;
-	[--sp] = (R7:0,P5:0);
-	cli r0;
-
-	/* get wake up interrupt ID */
-	P0.l = LO(SEC_SCI_BASE + SEC_CSID);
-	P0.h = HI(SEC_SCI_BASE + SEC_CSID);
-	R0 = [P0];
-
-	/* ACK wake up interrupt in SEC */
-	P1.l = LO(SEC_END);
-	P1.h = HI(SEC_END);
-
-	[P1] = R0;
-	SSYNC;
-
-	/* restore EVT 11 entry */
-	p0.h = hi(EVT11);
-	p0.l = lo(EVT11);
-	p1.h = _evt_evt11;
-	p1.l = _evt_evt11;
-
-	[p0] = p1;
-	SSYNC;
-
-	(R7:0,P5:0) = [sp++];
-	SYSCFG = [sp++];
-	RTI;
-ENDPROC(_dummy_deepsleep)
-
-ENTRY(_enter_deepsleep)
-	LINK 0xC;
-	[--sp] = (R7:0,P5:0);
-
-	/* Change EVT 11 entry to dummy handler for wake up event */
-	p0.h = hi(EVT11);
-	p0.l = lo(EVT11);
-	p1.h = _dummy_deepsleep;
-	p1.l = _dummy_deepsleep;
-
-	[p0] = p1;
-
-	P0.H = HI(PM_STACK);
-	P0.L = LO(PM_STACK);
-
-	EX_SCRATCH_REG = SP;
-	SP = P0;
-
-	SSYNC;
-
-	/* should put ddr to self refresh mode before sleep */
-	call _bf609_ddr_sr;
-
-	/* Set DPM controller to deep sleep mode */
-	P0.H = HI(DPM0_CTL);
-	P0.L = LO(DPM0_CTL);
-	R3.H = HI(0x00000008);
-	R3.L = LO(0x00000008);
-	[P0] = R3;
-	CSYNC;
-
-	/* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
-	r0.l = 0x800;
-	r0.h = 0;
-	sti r0;
-	SSYNC;
-
-	bfin_init_pm_bench_cycles;
-
-	/* Fall into deep sleep in idle*/
-	idle;
-	SSYNC;
-
-	/* Restore PLL after wake up from deep sleep */
-	call _bf609_resume_ccbuf;
-
-	/* turn ddr out of self refresh mode */
-	call _bf609_ddr_sr_exit;
-
-	SP = EX_SCRATCH_REG;
-
-	(R7:0,P5:0) = [SP++];
-	UNLINK;
-	RTS;
-ENDPROC(_enter_deepsleep)
-
-.section .text
-ENTRY(_bf609_hibernate)
-	bfin_cpu_reg_save;
-	bfin_core_mmr_save;
-
-	P0.H = _bf609_pm_data;
-	P0.L = _bf609_pm_data;
-	R1.H = 0xDEAD;
-	R1.L = 0xBEEF;
-	R2.H = .Lpm_resume_here;
-	R2.L = .Lpm_resume_here;
-	[P0++] = R1;
-	[P0++] = R2;
-	[P0++] = SP;
-
-	P1.H = _enter_hibernate;
-	P1.L = _enter_hibernate;
-
-	call (P1);
-.Lpm_resume_here:
-
-	bfin_core_mmr_restore;
-	bfin_cpu_reg_restore;
-
-	[--sp] = RETI;  /* Clear Global Interrupt Disable */
-	SP += 4;
-
-	RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
deleted file mode 100644
index 696786e9a531..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
-/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
-#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
-/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
-#define ANOMALY_16000024 (1)
-/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
-#define ANOMALY_16000025 (1)
-/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Default SPI Master Boot Mode Setting is Incorrect */
-#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
-/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
-/* Incorrect Default USB_PLL_OSC.PLLM Value */
-#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
-/* Core Reads of System MMRs May Cause the Core to Hang */
-#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
-/* PPI Data Underflow on First Word Not Reported in Certain Modes */
-#define ANOMALY_16000033 (1)
-/* CNV1 Red Pixel Substitution feature not functional in the PVP */
-#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
-/* IPF0 Output Port Color Separation feature not functional */
-#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
-/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
-#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
-/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
-#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
-/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
-#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
-/* CGU_STAT.PLOCKERR Bit May be Unreliable */
-#define ANOMALY_16000039 (1)
-/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
-#define ANOMALY_16000040 (1)
-/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
-#define ANOMALY_16000041 (1)
-/* Instruction Cache Failure When Parity Is Enabled */
-#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
deleted file mode 100644
index c897c2a2fbfa..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bf609.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF609_H__
-#define __MACH_BF609_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15		0x8000
-#define IMASK_IVG14		0x4000
-#define IMASK_IVG13		0x2000
-#define IMASK_IVG12		0x1000
-
-#define IMASK_IVG11		0x0800
-#define IMASK_IVG10		0x0400
-#define IMASK_IVG9		0x0200
-#define IMASK_IVG8		0x0100
-
-#define IMASK_IVG7		0x0080
-#define IMASK_IVGTMR		0x0040
-#define IMASK_IVGHW		0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS		4
-#define BFIN_DWAYS		2
-#define BFIN_DLINES		64
-#define BFIN_ISUBBANKS		4
-#define BFIN_IWAYS		4
-#define BFIN_ILINES		32
-
-#define WAY0_L			0x1
-#define WAY1_L			0x2
-#define WAY01_L			0x3
-#define WAY2_L			0x4
-#define WAY02_L			0x5
-#define	WAY12_L			0x6
-#define	WAY012_L		0x7
-
-#define	WAY3_L			0x8
-#define	WAY03_L			0x9
-#define	WAY13_L			0xA
-#define	WAY013_L		0xB
-
-#define	WAY32_L			0xC
-#define	WAY320_L		0xD
-#define	WAY321_L		0xE
-#define	WAYALL_L		0xF
-
-#define DMC_ENABLE (2<<2)	/*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL	((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL	((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL	(V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF609)
-# define CPU   "BF609"
-# define CPUID 0x27fe	/* temperary fake value */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif	/* __MACH_BF609_H__  */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
deleted file mode 100644
index 1fd398147fd9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS	2
-#define BFIN_UART_TX_FIFO_SIZE	8
-
-#define BFIN_UART_BF60X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
deleted file mode 100644
index b1a48c410711..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/blackfin.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf609.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF609
-# include "defBF609.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF609
-#  include "cdefBF609.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
deleted file mode 100644
index c4f3fe19acda..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
-#include "cdefBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-
-#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
deleted file mode 100644
index 102ee4025ac9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ /dev/null
@@ -1,3254 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF60X_H
-#define _CDEF_BF60X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
-/* ************************************************************** */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID()		bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-/* SEC0 Registers */
-#define bfin_read_SEC0_CCTL()		bfin_read32(SEC0_CCTL)
-#define bfin_write_SEC0_CCTL(val)	bfin_write32(SEC0_CCTL, val)
-#define bfin_read_SEC0_CSID()		bfin_read32(SEC0_CSID)
-#define bfin_write_SEC0_CSID(val)	bfin_write32(SEC0_CSID, val)
-#define bfin_read_SEC_GCTL()		bfin_read32(SEC_GCTL)
-#define bfin_write_SEC_GCTL(val)	bfin_write32(SEC_GCTL, val)
-
-#define bfin_read_SEC_FCTL()		bfin_read32(SEC_FCTL)
-#define bfin_write_SEC_FCTL(val)	bfin_write32(SEC_FCTL, val)
-
-#define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC_SCTL0 + (sid) * 8), val)
-
-#define bfin_read_SEC_SSTAT(sid)	bfin_read32((SEC_SSTAT0 + (sid) * 8))
-#define bfin_write_SEC_SSTAT(sid, val)	bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
-
-/* RCU0 Registers */
-#define bfin_read_RCU0_CTL()		bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val)	bfin_write32(RCU0_CTL, val)
-
-/* Watchdog Timer Registers */
-#define bfin_read_WDOG_CTL()		bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)	bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()		bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)	bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()		bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)	bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_REVID()		bfin_read32(UART0_REVID)
-#define bfin_write_UART0_REVID(val)	bfin_write32(UART0_REVID, val)
-#define bfin_read_UART0_GCTL()		bfin_read32(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)	bfin_write32(UART0_GCTL, val)
-#define bfin_read_UART0_STAT()		bfin_read32(UART0_STAT)
-#define bfin_write_UART0_STAT(val)	bfin_write32(UART0_STAT, val)
-#define bfin_read_UART0_SCR()		bfin_read32(UART0_SCR)
-#define bfin_write_UART0_SCR(val)	bfin_write32(UART0_SCR, val)
-#define bfin_read_UART0_CLK()		bfin_read32(UART0_CLK)
-#define bfin_write_UART0_CLK(val)	bfin_write32(UART0_CLK, val)
-#define bfin_read_UART0_IER()		bfin_read32(UART0_IER)
-#define bfin_write_UART0_IER(val)	bfin_write32(UART0_IER, val)
-#define bfin_read_UART0_IER_SET()	bfin_read32(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)	bfin_write32(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()	bfin_read32(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val)	bfin_write32(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_RBR()		bfin_read32(UART0_RBR)
-#define bfin_write_UART0_RBR(val)	bfin_write32(UART0_RBR, val)
-#define bfin_read_UART0_THR()		bfin_read32(UART0_THR)
-#define bfin_write_UART0_THR(val)	bfin_write32(UART0_THR, val)
-#define bfin_read_UART0_TAIP()		bfin_read32(UART0_TAIP)
-#define bfin_write_UART0_TAIP(val)	bfin_write32(UART0_TAIP, val)
-#define bfin_read_UART0_TSR()		bfin_read32(UART0_TSR)
-#define bfin_write_UART0_TSR(val)	bfin_write32(UART0_TSR, val)
-#define bfin_read_UART0_RSR()		bfin_read32(UART0_RSR)
-#define bfin_write_UART0_RSR(val)	bfin_write32(UART0_RSR, val)
-#define bfin_read_UART0_TXCNT()		bfin_read32(UART0_TXCNT)
-#define bfin_write_UART0_TXCNT(val)	bfin_write32(UART0_TXCNT, val)
-#define bfin_read_UART0_RXCNT()		bfin_read32(UART0_RXCNT)
-#define bfin_write_UART0_RXCNT(val)	bfin_write32(UART0_RXCNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_REVID()		bfin_read32(UART1_REVID)
-#define bfin_write_UART1_REVID(val)	bfin_write32(UART1_REVID, val)
-#define bfin_read_UART1_GCTL()		bfin_read32(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)	bfin_write32(UART1_GCTL, val)
-#define bfin_read_UART1_STAT()		bfin_read32(UART1_STAT)
-#define bfin_write_UART1_STAT(val)	bfin_write32(UART1_STAT, val)
-#define bfin_read_UART1_SCR()		bfin_read32(UART1_SCR)
-#define bfin_write_UART1_SCR(val)	bfin_write32(UART1_SCR, val)
-#define bfin_read_UART1_CLK()		bfin_read32(UART1_CLK)
-#define bfin_write_UART1_CLK(val)	bfin_write32(UART1_CLK, val)
-#define bfin_read_UART1_IER()		bfin_read32(UART1_IER)
-#define bfin_write_UART1_IER(val)	bfin_write32(UART1_IER, val)
-#define bfin_read_UART1_IER_SET()	bfin_read32(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)	bfin_write32(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()	bfin_read32(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val)	bfin_write32(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_RBR()		bfin_read32(UART1_RBR)
-#define bfin_write_UART1_RBR(val)	bfin_write32(UART1_RBR, val)
-#define bfin_read_UART1_THR()		bfin_read32(UART1_THR)
-#define bfin_write_UART1_THR(val)	bfin_write32(UART1_THR, val)
-#define bfin_read_UART1_TAIP()		bfin_read32(UART1_TAIP)
-#define bfin_write_UART1_TAIP(val)	bfin_write32(UART1_TAIP, val)
-#define bfin_read_UART1_TSR()		bfin_read32(UART1_TSR)
-#define bfin_write_UART1_TSR(val)	bfin_write32(UART1_TSR, val)
-#define bfin_read_UART1_RSR()		bfin_read32(UART1_RSR)
-#define bfin_write_UART1_RSR(val)	bfin_write32(UART1_RSR, val)
-#define bfin_read_UART1_TXCNT()		bfin_read32(UART1_TXCNT)
-#define bfin_write_UART1_TXCNT(val)	bfin_write32(UART1_TXCNT, val)
-#define bfin_read_UART1_RXCNT()		bfin_read32(UART1_RXCNT)
-#define bfin_write_UART1_RXCNT(val)	bfin_write32(UART1_RXCNT, val)
-
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL()		bfin_read32(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)	bfin_write32(SPI0_CTL, val)
-#define bfin_read_SPI0_RXCTL()		bfin_read32(SPI0_RXCTL)
-#define bfin_write_SPI0_RXCTL(val)	bfin_write32(SPI0_RXCTL, val)
-#define bfin_read_SPI0_TXCTL()		bfin_read32(SPI0_TXCTL)
-#define bfin_write_SPI0_TXCTL(val)	bfin_write32(SPI0_TXCTL, val)
-#define bfin_read_SPI0_CLK()		bfin_read32(SPI0_CLK)
-#define bfin_write_SPI0_CLK(val)	bfin_write32(SPI0_CLK, val)
-#define bfin_read_SPI0_DLY()		bfin_read32(SPI0_DLY)
-#define bfin_write_SPI0_DLY(val)	bfin_write32(SPI0_DLY, val)
-#define bfin_read_SPI0_SLVSEL()		bfin_read32(SPI0_SLVSEL)
-#define bfin_write_SPI0_SLVSEL(val)	bfin_write32(SPI0_SLVSEL, val)
-#define bfin_read_SPI0_RWC()		bfin_read32(SPI0_RWC)
-#define bfin_write_SPI0_RWC(val)	bfin_write32(SPI0_RWC, val)
-#define bfin_read_SPI0_RWCR()		bfin_read32(SPI0_RWCR)
-#define bfin_write_SPI0_RWCR(val)	bfin_write32(SPI0_RWCR, val)
-#define bfin_read_SPI0_TWC()		bfin_read32(SPI0_TWC)
-#define bfin_write_SPI0_TWC(val)	bfin_write32(SPI0_TWC, val)
-#define bfin_read_SPI0_TWCR()		bfin_read32(SPI0_TWCR)
-#define bfin_write_SPI0_TWCR(val)	bfin_write32(SPI0_TWCR, val)
-#define bfin_read_SPI0_IMSK()		bfin_read32(SPI0_IMSK)
-#define bfin_write_SPI0_IMSK(val)	bfin_write32(SPI0_IMSK, val)
-#define bfin_read_SPI0_IMSK_CLR()	bfin_read32(SPI0_IMSK_CLR)
-#define bfin_write_SPI0_IMSK_CLR(val)	bfin_write32(SPI0_IMSK_CLR, val)
-#define bfin_read_SPI0_IMSK_SET()	bfin_read32(SPI0_IMSK_SET)
-#define bfin_write_SPI0_IMSK_SET(val)	bfin_write32(SPI0_IMSK_SET, val)
-#define bfin_read_SPI0_STAT()		bfin_read32(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)	bfin_write32(SPI0_STAT, val)
-#define bfin_read_SPI0_ILAT()		bfin_read32(SPI0_ILAT)
-#define bfin_write_SPI0_ILAT(val)	bfin_write32(SPI0_ILAT, val)
-#define bfin_read_SPI0_ILAT_CLR()	bfin_read32(SPI0_ILAT_CLR)
-#define bfin_write_SPI0_ILAT_CLR(val)	bfin_write32(SPI0_ILAT_CLR, val)
-#define bfin_read_SPI0_RFIFO()		bfin_read32(SPI0_RFIFO)
-#define bfin_write_SPI0_RFIFO(val)	bfin_write32(SPI0_RFIFO, val)
-#define bfin_read_SPI0_TFIFO()		bfin_read32(SPI0_TFIFO)
-#define bfin_write_SPI0_TFIFO(val)	bfin_write32(SPI0_TFIFO, val)
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL()		bfin_read32(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)	bfin_write32(SPI1_CTL, val)
-#define bfin_read_SPI1_RXCTL()		bfin_read32(SPI1_RXCTL)
-#define bfin_write_SPI1_RXCTL(val)	bfin_write32(SPI1_RXCTL, val)
-#define bfin_read_SPI1_TXCTL()		bfin_read32(SPI1_TXCTL)
-#define bfin_write_SPI1_TXCTL(val)	bfin_write32(SPI1_TXCTL, val)
-#define bfin_read_SPI1_CLK()		bfin_read32(SPI1_CLK)
-#define bfin_write_SPI1_CLK(val)	bfin_write32(SPI1_CLK, val)
-#define bfin_read_SPI1_DLY()		bfin_read32(SPI1_DLY)
-#define bfin_write_SPI1_DLY(val)	bfin_write32(SPI1_DLY, val)
-#define bfin_read_SPI1_SLVSEL()		bfin_read32(SPI1_SLVSEL)
-#define bfin_write_SPI1_SLVSEL(val)	bfin_write32(SPI1_SLVSEL, val)
-#define bfin_read_SPI1_RWC()		bfin_read32(SPI1_RWC)
-#define bfin_write_SPI1_RWC(val)	bfin_write32(SPI1_RWC, val)
-#define bfin_read_SPI1_RWCR()		bfin_read32(SPI1_RWCR)
-#define bfin_write_SPI1_RWCR(val)	bfin_write32(SPI1_RWCR, val)
-#define bfin_read_SPI1_TWC()		bfin_read32(SPI1_TWC)
-#define bfin_write_SPI1_TWC(val)	bfin_write32(SPI1_TWC, val)
-#define bfin_read_SPI1_TWCR()		bfin_read32(SPI1_TWCR)
-#define bfin_write_SPI1_TWCR(val)	bfin_write32(SPI1_TWCR, val)
-#define bfin_read_SPI1_IMSK()		bfin_read32(SPI1_IMSK)
-#define bfin_write_SPI1_IMSK(val)	bfin_write32(SPI1_IMSK, val)
-#define bfin_read_SPI1_IMSK_CLR()	bfin_read32(SPI1_IMSK_CLR)
-#define bfin_write_SPI1_IMSK_CLR(val)	bfin_write32(SPI1_IMSK_CLR, val)
-#define bfin_read_SPI1_IMSK_SET()	bfin_read32(SPI1_IMSK_SET)
-#define bfin_write_SPI1_IMSK_SET(val)	bfin_write32(SPI1_IMSK_SET, val)
-#define bfin_read_SPI1_STAT()		bfin_read32(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)	bfin_write32(SPI1_STAT, val)
-#define bfin_read_SPI1_ILAT()		bfin_read32(SPI1_ILAT)
-#define bfin_write_SPI1_ILAT(val)	bfin_write32(SPI1_ILAT, val)
-#define bfin_read_SPI1_ILAT_CLR()	bfin_read32(SPI1_ILAT_CLR)
-#define bfin_write_SPI1_ILAT_CLR(val)	bfin_write32(SPI1_ILAT_CLR, val)
-#define bfin_read_SPI1_RFIFO()		bfin_read32(SPI1_RFIFO)
-#define bfin_write_SPI1_RFIFO(val)	bfin_write32(SPI1_RFIFO, val)
-#define bfin_read_SPI1_TFIFO()		bfin_read32(SPI1_TFIFO)
-#define bfin_write_SPI1_TFIFO(val)	bfin_write32(SPI1_TFIFO, val)
-
-/* Timer 0-7 registers */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH, val)
-
-
-
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT1 Registers */
-
-
-/* SMC Registers */
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-/* DDR2 Memory Control Registers */
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
-#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() 		bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) 	bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() 		bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) 	bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()			bfin_read32(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)		bfin_write32(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()		bfin_read32(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)		bfin_write32(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()		bfin_read32(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) 		bfin_write32(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()		bfin_read32(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)		bfin_write32(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()		bfin_read32(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) 		bfin_write32(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() 		bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) 	bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_PREV_DESC_PTR() 		bfin_read32(DMA0_PREV_DESC_PTR)
-#define bfin_write_DMA0_PREV_DESC_PTR(val) 	bfin_write32(DMA0_PREV_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() 		bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) 		bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()		bfin_read32(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)		bfin_write32(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_CURR_X_COUNT()		bfin_read32(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)	bfin_write32(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()		bfin_read32(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)	bfin_write32(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_BWL_COUNT()		bfin_read32(DMA0_BWL_COUNT)
-#define bfin_write_DMA0_BWL_COUNT(val)		bfin_write32(DMA0_BWL_COUNT, val)
-#define bfin_read_DMA0_CURR_BWL_COUNT()		bfin_read32(DMA0_CURR_BWL_COUNT)
-#define bfin_write_DMA0_CURR_BWL_COUNT(val)	bfin_write32(DMA0_CURR_BWL_COUNT, val)
-#define bfin_read_DMA0_BWM_COUNT()		bfin_read32(DMA0_BWM_COUNT)
-#define bfin_write_DMA0_BWM_COUNT(val)		bfin_write32(DMA0_BWM_COUNT, val)
-#define bfin_read_DMA0_CURR_BWM_COUNT()		bfin_read32(DMA0_CURR_BWM_COUNT)
-#define bfin_write_DMA0_CURR_BWM_COUNT(val)	bfin_write32(DMA0_CURR_BWM_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() 		bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) 	bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() 		bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) 	bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()			bfin_read32(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)		bfin_write32(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()		bfin_read32(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)		bfin_write32(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()		bfin_read32(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) 		bfin_write32(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()		bfin_read32(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)		bfin_write32(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()		bfin_read32(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) 		bfin_write32(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() 		bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) 	bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_PREV_DESC_PTR() 		bfin_read32(DMA1_PREV_DESC_PTR)
-#define bfin_write_DMA1_PREV_DESC_PTR(val) 	bfin_write32(DMA1_PREV_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() 		bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) 		bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()		bfin_read32(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)		bfin_write32(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_CURR_X_COUNT()		bfin_read32(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)	bfin_write32(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()		bfin_read32(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)	bfin_write32(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_BWL_COUNT()		bfin_read32(DMA1_BWL_COUNT)
-#define bfin_write_DMA1_BWL_COUNT(val)		bfin_write32(DMA1_BWL_COUNT, val)
-#define bfin_read_DMA1_CURR_BWL_COUNT()		bfin_read32(DMA1_CURR_BWL_COUNT)
-#define bfin_write_DMA1_CURR_BWL_COUNT(val)	bfin_write32(DMA1_CURR_BWL_COUNT, val)
-#define bfin_read_DMA1_BWM_COUNT()		bfin_read32(DMA1_BWM_COUNT)
-#define bfin_write_DMA1_BWM_COUNT(val)		bfin_write32(DMA1_BWM_COUNT, val)
-#define bfin_read_DMA1_CURR_BWM_COUNT()		bfin_read32(DMA1_CURR_BWM_COUNT)
-#define bfin_write_DMA1_CURR_BWM_COUNT(val)	bfin_write32(DMA1_CURR_BWM_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() 		bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) 	bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() 		bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) 	bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()			bfin_read32(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)		bfin_write32(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()		bfin_read32(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)		bfin_write32(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()		bfin_read32(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) 		bfin_write32(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()		bfin_read32(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)		bfin_write32(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()		bfin_read32(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) 		bfin_write32(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() 		bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) 	bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_PREV_DESC_PTR() 		bfin_read32(DMA2_PREV_DESC_PTR)
-#define bfin_write_DMA2_PREV_DESC_PTR(val) 	bfin_write32(DMA2_PREV_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() 		bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) 		bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()		bfin_read32(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)		bfin_write32(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_CURR_X_COUNT()		bfin_read32(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)	bfin_write32(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()		bfin_read32(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)	bfin_write32(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_BWL_COUNT()		bfin_read32(DMA2_BWL_COUNT)
-#define bfin_write_DMA2_BWL_COUNT(val)		bfin_write32(DMA2_BWL_COUNT, val)
-#define bfin_read_DMA2_CURR_BWL_COUNT()		bfin_read32(DMA2_CURR_BWL_COUNT)
-#define bfin_write_DMA2_CURR_BWL_COUNT(val)	bfin_write32(DMA2_CURR_BWL_COUNT, val)
-#define bfin_read_DMA2_BWM_COUNT()		bfin_read32(DMA2_BWM_COUNT)
-#define bfin_write_DMA2_BWM_COUNT(val)		bfin_write32(DMA2_BWM_COUNT, val)
-#define bfin_read_DMA2_CURR_BWM_COUNT()		bfin_read32(DMA2_CURR_BWM_COUNT)
-#define bfin_write_DMA2_CURR_BWM_COUNT(val)	bfin_write32(DMA2_CURR_BWM_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() 		bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) 	bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() 		bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) 	bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()			bfin_read32(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)		bfin_write32(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()		bfin_read32(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)		bfin_write32(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()		bfin_read32(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) 		bfin_write32(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()		bfin_read32(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)		bfin_write32(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()		bfin_read32(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) 		bfin_write32(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() 		bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) 	bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_PREV_DESC_PTR() 		bfin_read32(DMA3_PREV_DESC_PTR)
-#define bfin_write_DMA3_PREV_DESC_PTR(val) 	bfin_write32(DMA3_PREV_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() 		bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) 		bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()		bfin_read32(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)		bfin_write32(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_CURR_X_COUNT()		bfin_read32(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)	bfin_write32(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()		bfin_read32(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)	bfin_write32(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_BWL_COUNT()		bfin_read32(DMA3_BWL_COUNT)
-#define bfin_write_DMA3_BWL_COUNT(val)		bfin_write32(DMA3_BWL_COUNT, val)
-#define bfin_read_DMA3_CURR_BWL_COUNT()		bfin_read32(DMA3_CURR_BWL_COUNT)
-#define bfin_write_DMA3_CURR_BWL_COUNT(val)	bfin_write32(DMA3_CURR_BWL_COUNT, val)
-#define bfin_read_DMA3_BWM_COUNT()		bfin_read32(DMA3_BWM_COUNT)
-#define bfin_write_DMA3_BWM_COUNT(val)		bfin_write32(DMA3_BWM_COUNT, val)
-#define bfin_read_DMA3_CURR_BWM_COUNT()		bfin_read32(DMA3_CURR_BWM_COUNT)
-#define bfin_write_DMA3_CURR_BWM_COUNT(val)	bfin_write32(DMA3_CURR_BWM_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() 		bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) 	bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() 		bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) 	bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()			bfin_read32(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)		bfin_write32(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()		bfin_read32(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)		bfin_write32(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()		bfin_read32(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) 		bfin_write32(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()		bfin_read32(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)		bfin_write32(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()		bfin_read32(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) 		bfin_write32(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() 		bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) 	bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_PREV_DESC_PTR() 		bfin_read32(DMA4_PREV_DESC_PTR)
-#define bfin_write_DMA4_PREV_DESC_PTR(val) 	bfin_write32(DMA4_PREV_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() 		bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) 		bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()		bfin_read32(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)		bfin_write32(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_CURR_X_COUNT()		bfin_read32(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)	bfin_write32(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()		bfin_read32(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)	bfin_write32(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_BWL_COUNT()		bfin_read32(DMA4_BWL_COUNT)
-#define bfin_write_DMA4_BWL_COUNT(val)		bfin_write32(DMA4_BWL_COUNT, val)
-#define bfin_read_DMA4_CURR_BWL_COUNT()		bfin_read32(DMA4_CURR_BWL_COUNT)
-#define bfin_write_DMA4_CURR_BWL_COUNT(val)	bfin_write32(DMA4_CURR_BWL_COUNT, val)
-#define bfin_read_DMA4_BWM_COUNT()		bfin_read32(DMA4_BWM_COUNT)
-#define bfin_write_DMA4_BWM_COUNT(val)		bfin_write32(DMA4_BWM_COUNT, val)
-#define bfin_read_DMA4_CURR_BWM_COUNT()		bfin_read32(DMA4_CURR_BWM_COUNT)
-#define bfin_write_DMA4_CURR_BWM_COUNT(val)	bfin_write32(DMA4_CURR_BWM_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() 		bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) 	bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() 		bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) 	bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()			bfin_read32(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)		bfin_write32(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()		bfin_read32(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)		bfin_write32(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()		bfin_read32(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) 		bfin_write32(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()		bfin_read32(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)		bfin_write32(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()		bfin_read32(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) 		bfin_write32(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() 		bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) 	bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_PREV_DESC_PTR() 		bfin_read32(DMA5_PREV_DESC_PTR)
-#define bfin_write_DMA5_PREV_DESC_PTR(val) 	bfin_write32(DMA5_PREV_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() 		bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) 		bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()		bfin_read32(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)		bfin_write32(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_CURR_X_COUNT()		bfin_read32(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)	bfin_write32(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()		bfin_read32(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)	bfin_write32(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_BWL_COUNT()		bfin_read32(DMA5_BWL_COUNT)
-#define bfin_write_DMA5_BWL_COUNT(val)		bfin_write32(DMA5_BWL_COUNT, val)
-#define bfin_read_DMA5_CURR_BWL_COUNT()		bfin_read32(DMA5_CURR_BWL_COUNT)
-#define bfin_write_DMA5_CURR_BWL_COUNT(val)	bfin_write32(DMA5_CURR_BWL_COUNT, val)
-#define bfin_read_DMA5_BWM_COUNT()		bfin_read32(DMA5_BWM_COUNT)
-#define bfin_write_DMA5_BWM_COUNT(val)		bfin_write32(DMA5_BWM_COUNT, val)
-#define bfin_read_DMA5_CURR_BWM_COUNT()		bfin_read32(DMA5_CURR_BWM_COUNT)
-#define bfin_write_DMA5_CURR_BWM_COUNT(val)	bfin_write32(DMA5_CURR_BWM_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() 		bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) 	bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() 		bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) 	bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()			bfin_read32(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)		bfin_write32(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()		bfin_read32(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)		bfin_write32(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()		bfin_read32(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) 		bfin_write32(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()		bfin_read32(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)		bfin_write32(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()		bfin_read32(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) 		bfin_write32(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() 		bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) 	bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_PREV_DESC_PTR() 		bfin_read32(DMA6_PREV_DESC_PTR)
-#define bfin_write_DMA6_PREV_DESC_PTR(val) 	bfin_write32(DMA6_PREV_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() 		bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) 		bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()		bfin_read32(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)		bfin_write32(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_CURR_X_COUNT()		bfin_read32(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)	bfin_write32(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()		bfin_read32(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)	bfin_write32(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_BWL_COUNT()		bfin_read32(DMA6_BWL_COUNT)
-#define bfin_write_DMA6_BWL_COUNT(val)		bfin_write32(DMA6_BWL_COUNT, val)
-#define bfin_read_DMA6_CURR_BWL_COUNT()		bfin_read32(DMA6_CURR_BWL_COUNT)
-#define bfin_write_DMA6_CURR_BWL_COUNT(val)	bfin_write32(DMA6_CURR_BWL_COUNT, val)
-#define bfin_read_DMA6_BWM_COUNT()		bfin_read32(DMA6_BWM_COUNT)
-#define bfin_write_DMA6_BWM_COUNT(val)		bfin_write32(DMA6_BWM_COUNT, val)
-#define bfin_read_DMA6_CURR_BWM_COUNT()		bfin_read32(DMA6_CURR_BWM_COUNT)
-#define bfin_write_DMA6_CURR_BWM_COUNT(val)	bfin_write32(DMA6_CURR_BWM_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() 		bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) 	bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() 		bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) 	bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()			bfin_read32(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)		bfin_write32(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()		bfin_read32(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)		bfin_write32(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()		bfin_read32(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) 		bfin_write32(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()		bfin_read32(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)		bfin_write32(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()		bfin_read32(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) 		bfin_write32(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() 		bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) 	bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_PREV_DESC_PTR() 		bfin_read32(DMA7_PREV_DESC_PTR)
-#define bfin_write_DMA7_PREV_DESC_PTR(val) 	bfin_write32(DMA7_PREV_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() 		bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) 		bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()		bfin_read32(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)		bfin_write32(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_CURR_X_COUNT()		bfin_read32(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)	bfin_write32(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()		bfin_read32(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)	bfin_write32(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_BWL_COUNT()		bfin_read32(DMA7_BWL_COUNT)
-#define bfin_write_DMA7_BWL_COUNT(val)		bfin_write32(DMA7_BWL_COUNT, val)
-#define bfin_read_DMA7_CURR_BWL_COUNT()		bfin_read32(DMA7_CURR_BWL_COUNT)
-#define bfin_write_DMA7_CURR_BWL_COUNT(val)	bfin_write32(DMA7_CURR_BWL_COUNT, val)
-#define bfin_read_DMA7_BWM_COUNT()		bfin_read32(DMA7_BWM_COUNT)
-#define bfin_write_DMA7_BWM_COUNT(val)		bfin_write32(DMA7_BWM_COUNT, val)
-#define bfin_read_DMA7_CURR_BWM_COUNT()		bfin_read32(DMA7_CURR_BWM_COUNT)
-#define bfin_write_DMA7_CURR_BWM_COUNT(val)	bfin_write32(DMA7_CURR_BWM_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() 		bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) 	bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() 		bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) 	bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()			bfin_read32(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)		bfin_write32(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()		bfin_read32(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)		bfin_write32(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()		bfin_read32(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) 		bfin_write32(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()		bfin_read32(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)		bfin_write32(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()		bfin_read32(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) 		bfin_write32(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() 		bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) 	bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_PREV_DESC_PTR() 		bfin_read32(DMA8_PREV_DESC_PTR)
-#define bfin_write_DMA8_PREV_DESC_PTR(val) 	bfin_write32(DMA8_PREV_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() 		bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) 		bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()		bfin_read32(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)		bfin_write32(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_CURR_X_COUNT()		bfin_read32(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)	bfin_write32(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()		bfin_read32(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)	bfin_write32(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_BWL_COUNT()		bfin_read32(DMA8_BWL_COUNT)
-#define bfin_write_DMA8_BWL_COUNT(val)		bfin_write32(DMA8_BWL_COUNT, val)
-#define bfin_read_DMA8_CURR_BWL_COUNT()		bfin_read32(DMA8_CURR_BWL_COUNT)
-#define bfin_write_DMA8_CURR_BWL_COUNT(val)	bfin_write32(DMA8_CURR_BWL_COUNT, val)
-#define bfin_read_DMA8_BWM_COUNT()		bfin_read32(DMA8_BWM_COUNT)
-#define bfin_write_DMA8_BWM_COUNT(val)		bfin_write32(DMA8_BWM_COUNT, val)
-#define bfin_read_DMA8_CURR_BWM_COUNT()		bfin_read32(DMA8_CURR_BWM_COUNT)
-#define bfin_write_DMA8_CURR_BWM_COUNT(val)	bfin_write32(DMA8_CURR_BWM_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() 		bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) 	bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() 		bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) 	bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()			bfin_read32(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)		bfin_write32(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()		bfin_read32(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)		bfin_write32(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()		bfin_read32(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) 		bfin_write32(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()		bfin_read32(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)		bfin_write32(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()		bfin_read32(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) 		bfin_write32(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() 		bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) 	bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_PREV_DESC_PTR() 		bfin_read32(DMA9_PREV_DESC_PTR)
-#define bfin_write_DMA9_PREV_DESC_PTR(val) 	bfin_write32(DMA9_PREV_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() 		bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) 		bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()		bfin_read32(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)		bfin_write32(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_CURR_X_COUNT()		bfin_read32(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)	bfin_write32(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()		bfin_read32(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)	bfin_write32(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_BWL_COUNT()		bfin_read32(DMA9_BWL_COUNT)
-#define bfin_write_DMA9_BWL_COUNT(val)		bfin_write32(DMA9_BWL_COUNT, val)
-#define bfin_read_DMA9_CURR_BWL_COUNT()		bfin_read32(DMA9_CURR_BWL_COUNT)
-#define bfin_write_DMA9_CURR_BWL_COUNT(val)	bfin_write32(DMA9_CURR_BWL_COUNT, val)
-#define bfin_read_DMA9_BWM_COUNT()		bfin_read32(DMA9_BWM_COUNT)
-#define bfin_write_DMA9_BWM_COUNT(val)		bfin_write32(DMA9_BWM_COUNT, val)
-#define bfin_read_DMA9_CURR_BWM_COUNT()		bfin_read32(DMA9_CURR_BWM_COUNT)
-#define bfin_write_DMA9_CURR_BWM_COUNT(val)	bfin_write32(DMA9_CURR_BWM_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() 	bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) 	bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() 		bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) 	bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()		bfin_read32(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)		bfin_write32(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()		bfin_read32(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)		bfin_write32(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()		bfin_read32(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) 		bfin_write32(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()		bfin_read32(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)		bfin_write32(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()		bfin_read32(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) 		bfin_write32(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() 	bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) 	bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_PREV_DESC_PTR() 	bfin_read32(DMA10_PREV_DESC_PTR)
-#define bfin_write_DMA10_PREV_DESC_PTR(val) 	bfin_write32(DMA10_PREV_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() 		bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) 	bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()		bfin_read32(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)	bfin_write32(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_CURR_X_COUNT()		bfin_read32(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)	bfin_write32(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()		bfin_read32(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)	bfin_write32(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_BWL_COUNT()		bfin_read32(DMA10_BWL_COUNT)
-#define bfin_write_DMA10_BWL_COUNT(val)		bfin_write32(DMA10_BWL_COUNT, val)
-#define bfin_read_DMA10_CURR_BWL_COUNT()	bfin_read32(DMA10_CURR_BWL_COUNT)
-#define bfin_write_DMA10_CURR_BWL_COUNT(val)	bfin_write32(DMA10_CURR_BWL_COUNT, val)
-#define bfin_read_DMA10_BWM_COUNT()		bfin_read32(DMA10_BWM_COUNT)
-#define bfin_write_DMA10_BWM_COUNT(val)		bfin_write32(DMA10_BWM_COUNT, val)
-#define bfin_read_DMA10_CURR_BWM_COUNT()	bfin_read32(DMA10_CURR_BWM_COUNT)
-#define bfin_write_DMA10_CURR_BWM_COUNT(val)	bfin_write32(DMA10_CURR_BWM_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() 	bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) 	bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() 		bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) 	bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()		bfin_read32(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)		bfin_write32(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()		bfin_read32(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)		bfin_write32(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()		bfin_read32(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) 		bfin_write32(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()		bfin_read32(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)		bfin_write32(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()		bfin_read32(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) 		bfin_write32(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() 	bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) 	bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_PREV_DESC_PTR() 	bfin_read32(DMA11_PREV_DESC_PTR)
-#define bfin_write_DMA11_PREV_DESC_PTR(val) 	bfin_write32(DMA11_PREV_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() 		bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) 	bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()		bfin_read32(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)	bfin_write32(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_CURR_X_COUNT()		bfin_read32(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)	bfin_write32(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()		bfin_read32(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)	bfin_write32(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_BWL_COUNT()		bfin_read32(DMA11_BWL_COUNT)
-#define bfin_write_DMA11_BWL_COUNT(val)		bfin_write32(DMA11_BWL_COUNT, val)
-#define bfin_read_DMA11_CURR_BWL_COUNT()	bfin_read32(DMA11_CURR_BWL_COUNT)
-#define bfin_write_DMA11_CURR_BWL_COUNT(val)	bfin_write32(DMA11_CURR_BWL_COUNT, val)
-#define bfin_read_DMA11_BWM_COUNT()		bfin_read32(DMA11_BWM_COUNT)
-#define bfin_write_DMA11_BWM_COUNT(val)		bfin_write32(DMA11_BWM_COUNT, val)
-#define bfin_read_DMA11_CURR_BWM_COUNT()	bfin_read32(DMA11_CURR_BWM_COUNT)
-#define bfin_write_DMA11_CURR_BWM_COUNT(val)	bfin_write32(DMA11_CURR_BWM_COUNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() 	bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) 	bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() 		bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) 	bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()		bfin_read32(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)		bfin_write32(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()		bfin_read32(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)		bfin_write32(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()		bfin_read32(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) 		bfin_write32(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()		bfin_read32(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)		bfin_write32(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()		bfin_read32(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) 		bfin_write32(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() 	bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) 	bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_PREV_DESC_PTR() 	bfin_read32(DMA12_PREV_DESC_PTR)
-#define bfin_write_DMA12_PREV_DESC_PTR(val) 	bfin_write32(DMA12_PREV_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() 		bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) 	bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()		bfin_read32(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val)	bfin_write32(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_CURR_X_COUNT()		bfin_read32(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val)	bfin_write32(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT()		bfin_read32(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val)	bfin_write32(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_BWL_COUNT()		bfin_read32(DMA12_BWL_COUNT)
-#define bfin_write_DMA12_BWL_COUNT(val)		bfin_write32(DMA12_BWL_COUNT, val)
-#define bfin_read_DMA12_CURR_BWL_COUNT()	bfin_read32(DMA12_CURR_BWL_COUNT)
-#define bfin_write_DMA12_CURR_BWL_COUNT(val)	bfin_write32(DMA12_CURR_BWL_COUNT, val)
-#define bfin_read_DMA12_BWM_COUNT()		bfin_read32(DMA12_BWM_COUNT)
-#define bfin_write_DMA12_BWM_COUNT(val)		bfin_write32(DMA12_BWM_COUNT, val)
-#define bfin_read_DMA12_CURR_BWM_COUNT()	bfin_read32(DMA12_CURR_BWM_COUNT)
-#define bfin_write_DMA12_CURR_BWM_COUNT(val)	bfin_write32(DMA12_CURR_BWM_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() 	bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) 	bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() 		bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) 	bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()		bfin_read32(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)		bfin_write32(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()		bfin_read32(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)		bfin_write32(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()		bfin_read32(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) 		bfin_write32(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()		bfin_read32(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)		bfin_write32(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()		bfin_read32(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) 		bfin_write32(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() 	bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) 	bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_PREV_DESC_PTR() 	bfin_read32(DMA13_PREV_DESC_PTR)
-#define bfin_write_DMA13_PREV_DESC_PTR(val) 	bfin_write32(DMA13_PREV_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() 		bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) 	bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()		bfin_read32(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val)	bfin_write32(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_CURR_X_COUNT()		bfin_read32(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val)	bfin_write32(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT()		bfin_read32(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val)	bfin_write32(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_BWL_COUNT()		bfin_read32(DMA13_BWL_COUNT)
-#define bfin_write_DMA13_BWL_COUNT(val)		bfin_write32(DMA13_BWL_COUNT, val)
-#define bfin_read_DMA13_CURR_BWL_COUNT()	bfin_read32(DMA13_CURR_BWL_COUNT)
-#define bfin_write_DMA13_CURR_BWL_COUNT(val)	bfin_write32(DMA13_CURR_BWL_COUNT, val)
-#define bfin_read_DMA13_BWM_COUNT()		bfin_read32(DMA13_BWM_COUNT)
-#define bfin_write_DMA13_BWM_COUNT(val)		bfin_write32(DMA13_BWM_COUNT, val)
-#define bfin_read_DMA13_CURR_BWM_COUNT()	bfin_read32(DMA13_CURR_BWM_COUNT)
-#define bfin_write_DMA13_CURR_BWM_COUNT(val)	bfin_write32(DMA13_CURR_BWM_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() 	bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) 	bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() 		bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) 	bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()		bfin_read32(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)		bfin_write32(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()		bfin_read32(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)		bfin_write32(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()		bfin_read32(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) 		bfin_write32(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()		bfin_read32(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)		bfin_write32(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()		bfin_read32(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) 		bfin_write32(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() 	bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) 	bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_PREV_DESC_PTR() 	bfin_read32(DMA14_PREV_DESC_PTR)
-#define bfin_write_DMA14_PREV_DESC_PTR(val) 	bfin_write32(DMA14_PREV_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() 		bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) 	bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()		bfin_read32(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val)	bfin_write32(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_CURR_X_COUNT()		bfin_read32(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val)	bfin_write32(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT()		bfin_read32(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val)	bfin_write32(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_BWL_COUNT()		bfin_read32(DMA14_BWL_COUNT)
-#define bfin_write_DMA14_BWL_COUNT(val)		bfin_write32(DMA14_BWL_COUNT, val)
-#define bfin_read_DMA14_CURR_BWL_COUNT()	bfin_read32(DMA14_CURR_BWL_COUNT)
-#define bfin_write_DMA14_CURR_BWL_COUNT(val)	bfin_write32(DMA14_CURR_BWL_COUNT, val)
-#define bfin_read_DMA14_BWM_COUNT()		bfin_read32(DMA14_BWM_COUNT)
-#define bfin_write_DMA14_BWM_COUNT(val)		bfin_write32(DMA14_BWM_COUNT, val)
-#define bfin_read_DMA14_CURR_BWM_COUNT()	bfin_read32(DMA14_CURR_BWM_COUNT)
-#define bfin_write_DMA14_CURR_BWM_COUNT(val)	bfin_write32(DMA14_CURR_BWM_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() 	bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) 	bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() 		bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) 	bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()		bfin_read32(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)		bfin_write32(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()		bfin_read32(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)		bfin_write32(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()		bfin_read32(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) 		bfin_write32(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()		bfin_read32(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)		bfin_write32(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()		bfin_read32(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) 		bfin_write32(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() 	bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) 	bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_PREV_DESC_PTR() 	bfin_read32(DMA15_PREV_DESC_PTR)
-#define bfin_write_DMA15_PREV_DESC_PTR(val) 	bfin_write32(DMA15_PREV_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() 		bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) 	bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()		bfin_read32(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val)	bfin_write32(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_CURR_X_COUNT()		bfin_read32(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val)	bfin_write32(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT()		bfin_read32(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val)	bfin_write32(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_BWL_COUNT()		bfin_read32(DMA15_BWL_COUNT)
-#define bfin_write_DMA15_BWL_COUNT(val)		bfin_write32(DMA15_BWL_COUNT, val)
-#define bfin_read_DMA15_CURR_BWL_COUNT()	bfin_read32(DMA15_CURR_BWL_COUNT)
-#define bfin_write_DMA15_CURR_BWL_COUNT(val)	bfin_write32(DMA15_CURR_BWL_COUNT, val)
-#define bfin_read_DMA15_BWM_COUNT()		bfin_read32(DMA15_BWM_COUNT)
-#define bfin_write_DMA15_BWM_COUNT(val)		bfin_write32(DMA15_BWM_COUNT, val)
-#define bfin_read_DMA15_CURR_BWM_COUNT()	bfin_read32(DMA15_CURR_BWM_COUNT)
-#define bfin_write_DMA15_CURR_BWM_COUNT(val)	bfin_write32(DMA15_CURR_BWM_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() 	bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) 	bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() 		bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) 	bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()		bfin_read32(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)		bfin_write32(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()		bfin_read32(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)		bfin_write32(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()		bfin_read32(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) 		bfin_write32(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()		bfin_read32(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)		bfin_write32(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()		bfin_read32(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) 		bfin_write32(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() 	bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) 	bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_PREV_DESC_PTR() 	bfin_read32(DMA16_PREV_DESC_PTR)
-#define bfin_write_DMA16_PREV_DESC_PTR(val) 	bfin_write32(DMA16_PREV_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() 		bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) 	bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()		bfin_read32(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val)	bfin_write32(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_CURR_X_COUNT()		bfin_read32(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val)	bfin_write32(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT()		bfin_read32(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val)	bfin_write32(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_BWL_COUNT()		bfin_read32(DMA16_BWL_COUNT)
-#define bfin_write_DMA16_BWL_COUNT(val)		bfin_write32(DMA16_BWL_COUNT, val)
-#define bfin_read_DMA16_CURR_BWL_COUNT()	bfin_read32(DMA16_CURR_BWL_COUNT)
-#define bfin_write_DMA16_CURR_BWL_COUNT(val)	bfin_write32(DMA16_CURR_BWL_COUNT, val)
-#define bfin_read_DMA16_BWM_COUNT()		bfin_read32(DMA16_BWM_COUNT)
-#define bfin_write_DMA16_BWM_COUNT(val)		bfin_write32(DMA16_BWM_COUNT, val)
-#define bfin_read_DMA16_CURR_BWM_COUNT()	bfin_read32(DMA16_CURR_BWM_COUNT)
-#define bfin_write_DMA16_CURR_BWM_COUNT(val)	bfin_write32(DMA16_CURR_BWM_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() 	bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) 	bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() 		bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) 	bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()		bfin_read32(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)		bfin_write32(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()		bfin_read32(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)		bfin_write32(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()		bfin_read32(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) 		bfin_write32(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()		bfin_read32(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)		bfin_write32(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()		bfin_read32(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) 		bfin_write32(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() 	bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) 	bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_PREV_DESC_PTR() 	bfin_read32(DMA17_PREV_DESC_PTR)
-#define bfin_write_DMA17_PREV_DESC_PTR(val) 	bfin_write32(DMA17_PREV_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() 		bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) 	bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()		bfin_read32(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val)	bfin_write32(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_CURR_X_COUNT()		bfin_read32(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val)	bfin_write32(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT()		bfin_read32(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val)	bfin_write32(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_BWL_COUNT()		bfin_read32(DMA17_BWL_COUNT)
-#define bfin_write_DMA17_BWL_COUNT(val)		bfin_write32(DMA17_BWL_COUNT, val)
-#define bfin_read_DMA17_CURR_BWL_COUNT()	bfin_read32(DMA17_CURR_BWL_COUNT)
-#define bfin_write_DMA17_CURR_BWL_COUNT(val)	bfin_write32(DMA17_CURR_BWL_COUNT, val)
-#define bfin_read_DMA17_BWM_COUNT()		bfin_read32(DMA17_BWM_COUNT)
-#define bfin_write_DMA17_BWM_COUNT(val)		bfin_write32(DMA17_BWM_COUNT, val)
-#define bfin_read_DMA17_CURR_BWM_COUNT()	bfin_read32(DMA17_CURR_BWM_COUNT)
-#define bfin_write_DMA17_CURR_BWM_COUNT(val)	bfin_write32(DMA17_CURR_BWM_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() 	bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) 	bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() 		bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) 	bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()		bfin_read32(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)		bfin_write32(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()		bfin_read32(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)		bfin_write32(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()		bfin_read32(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) 		bfin_write32(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()		bfin_read32(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)		bfin_write32(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()		bfin_read32(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) 		bfin_write32(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() 	bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) 	bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_PREV_DESC_PTR() 	bfin_read32(DMA18_PREV_DESC_PTR)
-#define bfin_write_DMA18_PREV_DESC_PTR(val) 	bfin_write32(DMA18_PREV_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() 		bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) 	bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()		bfin_read32(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val)	bfin_write32(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_CURR_X_COUNT()		bfin_read32(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val)	bfin_write32(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT()		bfin_read32(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val)	bfin_write32(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_BWL_COUNT()		bfin_read32(DMA18_BWL_COUNT)
-#define bfin_write_DMA18_BWL_COUNT(val)		bfin_write32(DMA18_BWL_COUNT, val)
-#define bfin_read_DMA18_CURR_BWL_COUNT()	bfin_read32(DMA18_CURR_BWL_COUNT)
-#define bfin_write_DMA18_CURR_BWL_COUNT(val)	bfin_write32(DMA18_CURR_BWL_COUNT, val)
-#define bfin_read_DMA18_BWM_COUNT()		bfin_read32(DMA18_BWM_COUNT)
-#define bfin_write_DMA18_BWM_COUNT(val)		bfin_write32(DMA18_BWM_COUNT, val)
-#define bfin_read_DMA18_CURR_BWM_COUNT()	bfin_read32(DMA18_CURR_BWM_COUNT)
-#define bfin_write_DMA18_CURR_BWM_COUNT(val)	bfin_write32(DMA18_CURR_BWM_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() 	bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) 	bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() 		bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) 	bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()		bfin_read32(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)		bfin_write32(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()		bfin_read32(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)		bfin_write32(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()		bfin_read32(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) 		bfin_write32(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()		bfin_read32(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)		bfin_write32(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()		bfin_read32(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) 		bfin_write32(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() 	bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) 	bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_PREV_DESC_PTR() 	bfin_read32(DMA19_PREV_DESC_PTR)
-#define bfin_write_DMA19_PREV_DESC_PTR(val) 	bfin_write32(DMA19_PREV_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() 		bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) 	bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()		bfin_read32(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val)	bfin_write32(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_CURR_X_COUNT()		bfin_read32(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val)	bfin_write32(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT()		bfin_read32(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val)	bfin_write32(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_BWL_COUNT()		bfin_read32(DMA19_BWL_COUNT)
-#define bfin_write_DMA19_BWL_COUNT(val)		bfin_write32(DMA19_BWL_COUNT, val)
-#define bfin_read_DMA19_CURR_BWL_COUNT()	bfin_read32(DMA19_CURR_BWL_COUNT)
-#define bfin_write_DMA19_CURR_BWL_COUNT(val)	bfin_write32(DMA19_CURR_BWL_COUNT, val)
-#define bfin_read_DMA19_BWM_COUNT()		bfin_read32(DMA19_BWM_COUNT)
-#define bfin_write_DMA19_BWM_COUNT(val)		bfin_write32(DMA19_BWM_COUNT, val)
-#define bfin_read_DMA19_CURR_BWM_COUNT()	bfin_read32(DMA19_CURR_BWM_COUNT)
-#define bfin_write_DMA19_CURR_BWM_COUNT(val)	bfin_write32(DMA19_CURR_BWM_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() 	bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) 	bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() 		bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) 	bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()		bfin_read32(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)		bfin_write32(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()		bfin_read32(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)		bfin_write32(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()		bfin_read32(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) 		bfin_write32(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()		bfin_read32(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)		bfin_write32(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()		bfin_read32(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) 		bfin_write32(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() 	bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) 	bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_PREV_DESC_PTR() 	bfin_read32(DMA20_PREV_DESC_PTR)
-#define bfin_write_DMA20_PREV_DESC_PTR(val) 	bfin_write32(DMA20_PREV_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() 		bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) 	bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()		bfin_read32(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val)	bfin_write32(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_CURR_X_COUNT()		bfin_read32(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val)	bfin_write32(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT()		bfin_read32(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val)	bfin_write32(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_BWL_COUNT()		bfin_read32(DMA20_BWL_COUNT)
-#define bfin_write_DMA20_BWL_COUNT(val)		bfin_write32(DMA20_BWL_COUNT, val)
-#define bfin_read_DMA20_CURR_BWL_COUNT()	bfin_read32(DMA20_CURR_BWL_COUNT)
-#define bfin_write_DMA20_CURR_BWL_COUNT(val)	bfin_write32(DMA20_CURR_BWL_COUNT, val)
-#define bfin_read_DMA20_BWM_COUNT()		bfin_read32(DMA20_BWM_COUNT)
-#define bfin_write_DMA20_BWM_COUNT(val)		bfin_write32(DMA20_BWM_COUNT, val)
-#define bfin_read_DMA20_CURR_BWM_COUNT()	bfin_read32(DMA20_CURR_BWM_COUNT)
-#define bfin_write_DMA20_CURR_BWM_COUNT(val)	bfin_write32(DMA20_CURR_BWM_COUNT, val)
-
-
-/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
-
-#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() 		bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) 	bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CONFIG()		bfin_read32(MDMA0_DEST_CRC0_CONFIG)
-#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val)		bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_COUNT()		bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val)		bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY()		bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) 	bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT()		bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val)		bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY()		bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) 	bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() 	bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) 	bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() 		bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) 	bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS()		bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val)	bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT()	bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val)	bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT()	bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val)	bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() 		bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) 	bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CONFIG()		bfin_read32(MDMA0_SRC_CRC0_CONFIG)
-#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val)		bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_COUNT()		bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val)		bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY()		bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) 	bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT()		bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val)		bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY()		bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) 	bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() 	bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) 	bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() 		bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) 	bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS()		bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val)	bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT()		bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val)	bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT()		bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val)	bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
-
-#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() 		bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) 	bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CONFIG()		bfin_read32(MDMA1_DEST_CRC1_CONFIG)
-#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val)		bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_COUNT()		bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val)		bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY()		bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) 	bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT()		bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val)		bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY()		bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) 	bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() 	bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) 	bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() 		bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) 	bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS()		bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val)	bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT()	bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val)	bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT()	bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val)	bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() 		bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) 	bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CONFIG()		bfin_read32(MDMA1_SRC_CRC1_CONFIG)
-#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val)		bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_COUNT()		bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val)		bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY()		bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) 	bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT()		bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val)		bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY()		bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) 	bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() 	bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) 	bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() 		bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) 	bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS()		bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val)	bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT()		bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val)	bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT()		bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val)	bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
-
-
-/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
-
-#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() 		bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_START_ADDR() 		bfin_read32(MDMA2_DEST_START_ADDR)
-#define bfin_write_MDMA2_DEST_START_ADDR(val) 		bfin_write32(MDMA2_DEST_START_ADDR, val)
-#define bfin_read_MDMA2_DEST_CONFIG()			bfin_read32(MDMA2_DEST_CONFIG)
-#define bfin_write_MDMA2_DEST_CONFIG(val)		bfin_write32(MDMA2_DEST_CONFIG, val)
-#define bfin_read_MDMA2_DEST_X_COUNT()			bfin_read32(MDMA2_DEST_X_COUNT)
-#define bfin_write_MDMA2_DEST_X_COUNT(val)		bfin_write32(MDMA2_DEST_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_X_MODIFY()			bfin_read32(MDMA2_DEST_X_MODIFY)
-#define bfin_write_MDMA2_DEST_X_MODIFY(val) 		bfin_write32(MDMA2_DEST_X_MODIFY, val)
-#define bfin_read_MDMA2_DEST_Y_COUNT()			bfin_read32(MDMA2_DEST_Y_COUNT)
-#define bfin_write_MDMA2_DEST_Y_COUNT(val)		bfin_write32(MDMA2_DEST_Y_COUNT, val)
-#define bfin_read_MDMA2_DEST_Y_MODIFY()			bfin_read32(MDMA2_DEST_Y_MODIFY)
-#define bfin_write_MDMA2_DEST_Y_MODIFY(val) 		bfin_write32(MDMA2_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() 		bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() 		bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) 	bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_CURR_ADDR() 		bfin_read32(MDMA2_DEST_CURR_ADDR)
-#define bfin_write_MDMA2_DEST_CURR_ADDR(val) 		bfin_write32(MDMA2_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA2_DEST_IRQ_STATUS()		bfin_read32(MDMA2_DEST_IRQ_STATUS)
-#define bfin_write_MDMA2_DEST_IRQ_STATUS(val)		bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA2_DEST_CURR_X_COUNT()		bfin_read32(MDMA2_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val)		bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_CURR_Y_COUNT()		bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val)		bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() 		bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) 	bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_START_ADDR() 		bfin_read32(MDMA2_SRC_START_ADDR)
-#define bfin_write_MDMA2_SRC_START_ADDR(val) 		bfin_write32(MDMA2_SRC_START_ADDR, val)
-#define bfin_read_MDMA2_SRC_CONFIG()			bfin_read32(MDMA2_SRC_CONFIG)
-#define bfin_write_MDMA2_SRC_CONFIG(val)		bfin_write32(MDMA2_SRC_CONFIG, val)
-#define bfin_read_MDMA2_SRC_X_COUNT()			bfin_read32(MDMA2_SRC_X_COUNT)
-#define bfin_write_MDMA2_SRC_X_COUNT(val)		bfin_write32(MDMA2_SRC_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_X_MODIFY()			bfin_read32(MDMA2_SRC_X_MODIFY)
-#define bfin_write_MDMA2_SRC_X_MODIFY(val) 		bfin_write32(MDMA2_SRC_X_MODIFY, val)
-#define bfin_read_MDMA2_SRC_Y_COUNT()			bfin_read32(MDMA2_SRC_Y_COUNT)
-#define bfin_write_MDMA2_SRC_Y_COUNT(val)		bfin_write32(MDMA2_SRC_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_Y_MODIFY()			bfin_read32(MDMA2_SRC_Y_MODIFY)
-#define bfin_write_MDMA2_SRC_Y_MODIFY(val) 		bfin_write32(MDMA2_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() 		bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val)		bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() 		bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) 	bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_CURR_ADDR() 		bfin_read32(MDMA2_SRC_CURR_ADDR)
-#define bfin_write_MDMA2_SRC_CURR_ADDR(val) 		bfin_write32(MDMA2_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA2_SRC_IRQ_STATUS()		bfin_read32(MDMA2_SRC_IRQ_STATUS)
-#define bfin_write_MDMA2_SRC_IRQ_STATUS(val)		bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA2_SRC_CURR_X_COUNT()		bfin_read32(MDMA2_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val)		bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_CURR_Y_COUNT()		bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val)		bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
-
-#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() 		bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_START_ADDR() 		bfin_read32(MDMA3_DEST_START_ADDR)
-#define bfin_write_MDMA3_DEST_START_ADDR(val) 		bfin_write32(MDMA3_DEST_START_ADDR, val)
-#define bfin_read_MDMA3_DEST_CONFIG()			bfin_read32(MDMA3_DEST_CONFIG)
-#define bfin_write_MDMA3_DEST_CONFIG(val)		bfin_write32(MDMA3_DEST_CONFIG, val)
-#define bfin_read_MDMA3_DEST_X_COUNT()			bfin_read32(MDMA3_DEST_X_COUNT)
-#define bfin_write_MDMA3_DEST_X_COUNT(val)		bfin_write32(MDMA3_DEST_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_X_MODIFY()			bfin_read32(MDMA3_DEST_X_MODIFY)
-#define bfin_write_MDMA3_DEST_X_MODIFY(val) 		bfin_write32(MDMA3_DEST_X_MODIFY, val)
-#define bfin_read_MDMA3_DEST_Y_COUNT()			bfin_read32(MDMA3_DEST_Y_COUNT)
-#define bfin_write_MDMA3_DEST_Y_COUNT(val)		bfin_write32(MDMA3_DEST_Y_COUNT, val)
-#define bfin_read_MDMA3_DEST_Y_MODIFY()			bfin_read32(MDMA3_DEST_Y_MODIFY)
-#define bfin_write_MDMA3_DEST_Y_MODIFY(val) 		bfin_write32(MDMA3_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() 		bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_PREV_DESC_PTR()	 	bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) 	bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_CURR_ADDR() 		bfin_read32(MDMA3_DEST_CURR_ADDR)
-#define bfin_write_MDMA3_DEST_CURR_ADDR(val) 		bfin_write32(MDMA3_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA3_DEST_IRQ_STATUS()		bfin_read32(MDMA3_DEST_IRQ_STATUS)
-#define bfin_write_MDMA3_DEST_IRQ_STATUS(val)		bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA3_DEST_CURR_X_COUNT()		bfin_read32(MDMA3_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val)		bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_CURR_Y_COUNT()		bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val)		bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() 		bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_START_ADDR() 		bfin_read32(MDMA3_SRC_START_ADDR)
-#define bfin_write_MDMA3_SRC_START_ADDR(val) 		bfin_write32(MDMA3_SRC_START_ADDR, val)
-#define bfin_read_MDMA3_SRC_CONFIG()			bfin_read32(MDMA3_SRC_CONFIG)
-#define bfin_write_MDMA3_SRC_CONFIG(val)		bfin_write32(MDMA3_SRC_CONFIG, val)
-#define bfin_read_MDMA3_SRC_X_COUNT()			bfin_read32(MDMA3_SRC_X_COUNT)
-#define bfin_write_MDMA3_SRC_X_COUNT(val)		bfin_write32(MDMA3_SRC_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_X_MODIFY()			bfin_read32(MDMA3_SRC_X_MODIFY)
-#define bfin_write_MDMA3_SRC_X_MODIFY(val) 		bfin_write32(MDMA3_SRC_X_MODIFY, val)
-#define bfin_read_MDMA3_SRC_Y_COUNT()			bfin_read32(MDMA3_SRC_Y_COUNT)
-#define bfin_write_MDMA3_SRC_Y_COUNT(val)		bfin_write32(MDMA3_SRC_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_Y_MODIFY()			bfin_read32(MDMA3_SRC_Y_MODIFY)
-#define bfin_write_MDMA3_SRC_Y_MODIFY(val) 		bfin_write32(MDMA3_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() 		bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() 		bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) 	bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_CURR_ADDR() 		bfin_read32(MDMA3_SRC_CURR_ADDR)
-#define bfin_write_MDMA3_SRC_CURR_ADDR(val) 		bfin_write32(MDMA3_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA3_SRC_IRQ_STATUS()		bfin_read32(MDMA3_SRC_IRQ_STATUS)
-#define bfin_write_MDMA3_SRC_IRQ_STATUS(val)		bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA3_SRC_CURR_X_COUNT()		bfin_read32(MDMA3_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val)		bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_CURR_Y_COUNT()		bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val)		bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
-
-
-/* DMA Channel 29 Registers */
-
-#define bfin_read_DMA29_NEXT_DESC_PTR() 	bfin_read32(DMA29_NEXT_DESC_PTR)
-#define bfin_write_DMA29_NEXT_DESC_PTR(val) 	bfin_write32(DMA29_NEXT_DESC_PTR, val)
-#define bfin_read_DMA29_START_ADDR() 		bfin_read32(DMA29_START_ADDR)
-#define bfin_write_DMA29_START_ADDR(val) 	bfin_write32(DMA29_START_ADDR, val)
-#define bfin_read_DMA29_CONFIG()		bfin_read32(DMA29_CONFIG)
-#define bfin_write_DMA29_CONFIG(val)		bfin_write32(DMA29_CONFIG, val)
-#define bfin_read_DMA29_X_COUNT()		bfin_read32(DMA29_X_COUNT)
-#define bfin_write_DMA29_X_COUNT(val)		bfin_write32(DMA29_X_COUNT, val)
-#define bfin_read_DMA29_X_MODIFY()		bfin_read32(DMA29_X_MODIFY)
-#define bfin_write_DMA29_X_MODIFY(val) 		bfin_write32(DMA29_X_MODIFY, val)
-#define bfin_read_DMA29_Y_COUNT()		bfin_read32(DMA29_Y_COUNT)
-#define bfin_write_DMA29_Y_COUNT(val)		bfin_write32(DMA29_Y_COUNT, val)
-#define bfin_read_DMA29_Y_MODIFY()		bfin_read32(DMA29_Y_MODIFY)
-#define bfin_write_DMA29_Y_MODIFY(val) 		bfin_write32(DMA29_Y_MODIFY, val)
-#define bfin_read_DMA29_CURR_DESC_PTR() 	bfin_read32(DMA29_CURR_DESC_PTR)
-#define bfin_write_DMA29_CURR_DESC_PTR(val) 	bfin_write32(DMA29_CURR_DESC_PTR, val)
-#define bfin_read_DMA29_PREV_DESC_PTR() 	bfin_read32(DMA29_PREV_DESC_PTR)
-#define bfin_write_DMA29_PREV_DESC_PTR(val) 	bfin_write32(DMA29_PREV_DESC_PTR, val)
-#define bfin_read_DMA29_CURR_ADDR() 		bfin_read32(DMA29_CURR_ADDR)
-#define bfin_write_DMA29_CURR_ADDR(val) 	bfin_write32(DMA29_CURR_ADDR, val)
-#define bfin_read_DMA29_IRQ_STATUS()		bfin_read32(DMA29_IRQ_STATUS)
-#define bfin_write_DMA29_IRQ_STATUS(val)	bfin_write32(DMA29_IRQ_STATUS, val)
-#define bfin_read_DMA29_CURR_X_COUNT()		bfin_read32(DMA29_CURR_X_COUNT)
-#define bfin_write_DMA29_CURR_X_COUNT(val)	bfin_write32(DMA29_CURR_X_COUNT, val)
-#define bfin_read_DMA29_CURR_Y_COUNT()		bfin_read32(DMA29_CURR_Y_COUNT)
-#define bfin_write_DMA29_CURR_Y_COUNT(val)	bfin_write32(DMA29_CURR_Y_COUNT, val)
-#define bfin_read_DMA29_BWL_COUNT()		bfin_read32(DMA29_BWL_COUNT)
-#define bfin_write_DMA29_BWL_COUNT(val)		bfin_write32(DMA29_BWL_COUNT, val)
-#define bfin_read_DMA29_CURR_BWL_COUNT()	bfin_read32(DMA29_CURR_BWL_COUNT)
-#define bfin_write_DMA29_CURR_BWL_COUNT(val)	bfin_write32(DMA29_CURR_BWL_COUNT, val)
-#define bfin_read_DMA29_BWM_COUNT()		bfin_read32(DMA29_BWM_COUNT)
-#define bfin_write_DMA29_BWM_COUNT(val)		bfin_write32(DMA29_BWM_COUNT, val)
-#define bfin_read_DMA29_CURR_BWM_COUNT()	bfin_read32(DMA29_CURR_BWM_COUNT)
-#define bfin_write_DMA29_CURR_BWM_COUNT(val)	bfin_write32(DMA29_CURR_BWM_COUNT, val)
-
-/* DMA Channel 30 Registers */
-
-#define bfin_read_DMA30_NEXT_DESC_PTR() 	bfin_read32(DMA30_NEXT_DESC_PTR)
-#define bfin_write_DMA30_NEXT_DESC_PTR(val) 	bfin_write32(DMA30_NEXT_DESC_PTR, val)
-#define bfin_read_DMA30_START_ADDR() 		bfin_read32(DMA30_START_ADDR)
-#define bfin_write_DMA30_START_ADDR(val) 	bfin_write32(DMA30_START_ADDR, val)
-#define bfin_read_DMA30_CONFIG()		bfin_read32(DMA30_CONFIG)
-#define bfin_write_DMA30_CONFIG(val)		bfin_write32(DMA30_CONFIG, val)
-#define bfin_read_DMA30_X_COUNT()		bfin_read32(DMA30_X_COUNT)
-#define bfin_write_DMA30_X_COUNT(val)		bfin_write32(DMA30_X_COUNT, val)
-#define bfin_read_DMA30_X_MODIFY()		bfin_read32(DMA30_X_MODIFY)
-#define bfin_write_DMA30_X_MODIFY(val) 		bfin_write32(DMA30_X_MODIFY, val)
-#define bfin_read_DMA30_Y_COUNT()		bfin_read32(DMA30_Y_COUNT)
-#define bfin_write_DMA30_Y_COUNT(val)		bfin_write32(DMA30_Y_COUNT, val)
-#define bfin_read_DMA30_Y_MODIFY()		bfin_read32(DMA30_Y_MODIFY)
-#define bfin_write_DMA30_Y_MODIFY(val) 		bfin_write32(DMA30_Y_MODIFY, val)
-#define bfin_read_DMA30_CURR_DESC_PTR() 	bfin_read32(DMA30_CURR_DESC_PTR)
-#define bfin_write_DMA30_CURR_DESC_PTR(val) 	bfin_write32(DMA30_CURR_DESC_PTR, val)
-#define bfin_read_DMA30_PREV_DESC_PTR() 	bfin_read32(DMA30_PREV_DESC_PTR)
-#define bfin_write_DMA30_PREV_DESC_PTR(val) 	bfin_write32(DMA30_PREV_DESC_PTR, val)
-#define bfin_read_DMA30_CURR_ADDR() 		bfin_read32(DMA30_CURR_ADDR)
-#define bfin_write_DMA30_CURR_ADDR(val) 	bfin_write32(DMA30_CURR_ADDR, val)
-#define bfin_read_DMA30_IRQ_STATUS()		bfin_read32(DMA30_IRQ_STATUS)
-#define bfin_write_DMA30_IRQ_STATUS(val)	bfin_write32(DMA30_IRQ_STATUS, val)
-#define bfin_read_DMA30_CURR_X_COUNT()		bfin_read32(DMA30_CURR_X_COUNT)
-#define bfin_write_DMA30_CURR_X_COUNT(val)	bfin_write32(DMA30_CURR_X_COUNT, val)
-#define bfin_read_DMA30_CURR_Y_COUNT()		bfin_read32(DMA30_CURR_Y_COUNT)
-#define bfin_write_DMA30_CURR_Y_COUNT(val)	bfin_write32(DMA30_CURR_Y_COUNT, val)
-#define bfin_read_DMA30_BWL_COUNT()		bfin_read32(DMA30_BWL_COUNT)
-#define bfin_write_DMA30_BWL_COUNT(val)		bfin_write32(DMA30_BWL_COUNT, val)
-#define bfin_read_DMA30_CURR_BWL_COUNT()	bfin_read32(DMA30_CURR_BWL_COUNT)
-#define bfin_write_DMA30_CURR_BWL_COUNT(val)	bfin_write32(DMA30_CURR_BWL_COUNT, val)
-#define bfin_read_DMA30_BWM_COUNT()		bfin_read32(DMA30_BWM_COUNT)
-#define bfin_write_DMA30_BWM_COUNT(val)		bfin_write32(DMA30_BWM_COUNT, val)
-#define bfin_read_DMA30_CURR_BWM_COUNT()	bfin_read32(DMA30_CURR_BWM_COUNT)
-#define bfin_write_DMA30_CURR_BWM_COUNT(val)	bfin_write32(DMA30_CURR_BWM_COUNT, val)
-
-/* DMA Channel 31 Registers */
-
-#define bfin_read_DMA31_NEXT_DESC_PTR() 	bfin_read32(DMA31_NEXT_DESC_PTR)
-#define bfin_write_DMA31_NEXT_DESC_PTR(val) 	bfin_write32(DMA31_NEXT_DESC_PTR, val)
-#define bfin_read_DMA31_START_ADDR() 		bfin_read32(DMA31_START_ADDR)
-#define bfin_write_DMA31_START_ADDR(val) 	bfin_write32(DMA31_START_ADDR, val)
-#define bfin_read_DMA31_CONFIG()		bfin_read32(DMA31_CONFIG)
-#define bfin_write_DMA31_CONFIG(val)		bfin_write32(DMA31_CONFIG, val)
-#define bfin_read_DMA31_X_COUNT()		bfin_read32(DMA31_X_COUNT)
-#define bfin_write_DMA31_X_COUNT(val)		bfin_write32(DMA31_X_COUNT, val)
-#define bfin_read_DMA31_X_MODIFY()		bfin_read32(DMA31_X_MODIFY)
-#define bfin_write_DMA31_X_MODIFY(val) 		bfin_write32(DMA31_X_MODIFY, val)
-#define bfin_read_DMA31_Y_COUNT()		bfin_read32(DMA31_Y_COUNT)
-#define bfin_write_DMA31_Y_COUNT(val)		bfin_write32(DMA31_Y_COUNT, val)
-#define bfin_read_DMA31_Y_MODIFY()		bfin_read32(DMA31_Y_MODIFY)
-#define bfin_write_DMA31_Y_MODIFY(val) 		bfin_write32(DMA31_Y_MODIFY, val)
-#define bfin_read_DMA31_CURR_DESC_PTR() 	bfin_read32(DMA31_CURR_DESC_PTR)
-#define bfin_write_DMA31_CURR_DESC_PTR(val) 	bfin_write32(DMA31_CURR_DESC_PTR, val)
-#define bfin_read_DMA31_PREV_DESC_PTR() 	bfin_read32(DMA31_PREV_DESC_PTR)
-#define bfin_write_DMA31_PREV_DESC_PTR(val) 	bfin_write32(DMA31_PREV_DESC_PTR, val)
-#define bfin_read_DMA31_CURR_ADDR() 		bfin_read32(DMA31_CURR_ADDR)
-#define bfin_write_DMA31_CURR_ADDR(val) 	bfin_write32(DMA31_CURR_ADDR, val)
-#define bfin_read_DMA31_IRQ_STATUS()		bfin_read32(DMA31_IRQ_STATUS)
-#define bfin_write_DMA31_IRQ_STATUS(val)	bfin_write32(DMA31_IRQ_STATUS, val)
-#define bfin_read_DMA31_CURR_X_COUNT()		bfin_read32(DMA31_CURR_X_COUNT)
-#define bfin_write_DMA31_CURR_X_COUNT(val)	bfin_write32(DMA31_CURR_X_COUNT, val)
-#define bfin_read_DMA31_CURR_Y_COUNT()		bfin_read32(DMA31_CURR_Y_COUNT)
-#define bfin_write_DMA31_CURR_Y_COUNT(val)	bfin_write32(DMA31_CURR_Y_COUNT, val)
-#define bfin_read_DMA31_BWL_COUNT()		bfin_read32(DMA31_BWL_COUNT)
-#define bfin_write_DMA31_BWL_COUNT(val)		bfin_write32(DMA31_BWL_COUNT, val)
-#define bfin_read_DMA31_CURR_BWL_COUNT()	bfin_read32(DMA31_CURR_BWL_COUNT)
-#define bfin_write_DMA31_CURR_BWL_COUNT(val)	bfin_write32(DMA31_CURR_BWL_COUNT, val)
-#define bfin_read_DMA31_BWM_COUNT()		bfin_read32(DMA31_BWM_COUNT)
-#define bfin_write_DMA31_BWM_COUNT(val)		bfin_write32(DMA31_BWM_COUNT, val)
-#define bfin_read_DMA31_CURR_BWM_COUNT()	bfin_read32(DMA31_CURR_BWM_COUNT)
-#define bfin_write_DMA31_CURR_BWM_COUNT(val)	bfin_write32(DMA31_CURR_BWM_COUNT, val)
-
-/* DMA Channel 32 Registers */
-
-#define bfin_read_DMA32_NEXT_DESC_PTR() 	bfin_read32(DMA32_NEXT_DESC_PTR)
-#define bfin_write_DMA32_NEXT_DESC_PTR(val) 	bfin_write32(DMA32_NEXT_DESC_PTR, val)
-#define bfin_read_DMA32_START_ADDR() 		bfin_read32(DMA32_START_ADDR)
-#define bfin_write_DMA32_START_ADDR(val) 	bfin_write32(DMA32_START_ADDR, val)
-#define bfin_read_DMA32_CONFIG()		bfin_read32(DMA32_CONFIG)
-#define bfin_write_DMA32_CONFIG(val)		bfin_write32(DMA32_CONFIG, val)
-#define bfin_read_DMA32_X_COUNT()		bfin_read32(DMA32_X_COUNT)
-#define bfin_write_DMA32_X_COUNT(val)		bfin_write32(DMA32_X_COUNT, val)
-#define bfin_read_DMA32_X_MODIFY()		bfin_read32(DMA32_X_MODIFY)
-#define bfin_write_DMA32_X_MODIFY(val) 		bfin_write32(DMA32_X_MODIFY, val)
-#define bfin_read_DMA32_Y_COUNT()		bfin_read32(DMA32_Y_COUNT)
-#define bfin_write_DMA32_Y_COUNT(val)		bfin_write32(DMA32_Y_COUNT, val)
-#define bfin_read_DMA32_Y_MODIFY()		bfin_read32(DMA32_Y_MODIFY)
-#define bfin_write_DMA32_Y_MODIFY(val) 		bfin_write32(DMA32_Y_MODIFY, val)
-#define bfin_read_DMA32_CURR_DESC_PTR() 	bfin_read32(DMA32_CURR_DESC_PTR)
-#define bfin_write_DMA32_CURR_DESC_PTR(val) 	bfin_write32(DMA32_CURR_DESC_PTR, val)
-#define bfin_read_DMA32_PREV_DESC_PTR() 	bfin_read32(DMA32_PREV_DESC_PTR)
-#define bfin_write_DMA32_PREV_DESC_PTR(val) 	bfin_write32(DMA32_PREV_DESC_PTR, val)
-#define bfin_read_DMA32_CURR_ADDR() 		bfin_read32(DMA32_CURR_ADDR)
-#define bfin_write_DMA32_CURR_ADDR(val) 	bfin_write32(DMA32_CURR_ADDR, val)
-#define bfin_read_DMA32_IRQ_STATUS()		bfin_read32(DMA32_IRQ_STATUS)
-#define bfin_write_DMA32_IRQ_STATUS(val)	bfin_write32(DMA32_IRQ_STATUS, val)
-#define bfin_read_DMA32_CURR_X_COUNT()		bfin_read32(DMA32_CURR_X_COUNT)
-#define bfin_write_DMA32_CURR_X_COUNT(val)	bfin_write32(DMA32_CURR_X_COUNT, val)
-#define bfin_read_DMA32_CURR_Y_COUNT()		bfin_read32(DMA32_CURR_Y_COUNT)
-#define bfin_write_DMA32_CURR_Y_COUNT(val)	bfin_write32(DMA32_CURR_Y_COUNT, val)
-#define bfin_read_DMA32_BWL_COUNT()		bfin_read32(DMA32_BWL_COUNT)
-#define bfin_write_DMA32_BWL_COUNT(val)		bfin_write32(DMA32_BWL_COUNT, val)
-#define bfin_read_DMA32_CURR_BWL_COUNT()	bfin_read32(DMA32_CURR_BWL_COUNT)
-#define bfin_write_DMA32_CURR_BWL_COUNT(val)	bfin_write32(DMA32_CURR_BWL_COUNT, val)
-#define bfin_read_DMA32_BWM_COUNT()		bfin_read32(DMA32_BWM_COUNT)
-#define bfin_write_DMA32_BWM_COUNT(val)		bfin_write32(DMA32_BWM_COUNT, val)
-#define bfin_read_DMA32_CURR_BWM_COUNT()	bfin_read32(DMA32_CURR_BWM_COUNT)
-#define bfin_write_DMA32_CURR_BWM_COUNT(val)	bfin_write32(DMA32_CURR_BWM_COUNT, val)
-
-/* DMA Channel 33 Registers */
-
-#define bfin_read_DMA33_NEXT_DESC_PTR() 	bfin_read32(DMA33_NEXT_DESC_PTR)
-#define bfin_write_DMA33_NEXT_DESC_PTR(val) 	bfin_write32(DMA33_NEXT_DESC_PTR, val)
-#define bfin_read_DMA33_START_ADDR() 		bfin_read32(DMA33_START_ADDR)
-#define bfin_write_DMA33_START_ADDR(val) 	bfin_write32(DMA33_START_ADDR, val)
-#define bfin_read_DMA33_CONFIG()		bfin_read32(DMA33_CONFIG)
-#define bfin_write_DMA33_CONFIG(val)		bfin_write32(DMA33_CONFIG, val)
-#define bfin_read_DMA33_X_COUNT()		bfin_read32(DMA33_X_COUNT)
-#define bfin_write_DMA33_X_COUNT(val)		bfin_write32(DMA33_X_COUNT, val)
-#define bfin_read_DMA33_X_MODIFY()		bfin_read32(DMA33_X_MODIFY)
-#define bfin_write_DMA33_X_MODIFY(val) 		bfin_write32(DMA33_X_MODIFY, val)
-#define bfin_read_DMA33_Y_COUNT()		bfin_read32(DMA33_Y_COUNT)
-#define bfin_write_DMA33_Y_COUNT(val)		bfin_write32(DMA33_Y_COUNT, val)
-#define bfin_read_DMA33_Y_MODIFY()		bfin_read32(DMA33_Y_MODIFY)
-#define bfin_write_DMA33_Y_MODIFY(val) 		bfin_write32(DMA33_Y_MODIFY, val)
-#define bfin_read_DMA33_CURR_DESC_PTR() 	bfin_read32(DMA33_CURR_DESC_PTR)
-#define bfin_write_DMA33_CURR_DESC_PTR(val) 	bfin_write32(DMA33_CURR_DESC_PTR, val)
-#define bfin_read_DMA33_PREV_DESC_PTR() 	bfin_read32(DMA33_PREV_DESC_PTR)
-#define bfin_write_DMA33_PREV_DESC_PTR(val) 	bfin_write32(DMA33_PREV_DESC_PTR, val)
-#define bfin_read_DMA33_CURR_ADDR() 		bfin_read32(DMA33_CURR_ADDR)
-#define bfin_write_DMA33_CURR_ADDR(val) 	bfin_write32(DMA33_CURR_ADDR, val)
-#define bfin_read_DMA33_IRQ_STATUS()		bfin_read32(DMA33_IRQ_STATUS)
-#define bfin_write_DMA33_IRQ_STATUS(val)	bfin_write32(DMA33_IRQ_STATUS, val)
-#define bfin_read_DMA33_CURR_X_COUNT()		bfin_read32(DMA33_CURR_X_COUNT)
-#define bfin_write_DMA33_CURR_X_COUNT(val)	bfin_write32(DMA33_CURR_X_COUNT, val)
-#define bfin_read_DMA33_CURR_Y_COUNT()		bfin_read32(DMA33_CURR_Y_COUNT)
-#define bfin_write_DMA33_CURR_Y_COUNT(val)	bfin_write32(DMA33_CURR_Y_COUNT, val)
-#define bfin_read_DMA33_BWL_COUNT()		bfin_read32(DMA33_BWL_COUNT)
-#define bfin_write_DMA33_BWL_COUNT(val)		bfin_write32(DMA33_BWL_COUNT, val)
-#define bfin_read_DMA33_CURR_BWL_COUNT()	bfin_read32(DMA33_CURR_BWL_COUNT)
-#define bfin_write_DMA33_CURR_BWL_COUNT(val)	bfin_write32(DMA33_CURR_BWL_COUNT, val)
-#define bfin_read_DMA33_BWM_COUNT()		bfin_read32(DMA33_BWM_COUNT)
-#define bfin_write_DMA33_BWM_COUNT(val)		bfin_write32(DMA33_BWM_COUNT, val)
-#define bfin_read_DMA33_CURR_BWM_COUNT()	bfin_read32(DMA33_CURR_BWM_COUNT)
-#define bfin_write_DMA33_CURR_BWM_COUNT(val)	bfin_write32(DMA33_CURR_BWM_COUNT, val)
-
-/* DMA Channel 34 Registers */
-
-#define bfin_read_DMA34_NEXT_DESC_PTR() 	bfin_read32(DMA34_NEXT_DESC_PTR)
-#define bfin_write_DMA34_NEXT_DESC_PTR(val) 	bfin_write32(DMA34_NEXT_DESC_PTR, val)
-#define bfin_read_DMA34_START_ADDR() 		bfin_read32(DMA34_START_ADDR)
-#define bfin_write_DMA34_START_ADDR(val) 	bfin_write32(DMA34_START_ADDR, val)
-#define bfin_read_DMA34_CONFIG()		bfin_read32(DMA34_CONFIG)
-#define bfin_write_DMA34_CONFIG(val)		bfin_write32(DMA34_CONFIG, val)
-#define bfin_read_DMA34_X_COUNT()		bfin_read32(DMA34_X_COUNT)
-#define bfin_write_DMA34_X_COUNT(val)		bfin_write32(DMA34_X_COUNT, val)
-#define bfin_read_DMA34_X_MODIFY()		bfin_read32(DMA34_X_MODIFY)
-#define bfin_write_DMA34_X_MODIFY(val) 		bfin_write32(DMA34_X_MODIFY, val)
-#define bfin_read_DMA34_Y_COUNT()		bfin_read32(DMA34_Y_COUNT)
-#define bfin_write_DMA34_Y_COUNT(val)		bfin_write32(DMA34_Y_COUNT, val)
-#define bfin_read_DMA34_Y_MODIFY()		bfin_read32(DMA34_Y_MODIFY)
-#define bfin_write_DMA34_Y_MODIFY(val) 		bfin_write32(DMA34_Y_MODIFY, val)
-#define bfin_read_DMA34_CURR_DESC_PTR() 	bfin_read32(DMA34_CURR_DESC_PTR)
-#define bfin_write_DMA34_CURR_DESC_PTR(val) 	bfin_write32(DMA34_CURR_DESC_PTR, val)
-#define bfin_read_DMA34_PREV_DESC_PTR() 	bfin_read32(DMA34_PREV_DESC_PTR)
-#define bfin_write_DMA34_PREV_DESC_PTR(val) 	bfin_write32(DMA34_PREV_DESC_PTR, val)
-#define bfin_read_DMA34_CURR_ADDR() 		bfin_read32(DMA34_CURR_ADDR)
-#define bfin_write_DMA34_CURR_ADDR(val) 	bfin_write32(DMA34_CURR_ADDR, val)
-#define bfin_read_DMA34_IRQ_STATUS()		bfin_read32(DMA34_IRQ_STATUS)
-#define bfin_write_DMA34_IRQ_STATUS(val)	bfin_write32(DMA34_IRQ_STATUS, val)
-#define bfin_read_DMA34_CURR_X_COUNT()		bfin_read32(DMA34_CURR_X_COUNT)
-#define bfin_write_DMA34_CURR_X_COUNT(val)	bfin_write32(DMA34_CURR_X_COUNT, val)
-#define bfin_read_DMA34_CURR_Y_COUNT()		bfin_read32(DMA34_CURR_Y_COUNT)
-#define bfin_write_DMA34_CURR_Y_COUNT(val)	bfin_write32(DMA34_CURR_Y_COUNT, val)
-#define bfin_read_DMA34_BWL_COUNT()		bfin_read32(DMA34_BWL_COUNT)
-#define bfin_write_DMA34_BWL_COUNT(val)		bfin_write32(DMA34_BWL_COUNT, val)
-#define bfin_read_DMA34_CURR_BWL_COUNT()	bfin_read32(DMA34_CURR_BWL_COUNT)
-#define bfin_write_DMA34_CURR_BWL_COUNT(val)	bfin_write32(DMA34_CURR_BWL_COUNT, val)
-#define bfin_read_DMA34_BWM_COUNT()		bfin_read32(DMA34_BWM_COUNT)
-#define bfin_write_DMA34_BWM_COUNT(val)		bfin_write32(DMA34_BWM_COUNT, val)
-#define bfin_read_DMA34_CURR_BWM_COUNT()	bfin_read32(DMA34_CURR_BWM_COUNT)
-#define bfin_write_DMA34_CURR_BWM_COUNT(val)	bfin_write32(DMA34_CURR_BWM_COUNT, val)
-
-/* DMA Channel 35 Registers */
-
-#define bfin_read_DMA35_NEXT_DESC_PTR() 	bfin_read32(DMA35_NEXT_DESC_PTR)
-#define bfin_write_DMA35_NEXT_DESC_PTR(val) 	bfin_write32(DMA35_NEXT_DESC_PTR, val)
-#define bfin_read_DMA35_START_ADDR() 		bfin_read32(DMA35_START_ADDR)
-#define bfin_write_DMA35_START_ADDR(val) 	bfin_write32(DMA35_START_ADDR, val)
-#define bfin_read_DMA35_CONFIG()		bfin_read32(DMA35_CONFIG)
-#define bfin_write_DMA35_CONFIG(val)		bfin_write32(DMA35_CONFIG, val)
-#define bfin_read_DMA35_X_COUNT()		bfin_read32(DMA35_X_COUNT)
-#define bfin_write_DMA35_X_COUNT(val)		bfin_write32(DMA35_X_COUNT, val)
-#define bfin_read_DMA35_X_MODIFY()		bfin_read32(DMA35_X_MODIFY)
-#define bfin_write_DMA35_X_MODIFY(val) 		bfin_write32(DMA35_X_MODIFY, val)
-#define bfin_read_DMA35_Y_COUNT()		bfin_read32(DMA35_Y_COUNT)
-#define bfin_write_DMA35_Y_COUNT(val)		bfin_write32(DMA35_Y_COUNT, val)
-#define bfin_read_DMA35_Y_MODIFY()		bfin_read32(DMA35_Y_MODIFY)
-#define bfin_write_DMA35_Y_MODIFY(val) 		bfin_write32(DMA35_Y_MODIFY, val)
-#define bfin_read_DMA35_CURR_DESC_PTR() 	bfin_read32(DMA35_CURR_DESC_PTR)
-#define bfin_write_DMA35_CURR_DESC_PTR(val) 	bfin_write32(DMA35_CURR_DESC_PTR, val)
-#define bfin_read_DMA35_PREV_DESC_PTR() 	bfin_read32(DMA35_PREV_DESC_PTR)
-#define bfin_write_DMA35_PREV_DESC_PTR(val) 	bfin_write32(DMA35_PREV_DESC_PTR, val)
-#define bfin_read_DMA35_CURR_ADDR() 		bfin_read32(DMA35_CURR_ADDR)
-#define bfin_write_DMA35_CURR_ADDR(val) 	bfin_write32(DMA35_CURR_ADDR, val)
-#define bfin_read_DMA35_IRQ_STATUS()		bfin_read32(DMA35_IRQ_STATUS)
-#define bfin_write_DMA35_IRQ_STATUS(val)	bfin_write32(DMA35_IRQ_STATUS, val)
-#define bfin_read_DMA35_CURR_X_COUNT()		bfin_read32(DMA35_CURR_X_COUNT)
-#define bfin_write_DMA35_CURR_X_COUNT(val)	bfin_write32(DMA35_CURR_X_COUNT, val)
-#define bfin_read_DMA35_CURR_Y_COUNT()		bfin_read32(DMA35_CURR_Y_COUNT)
-#define bfin_write_DMA35_CURR_Y_COUNT(val)	bfin_write32(DMA35_CURR_Y_COUNT, val)
-#define bfin_read_DMA35_BWL_COUNT()		bfin_read32(DMA35_BWL_COUNT)
-#define bfin_write_DMA35_BWL_COUNT(val)		bfin_write32(DMA35_BWL_COUNT, val)
-#define bfin_read_DMA35_CURR_BWL_COUNT()	bfin_read32(DMA35_CURR_BWL_COUNT)
-#define bfin_write_DMA35_CURR_BWL_COUNT(val)	bfin_write32(DMA35_CURR_BWL_COUNT, val)
-#define bfin_read_DMA35_BWM_COUNT()		bfin_read32(DMA35_BWM_COUNT)
-#define bfin_write_DMA35_BWM_COUNT(val)		bfin_write32(DMA35_BWM_COUNT, val)
-#define bfin_read_DMA35_CURR_BWM_COUNT()	bfin_read32(DMA35_CURR_BWM_COUNT)
-#define bfin_write_DMA35_CURR_BWM_COUNT(val)	bfin_write32(DMA35_CURR_BWM_COUNT, val)
-
-/* DMA Channel 36 Registers */
-
-#define bfin_read_DMA36_NEXT_DESC_PTR() 	bfin_read32(DMA36_NEXT_DESC_PTR)
-#define bfin_write_DMA36_NEXT_DESC_PTR(val) 	bfin_write32(DMA36_NEXT_DESC_PTR, val)
-#define bfin_read_DMA36_START_ADDR() 		bfin_read32(DMA36_START_ADDR)
-#define bfin_write_DMA36_START_ADDR(val) 	bfin_write32(DMA36_START_ADDR, val)
-#define bfin_read_DMA36_CONFIG()		bfin_read32(DMA36_CONFIG)
-#define bfin_write_DMA36_CONFIG(val)		bfin_write32(DMA36_CONFIG, val)
-#define bfin_read_DMA36_X_COUNT()		bfin_read32(DMA36_X_COUNT)
-#define bfin_write_DMA36_X_COUNT(val)		bfin_write32(DMA36_X_COUNT, val)
-#define bfin_read_DMA36_X_MODIFY()		bfin_read32(DMA36_X_MODIFY)
-#define bfin_write_DMA36_X_MODIFY(val) 		bfin_write32(DMA36_X_MODIFY, val)
-#define bfin_read_DMA36_Y_COUNT()		bfin_read32(DMA36_Y_COUNT)
-#define bfin_write_DMA36_Y_COUNT(val)		bfin_write32(DMA36_Y_COUNT, val)
-#define bfin_read_DMA36_Y_MODIFY()		bfin_read32(DMA36_Y_MODIFY)
-#define bfin_write_DMA36_Y_MODIFY(val) 		bfin_write32(DMA36_Y_MODIFY, val)
-#define bfin_read_DMA36_CURR_DESC_PTR() 	bfin_read32(DMA36_CURR_DESC_PTR)
-#define bfin_write_DMA36_CURR_DESC_PTR(val) 	bfin_write32(DMA36_CURR_DESC_PTR, val)
-#define bfin_read_DMA36_PREV_DESC_PTR() 	bfin_read32(DMA36_PREV_DESC_PTR)
-#define bfin_write_DMA36_PREV_DESC_PTR(val) 	bfin_write32(DMA36_PREV_DESC_PTR, val)
-#define bfin_read_DMA36_CURR_ADDR() 		bfin_read32(DMA36_CURR_ADDR)
-#define bfin_write_DMA36_CURR_ADDR(val) 	bfin_write32(DMA36_CURR_ADDR, val)
-#define bfin_read_DMA36_IRQ_STATUS()		bfin_read32(DMA36_IRQ_STATUS)
-#define bfin_write_DMA36_IRQ_STATUS(val)	bfin_write32(DMA36_IRQ_STATUS, val)
-#define bfin_read_DMA36_CURR_X_COUNT()		bfin_read32(DMA36_CURR_X_COUNT)
-#define bfin_write_DMA36_CURR_X_COUNT(val)	bfin_write32(DMA36_CURR_X_COUNT, val)
-#define bfin_read_DMA36_CURR_Y_COUNT()		bfin_read32(DMA36_CURR_Y_COUNT)
-#define bfin_write_DMA36_CURR_Y_COUNT(val)	bfin_write32(DMA36_CURR_Y_COUNT, val)
-#define bfin_read_DMA36_BWL_COUNT()		bfin_read32(DMA36_BWL_COUNT)
-#define bfin_write_DMA36_BWL_COUNT(val)		bfin_write32(DMA36_BWL_COUNT, val)
-#define bfin_read_DMA36_CURR_BWL_COUNT()	bfin_read32(DMA36_CURR_BWL_COUNT)
-#define bfin_write_DMA36_CURR_BWL_COUNT(val)	bfin_write32(DMA36_CURR_BWL_COUNT, val)
-#define bfin_read_DMA36_BWM_COUNT()		bfin_read32(DMA36_BWM_COUNT)
-#define bfin_write_DMA36_BWM_COUNT(val)		bfin_write32(DMA36_BWM_COUNT, val)
-#define bfin_read_DMA36_CURR_BWM_COUNT()	bfin_read32(DMA36_CURR_BWM_COUNT)
-#define bfin_write_DMA36_CURR_BWM_COUNT(val)	bfin_write32(DMA36_CURR_BWM_COUNT, val)
-
-/* DMA Channel 37 Registers */
-
-#define bfin_read_DMA37_NEXT_DESC_PTR() 	bfin_read32(DMA37_NEXT_DESC_PTR)
-#define bfin_write_DMA37_NEXT_DESC_PTR(val) 	bfin_write32(DMA37_NEXT_DESC_PTR, val)
-#define bfin_read_DMA37_START_ADDR() 		bfin_read32(DMA37_START_ADDR)
-#define bfin_write_DMA37_START_ADDR(val) 	bfin_write32(DMA37_START_ADDR, val)
-#define bfin_read_DMA37_CONFIG()		bfin_read32(DMA37_CONFIG)
-#define bfin_write_DMA37_CONFIG(val)		bfin_write32(DMA37_CONFIG, val)
-#define bfin_read_DMA37_X_COUNT()		bfin_read32(DMA37_X_COUNT)
-#define bfin_write_DMA37_X_COUNT(val)		bfin_write32(DMA37_X_COUNT, val)
-#define bfin_read_DMA37_X_MODIFY()		bfin_read32(DMA37_X_MODIFY)
-#define bfin_write_DMA37_X_MODIFY(val) 		bfin_write32(DMA37_X_MODIFY, val)
-#define bfin_read_DMA37_Y_COUNT()		bfin_read32(DMA37_Y_COUNT)
-#define bfin_write_DMA37_Y_COUNT(val)		bfin_write32(DMA37_Y_COUNT, val)
-#define bfin_read_DMA37_Y_MODIFY()		bfin_read32(DMA37_Y_MODIFY)
-#define bfin_write_DMA37_Y_MODIFY(val) 		bfin_write32(DMA37_Y_MODIFY, val)
-#define bfin_read_DMA37_CURR_DESC_PTR() 	bfin_read32(DMA37_CURR_DESC_PTR)
-#define bfin_write_DMA37_CURR_DESC_PTR(val) 	bfin_write32(DMA37_CURR_DESC_PTR, val)
-#define bfin_read_DMA37_PREV_DESC_PTR() 	bfin_read32(DMA37_PREV_DESC_PTR)
-#define bfin_write_DMA37_PREV_DESC_PTR(val) 	bfin_write32(DMA37_PREV_DESC_PTR, val)
-#define bfin_read_DMA37_CURR_ADDR() 		bfin_read32(DMA37_CURR_ADDR)
-#define bfin_write_DMA37_CURR_ADDR(val) 	bfin_write32(DMA37_CURR_ADDR, val)
-#define bfin_read_DMA37_IRQ_STATUS()		bfin_read32(DMA37_IRQ_STATUS)
-#define bfin_write_DMA37_IRQ_STATUS(val)	bfin_write32(DMA37_IRQ_STATUS, val)
-#define bfin_read_DMA37_CURR_X_COUNT()		bfin_read32(DMA37_CURR_X_COUNT)
-#define bfin_write_DMA37_CURR_X_COUNT(val)	bfin_write32(DMA37_CURR_X_COUNT, val)
-#define bfin_read_DMA37_CURR_Y_COUNT()		bfin_read32(DMA37_CURR_Y_COUNT)
-#define bfin_write_DMA37_CURR_Y_COUNT(val)	bfin_write32(DMA37_CURR_Y_COUNT, val)
-#define bfin_read_DMA37_BWL_COUNT()		bfin_read32(DMA37_BWL_COUNT)
-#define bfin_write_DMA37_BWL_COUNT(val)		bfin_write32(DMA37_BWL_COUNT, val)
-#define bfin_read_DMA37_CURR_BWL_COUNT()	bfin_read32(DMA37_CURR_BWL_COUNT)
-#define bfin_write_DMA37_CURR_BWL_COUNT(val)	bfin_write32(DMA37_CURR_BWL_COUNT, val)
-#define bfin_read_DMA37_BWM_COUNT()		bfin_read32(DMA37_BWM_COUNT)
-#define bfin_write_DMA37_BWM_COUNT(val)		bfin_write32(DMA37_BWM_COUNT, val)
-#define bfin_read_DMA37_CURR_BWM_COUNT()	bfin_read32(DMA37_CURR_BWM_COUNT)
-#define bfin_write_DMA37_CURR_BWM_COUNT(val)	bfin_write32(DMA37_CURR_BWM_COUNT, val)
-
-/* DMA Channel 38 Registers */
-
-#define bfin_read_DMA38_NEXT_DESC_PTR() 	bfin_read32(DMA38_NEXT_DESC_PTR)
-#define bfin_write_DMA38_NEXT_DESC_PTR(val) 	bfin_write32(DMA38_NEXT_DESC_PTR, val)
-#define bfin_read_DMA38_START_ADDR() 		bfin_read32(DMA38_START_ADDR)
-#define bfin_write_DMA38_START_ADDR(val) 	bfin_write32(DMA38_START_ADDR, val)
-#define bfin_read_DMA38_CONFIG()		bfin_read32(DMA38_CONFIG)
-#define bfin_write_DMA38_CONFIG(val)		bfin_write32(DMA38_CONFIG, val)
-#define bfin_read_DMA38_X_COUNT()		bfin_read32(DMA38_X_COUNT)
-#define bfin_write_DMA38_X_COUNT(val)		bfin_write32(DMA38_X_COUNT, val)
-#define bfin_read_DMA38_X_MODIFY()		bfin_read32(DMA38_X_MODIFY)
-#define bfin_write_DMA38_X_MODIFY(val) 		bfin_write32(DMA38_X_MODIFY, val)
-#define bfin_read_DMA38_Y_COUNT()		bfin_read32(DMA38_Y_COUNT)
-#define bfin_write_DMA38_Y_COUNT(val)		bfin_write32(DMA38_Y_COUNT, val)
-#define bfin_read_DMA38_Y_MODIFY()		bfin_read32(DMA38_Y_MODIFY)
-#define bfin_write_DMA38_Y_MODIFY(val) 		bfin_write32(DMA38_Y_MODIFY, val)
-#define bfin_read_DMA38_CURR_DESC_PTR() 	bfin_read32(DMA38_CURR_DESC_PTR)
-#define bfin_write_DMA38_CURR_DESC_PTR(val) 	bfin_write32(DMA38_CURR_DESC_PTR, val)
-#define bfin_read_DMA38_PREV_DESC_PTR() 	bfin_read32(DMA38_PREV_DESC_PTR)
-#define bfin_write_DMA38_PREV_DESC_PTR(val) 	bfin_write32(DMA38_PREV_DESC_PTR, val)
-#define bfin_read_DMA38_CURR_ADDR() 		bfin_read32(DMA38_CURR_ADDR)
-#define bfin_write_DMA38_CURR_ADDR(val) 	bfin_write32(DMA38_CURR_ADDR, val)
-#define bfin_read_DMA38_IRQ_STATUS()		bfin_read32(DMA38_IRQ_STATUS)
-#define bfin_write_DMA38_IRQ_STATUS(val)	bfin_write32(DMA38_IRQ_STATUS, val)
-#define bfin_read_DMA38_CURR_X_COUNT()		bfin_read32(DMA38_CURR_X_COUNT)
-#define bfin_write_DMA38_CURR_X_COUNT(val)	bfin_write32(DMA38_CURR_X_COUNT, val)
-#define bfin_read_DMA38_CURR_Y_COUNT()		bfin_read32(DMA38_CURR_Y_COUNT)
-#define bfin_write_DMA38_CURR_Y_COUNT(val)	bfin_write32(DMA38_CURR_Y_COUNT, val)
-#define bfin_read_DMA38_BWL_COUNT()		bfin_read32(DMA38_BWL_COUNT)
-#define bfin_write_DMA38_BWL_COUNT(val)		bfin_write32(DMA38_BWL_COUNT, val)
-#define bfin_read_DMA38_CURR_BWL_COUNT()	bfin_read32(DMA38_CURR_BWL_COUNT)
-#define bfin_write_DMA38_CURR_BWL_COUNT(val)	bfin_write32(DMA38_CURR_BWL_COUNT, val)
-#define bfin_read_DMA38_BWM_COUNT()		bfin_read32(DMA38_BWM_COUNT)
-#define bfin_write_DMA38_BWM_COUNT(val)		bfin_write32(DMA38_BWM_COUNT, val)
-#define bfin_read_DMA38_CURR_BWM_COUNT()	bfin_read32(DMA38_CURR_BWM_COUNT)
-#define bfin_write_DMA38_CURR_BWM_COUNT(val)	bfin_write32(DMA38_CURR_BWM_COUNT, val)
-
-/* DMA Channel 39 Registers */
-
-#define bfin_read_DMA39_NEXT_DESC_PTR() 	bfin_read32(DMA39_NEXT_DESC_PTR)
-#define bfin_write_DMA39_NEXT_DESC_PTR(val) 	bfin_write32(DMA39_NEXT_DESC_PTR, val)
-#define bfin_read_DMA39_START_ADDR() 		bfin_read32(DMA39_START_ADDR)
-#define bfin_write_DMA39_START_ADDR(val) 	bfin_write32(DMA39_START_ADDR, val)
-#define bfin_read_DMA39_CONFIG()		bfin_read32(DMA39_CONFIG)
-#define bfin_write_DMA39_CONFIG(val)		bfin_write32(DMA39_CONFIG, val)
-#define bfin_read_DMA39_X_COUNT()		bfin_read32(DMA39_X_COUNT)
-#define bfin_write_DMA39_X_COUNT(val)		bfin_write32(DMA39_X_COUNT, val)
-#define bfin_read_DMA39_X_MODIFY()		bfin_read32(DMA39_X_MODIFY)
-#define bfin_write_DMA39_X_MODIFY(val) 		bfin_write32(DMA39_X_MODIFY, val)
-#define bfin_read_DMA39_Y_COUNT()		bfin_read32(DMA39_Y_COUNT)
-#define bfin_write_DMA39_Y_COUNT(val)		bfin_write32(DMA39_Y_COUNT, val)
-#define bfin_read_DMA39_Y_MODIFY()		bfin_read32(DMA39_Y_MODIFY)
-#define bfin_write_DMA39_Y_MODIFY(val) 		bfin_write32(DMA39_Y_MODIFY, val)
-#define bfin_read_DMA39_CURR_DESC_PTR() 	bfin_read32(DMA39_CURR_DESC_PTR)
-#define bfin_write_DMA39_CURR_DESC_PTR(val) 	bfin_write32(DMA39_CURR_DESC_PTR, val)
-#define bfin_read_DMA39_PREV_DESC_PTR() 	bfin_read32(DMA39_PREV_DESC_PTR)
-#define bfin_write_DMA39_PREV_DESC_PTR(val) 	bfin_write32(DMA39_PREV_DESC_PTR, val)
-#define bfin_read_DMA39_CURR_ADDR() 		bfin_read32(DMA39_CURR_ADDR)
-#define bfin_write_DMA39_CURR_ADDR(val) 	bfin_write32(DMA39_CURR_ADDR, val)
-#define bfin_read_DMA39_IRQ_STATUS()		bfin_read32(DMA39_IRQ_STATUS)
-#define bfin_write_DMA39_IRQ_STATUS(val)	bfin_write32(DMA39_IRQ_STATUS, val)
-#define bfin_read_DMA39_CURR_X_COUNT()		bfin_read32(DMA39_CURR_X_COUNT)
-#define bfin_write_DMA39_CURR_X_COUNT(val)	bfin_write32(DMA39_CURR_X_COUNT, val)
-#define bfin_read_DMA39_CURR_Y_COUNT()		bfin_read32(DMA39_CURR_Y_COUNT)
-#define bfin_write_DMA39_CURR_Y_COUNT(val)	bfin_write32(DMA39_CURR_Y_COUNT, val)
-#define bfin_read_DMA39_BWL_COUNT()		bfin_read32(DMA39_BWL_COUNT)
-#define bfin_write_DMA39_BWL_COUNT(val)		bfin_write32(DMA39_BWL_COUNT, val)
-#define bfin_read_DMA39_CURR_BWL_COUNT()	bfin_read32(DMA39_CURR_BWL_COUNT)
-#define bfin_write_DMA39_CURR_BWL_COUNT(val)	bfin_write32(DMA39_CURR_BWL_COUNT, val)
-#define bfin_read_DMA39_BWM_COUNT()		bfin_read32(DMA39_BWM_COUNT)
-#define bfin_write_DMA39_BWM_COUNT(val)		bfin_write32(DMA39_BWM_COUNT, val)
-#define bfin_read_DMA39_CURR_BWM_COUNT()	bfin_read32(DMA39_CURR_BWM_COUNT)
-#define bfin_write_DMA39_CURR_BWM_COUNT(val)	bfin_write32(DMA39_CURR_BWM_COUNT, val)
-
-/* DMA Channel 40 Registers */
-
-#define bfin_read_DMA40_NEXT_DESC_PTR() 	bfin_read32(DMA40_NEXT_DESC_PTR)
-#define bfin_write_DMA40_NEXT_DESC_PTR(val) 	bfin_write32(DMA40_NEXT_DESC_PTR, val)
-#define bfin_read_DMA40_START_ADDR() 		bfin_read32(DMA40_START_ADDR)
-#define bfin_write_DMA40_START_ADDR(val) 	bfin_write32(DMA40_START_ADDR, val)
-#define bfin_read_DMA40_CONFIG()		bfin_read32(DMA40_CONFIG)
-#define bfin_write_DMA40_CONFIG(val)		bfin_write32(DMA40_CONFIG, val)
-#define bfin_read_DMA40_X_COUNT()		bfin_read32(DMA40_X_COUNT)
-#define bfin_write_DMA40_X_COUNT(val)		bfin_write32(DMA40_X_COUNT, val)
-#define bfin_read_DMA40_X_MODIFY()		bfin_read32(DMA40_X_MODIFY)
-#define bfin_write_DMA40_X_MODIFY(val) 		bfin_write32(DMA40_X_MODIFY, val)
-#define bfin_read_DMA40_Y_COUNT()		bfin_read32(DMA40_Y_COUNT)
-#define bfin_write_DMA40_Y_COUNT(val)		bfin_write32(DMA40_Y_COUNT, val)
-#define bfin_read_DMA40_Y_MODIFY()		bfin_read32(DMA40_Y_MODIFY)
-#define bfin_write_DMA40_Y_MODIFY(val) 		bfin_write32(DMA40_Y_MODIFY, val)
-#define bfin_read_DMA40_CURR_DESC_PTR() 	bfin_read32(DMA40_CURR_DESC_PTR)
-#define bfin_write_DMA40_CURR_DESC_PTR(val) 	bfin_write32(DMA40_CURR_DESC_PTR, val)
-#define bfin_read_DMA40_PREV_DESC_PTR() 	bfin_read32(DMA40_PREV_DESC_PTR)
-#define bfin_write_DMA40_PREV_DESC_PTR(val) 	bfin_write32(DMA40_PREV_DESC_PTR, val)
-#define bfin_read_DMA40_CURR_ADDR() 		bfin_read32(DMA40_CURR_ADDR)
-#define bfin_write_DMA40_CURR_ADDR(val) 	bfin_write32(DMA40_CURR_ADDR, val)
-#define bfin_read_DMA40_IRQ_STATUS()		bfin_read32(DMA40_IRQ_STATUS)
-#define bfin_write_DMA40_IRQ_STATUS(val)	bfin_write32(DMA40_IRQ_STATUS, val)
-#define bfin_read_DMA40_CURR_X_COUNT()		bfin_read32(DMA40_CURR_X_COUNT)
-#define bfin_write_DMA40_CURR_X_COUNT(val)	bfin_write32(DMA40_CURR_X_COUNT, val)
-#define bfin_read_DMA40_CURR_Y_COUNT()		bfin_read32(DMA40_CURR_Y_COUNT)
-#define bfin_write_DMA40_CURR_Y_COUNT(val)	bfin_write32(DMA40_CURR_Y_COUNT, val)
-#define bfin_read_DMA40_BWL_COUNT()		bfin_read32(DMA40_BWL_COUNT)
-#define bfin_write_DMA40_BWL_COUNT(val)		bfin_write32(DMA40_BWL_COUNT, val)
-#define bfin_read_DMA40_CURR_BWL_COUNT()	bfin_read32(DMA40_CURR_BWL_COUNT)
-#define bfin_write_DMA40_CURR_BWL_COUNT(val)	bfin_write32(DMA40_CURR_BWL_COUNT, val)
-#define bfin_read_DMA40_BWM_COUNT()		bfin_read32(DMA40_BWM_COUNT)
-#define bfin_write_DMA40_BWM_COUNT(val)		bfin_write32(DMA40_BWM_COUNT, val)
-#define bfin_read_DMA40_CURR_BWM_COUNT()	bfin_read32(DMA40_CURR_BWM_COUNT)
-#define bfin_write_DMA40_CURR_BWM_COUNT(val)	bfin_write32(DMA40_CURR_BWM_COUNT, val)
-
-/* DMA Channel 41 Registers */
-
-#define bfin_read_DMA41_NEXT_DESC_PTR() 	bfin_read32(DMA41_NEXT_DESC_PTR)
-#define bfin_write_DMA41_NEXT_DESC_PTR(val) 	bfin_write32(DMA41_NEXT_DESC_PTR, val)
-#define bfin_read_DMA41_START_ADDR() 		bfin_read32(DMA41_START_ADDR)
-#define bfin_write_DMA41_START_ADDR(val) 	bfin_write32(DMA41_START_ADDR, val)
-#define bfin_read_DMA41_CONFIG()		bfin_read32(DMA41_CONFIG)
-#define bfin_write_DMA41_CONFIG(val)		bfin_write32(DMA41_CONFIG, val)
-#define bfin_read_DMA41_X_COUNT()		bfin_read32(DMA41_X_COUNT)
-#define bfin_write_DMA41_X_COUNT(val)		bfin_write32(DMA41_X_COUNT, val)
-#define bfin_read_DMA41_X_MODIFY()		bfin_read32(DMA41_X_MODIFY)
-#define bfin_write_DMA41_X_MODIFY(val) 		bfin_write32(DMA41_X_MODIFY, val)
-#define bfin_read_DMA41_Y_COUNT()		bfin_read32(DMA41_Y_COUNT)
-#define bfin_write_DMA41_Y_COUNT(val)		bfin_write32(DMA41_Y_COUNT, val)
-#define bfin_read_DMA41_Y_MODIFY()		bfin_read32(DMA41_Y_MODIFY)
-#define bfin_write_DMA41_Y_MODIFY(val) 		bfin_write32(DMA41_Y_MODIFY, val)
-#define bfin_read_DMA41_CURR_DESC_PTR() 	bfin_read32(DMA41_CURR_DESC_PTR)
-#define bfin_write_DMA41_CURR_DESC_PTR(val) 	bfin_write32(DMA41_CURR_DESC_PTR, val)
-#define bfin_read_DMA41_PREV_DESC_PTR() 	bfin_read32(DMA41_PREV_DESC_PTR)
-#define bfin_write_DMA41_PREV_DESC_PTR(val) 	bfin_write32(DMA41_PREV_DESC_PTR, val)
-#define bfin_read_DMA41_CURR_ADDR() 		bfin_read32(DMA41_CURR_ADDR)
-#define bfin_write_DMA41_CURR_ADDR(val) 	bfin_write32(DMA41_CURR_ADDR, val)
-#define bfin_read_DMA41_IRQ_STATUS()		bfin_read32(DMA41_IRQ_STATUS)
-#define bfin_write_DMA41_IRQ_STATUS(val)	bfin_write32(DMA41_IRQ_STATUS, val)
-#define bfin_read_DMA41_CURR_X_COUNT()		bfin_read32(DMA41_CURR_X_COUNT)
-#define bfin_write_DMA41_CURR_X_COUNT(val)	bfin_write32(DMA41_CURR_X_COUNT, val)
-#define bfin_read_DMA41_CURR_Y_COUNT()		bfin_read32(DMA41_CURR_Y_COUNT)
-#define bfin_write_DMA41_CURR_Y_COUNT(val)	bfin_write32(DMA41_CURR_Y_COUNT, val)
-#define bfin_read_DMA41_BWL_COUNT()		bfin_read32(DMA41_BWL_COUNT)
-#define bfin_write_DMA41_BWL_COUNT(val)		bfin_write32(DMA41_BWL_COUNT, val)
-#define bfin_read_DMA41_CURR_BWL_COUNT()	bfin_read32(DMA41_CURR_BWL_COUNT)
-#define bfin_write_DMA41_CURR_BWL_COUNT(val)	bfin_write32(DMA41_CURR_BWL_COUNT, val)
-#define bfin_read_DMA41_BWM_COUNT()		bfin_read32(DMA41_BWM_COUNT)
-#define bfin_write_DMA41_BWM_COUNT(val)		bfin_write32(DMA41_BWM_COUNT, val)
-#define bfin_read_DMA41_CURR_BWM_COUNT()	bfin_read32(DMA41_CURR_BWM_COUNT)
-#define bfin_write_DMA41_CURR_BWM_COUNT(val)	bfin_write32(DMA41_CURR_BWM_COUNT, val)
-
-/* DMA Channel 42 Registers */
-
-#define bfin_read_DMA42_NEXT_DESC_PTR() 	bfin_read32(DMA42_NEXT_DESC_PTR)
-#define bfin_write_DMA42_NEXT_DESC_PTR(val) 	bfin_write32(DMA42_NEXT_DESC_PTR, val)
-#define bfin_read_DMA42_START_ADDR() 		bfin_read32(DMA42_START_ADDR)
-#define bfin_write_DMA42_START_ADDR(val) 	bfin_write32(DMA42_START_ADDR, val)
-#define bfin_read_DMA42_CONFIG()		bfin_read32(DMA42_CONFIG)
-#define bfin_write_DMA42_CONFIG(val)		bfin_write32(DMA42_CONFIG, val)
-#define bfin_read_DMA42_X_COUNT()		bfin_read32(DMA42_X_COUNT)
-#define bfin_write_DMA42_X_COUNT(val)		bfin_write32(DMA42_X_COUNT, val)
-#define bfin_read_DMA42_X_MODIFY()		bfin_read32(DMA42_X_MODIFY)
-#define bfin_write_DMA42_X_MODIFY(val) 		bfin_write32(DMA42_X_MODIFY, val)
-#define bfin_read_DMA42_Y_COUNT()		bfin_read32(DMA42_Y_COUNT)
-#define bfin_write_DMA42_Y_COUNT(val)		bfin_write32(DMA42_Y_COUNT, val)
-#define bfin_read_DMA42_Y_MODIFY()		bfin_read32(DMA42_Y_MODIFY)
-#define bfin_write_DMA42_Y_MODIFY(val) 		bfin_write32(DMA42_Y_MODIFY, val)
-#define bfin_read_DMA42_CURR_DESC_PTR() 	bfin_read32(DMA42_CURR_DESC_PTR)
-#define bfin_write_DMA42_CURR_DESC_PTR(val) 	bfin_write32(DMA42_CURR_DESC_PTR, val)
-#define bfin_read_DMA42_PREV_DESC_PTR() 	bfin_read32(DMA42_PREV_DESC_PTR)
-#define bfin_write_DMA42_PREV_DESC_PTR(val) 	bfin_write32(DMA42_PREV_DESC_PTR, val)
-#define bfin_read_DMA42_CURR_ADDR() 		bfin_read32(DMA42_CURR_ADDR)
-#define bfin_write_DMA42_CURR_ADDR(val) 	bfin_write32(DMA42_CURR_ADDR, val)
-#define bfin_read_DMA42_IRQ_STATUS()		bfin_read32(DMA42_IRQ_STATUS)
-#define bfin_write_DMA42_IRQ_STATUS(val)	bfin_write32(DMA42_IRQ_STATUS, val)
-#define bfin_read_DMA42_CURR_X_COUNT()		bfin_read32(DMA42_CURR_X_COUNT)
-#define bfin_write_DMA42_CURR_X_COUNT(val)	bfin_write32(DMA42_CURR_X_COUNT, val)
-#define bfin_read_DMA42_CURR_Y_COUNT()		bfin_read32(DMA42_CURR_Y_COUNT)
-#define bfin_write_DMA42_CURR_Y_COUNT(val)	bfin_write32(DMA42_CURR_Y_COUNT, val)
-#define bfin_read_DMA42_BWL_COUNT()		bfin_read32(DMA42_BWL_COUNT)
-#define bfin_write_DMA42_BWL_COUNT(val)		bfin_write32(DMA42_BWL_COUNT, val)
-#define bfin_read_DMA42_CURR_BWL_COUNT()	bfin_read32(DMA42_CURR_BWL_COUNT)
-#define bfin_write_DMA42_CURR_BWL_COUNT(val)	bfin_write32(DMA42_CURR_BWL_COUNT, val)
-#define bfin_read_DMA42_BWM_COUNT()		bfin_read32(DMA42_BWM_COUNT)
-#define bfin_write_DMA42_BWM_COUNT(val)		bfin_write32(DMA42_BWM_COUNT, val)
-#define bfin_read_DMA42_CURR_BWM_COUNT()	bfin_read32(DMA42_CURR_BWM_COUNT)
-#define bfin_write_DMA42_CURR_BWM_COUNT(val)	bfin_write32(DMA42_CURR_BWM_COUNT, val)
-
-/* DMA Channel 43 Registers */
-
-#define bfin_read_DMA43_NEXT_DESC_PTR() 	bfin_read32(DMA43_NEXT_DESC_PTR)
-#define bfin_write_DMA43_NEXT_DESC_PTR(val) 	bfin_write32(DMA43_NEXT_DESC_PTR, val)
-#define bfin_read_DMA43_START_ADDR() 		bfin_read32(DMA43_START_ADDR)
-#define bfin_write_DMA43_START_ADDR(val) 	bfin_write32(DMA43_START_ADDR, val)
-#define bfin_read_DMA43_CONFIG()		bfin_read32(DMA43_CONFIG)
-#define bfin_write_DMA43_CONFIG(val)		bfin_write32(DMA43_CONFIG, val)
-#define bfin_read_DMA43_X_COUNT()		bfin_read32(DMA43_X_COUNT)
-#define bfin_write_DMA43_X_COUNT(val)		bfin_write32(DMA43_X_COUNT, val)
-#define bfin_read_DMA43_X_MODIFY()		bfin_read32(DMA43_X_MODIFY)
-#define bfin_write_DMA43_X_MODIFY(val) 		bfin_write32(DMA43_X_MODIFY, val)
-#define bfin_read_DMA43_Y_COUNT()		bfin_read32(DMA43_Y_COUNT)
-#define bfin_write_DMA43_Y_COUNT(val)		bfin_write32(DMA43_Y_COUNT, val)
-#define bfin_read_DMA43_Y_MODIFY()		bfin_read32(DMA43_Y_MODIFY)
-#define bfin_write_DMA43_Y_MODIFY(val) 		bfin_write32(DMA43_Y_MODIFY, val)
-#define bfin_read_DMA43_CURR_DESC_PTR() 	bfin_read32(DMA43_CURR_DESC_PTR)
-#define bfin_write_DMA43_CURR_DESC_PTR(val) 	bfin_write32(DMA43_CURR_DESC_PTR, val)
-#define bfin_read_DMA43_PREV_DESC_PTR() 	bfin_read32(DMA43_PREV_DESC_PTR)
-#define bfin_write_DMA43_PREV_DESC_PTR(val) 	bfin_write32(DMA43_PREV_DESC_PTR, val)
-#define bfin_read_DMA43_CURR_ADDR() 		bfin_read32(DMA43_CURR_ADDR)
-#define bfin_write_DMA43_CURR_ADDR(val) 	bfin_write32(DMA43_CURR_ADDR, val)
-#define bfin_read_DMA43_IRQ_STATUS()		bfin_read32(DMA43_IRQ_STATUS)
-#define bfin_write_DMA43_IRQ_STATUS(val)	bfin_write32(DMA43_IRQ_STATUS, val)
-#define bfin_read_DMA43_CURR_X_COUNT()		bfin_read32(DMA43_CURR_X_COUNT)
-#define bfin_write_DMA43_CURR_X_COUNT(val)	bfin_write32(DMA43_CURR_X_COUNT, val)
-#define bfin_read_DMA43_CURR_Y_COUNT()		bfin_read32(DMA43_CURR_Y_COUNT)
-#define bfin_write_DMA43_CURR_Y_COUNT(val)	bfin_write32(DMA43_CURR_Y_COUNT, val)
-#define bfin_read_DMA43_BWL_COUNT()		bfin_read32(DMA43_BWL_COUNT)
-#define bfin_write_DMA43_BWL_COUNT(val)		bfin_write32(DMA43_BWL_COUNT, val)
-#define bfin_read_DMA43_CURR_BWL_COUNT()	bfin_read32(DMA43_CURR_BWL_COUNT)
-#define bfin_write_DMA43_CURR_BWL_COUNT(val)	bfin_write32(DMA43_CURR_BWL_COUNT, val)
-#define bfin_read_DMA43_BWM_COUNT()		bfin_read32(DMA43_BWM_COUNT)
-#define bfin_write_DMA43_BWM_COUNT(val)		bfin_write32(DMA43_BWM_COUNT, val)
-#define bfin_read_DMA43_CURR_BWM_COUNT()	bfin_read32(DMA43_CURR_BWM_COUNT)
-#define bfin_write_DMA43_CURR_BWM_COUNT(val)	bfin_write32(DMA43_CURR_BWM_COUNT, val)
-
-/* DMA Channel 44 Registers */
-
-#define bfin_read_DMA44_NEXT_DESC_PTR() 	bfin_read32(DMA44_NEXT_DESC_PTR)
-#define bfin_write_DMA44_NEXT_DESC_PTR(val) 	bfin_write32(DMA44_NEXT_DESC_PTR, val)
-#define bfin_read_DMA44_START_ADDR() 		bfin_read32(DMA44_START_ADDR)
-#define bfin_write_DMA44_START_ADDR(val) 	bfin_write32(DMA44_START_ADDR, val)
-#define bfin_read_DMA44_CONFIG()		bfin_read32(DMA44_CONFIG)
-#define bfin_write_DMA44_CONFIG(val)		bfin_write32(DMA44_CONFIG, val)
-#define bfin_read_DMA44_X_COUNT()		bfin_read32(DMA44_X_COUNT)
-#define bfin_write_DMA44_X_COUNT(val)		bfin_write32(DMA44_X_COUNT, val)
-#define bfin_read_DMA44_X_MODIFY()		bfin_read32(DMA44_X_MODIFY)
-#define bfin_write_DMA44_X_MODIFY(val) 		bfin_write32(DMA44_X_MODIFY, val)
-#define bfin_read_DMA44_Y_COUNT()		bfin_read32(DMA44_Y_COUNT)
-#define bfin_write_DMA44_Y_COUNT(val)		bfin_write32(DMA44_Y_COUNT, val)
-#define bfin_read_DMA44_Y_MODIFY()		bfin_read32(DMA44_Y_MODIFY)
-#define bfin_write_DMA44_Y_MODIFY(val) 		bfin_write32(DMA44_Y_MODIFY, val)
-#define bfin_read_DMA44_CURR_DESC_PTR() 	bfin_read32(DMA44_CURR_DESC_PTR)
-#define bfin_write_DMA44_CURR_DESC_PTR(val) 	bfin_write32(DMA44_CURR_DESC_PTR, val)
-#define bfin_read_DMA44_PREV_DESC_PTR() 	bfin_read32(DMA44_PREV_DESC_PTR)
-#define bfin_write_DMA44_PREV_DESC_PTR(val) 	bfin_write32(DMA44_PREV_DESC_PTR, val)
-#define bfin_read_DMA44_CURR_ADDR() 		bfin_read32(DMA44_CURR_ADDR)
-#define bfin_write_DMA44_CURR_ADDR(val) 	bfin_write32(DMA44_CURR_ADDR, val)
-#define bfin_read_DMA44_IRQ_STATUS()		bfin_read32(DMA44_IRQ_STATUS)
-#define bfin_write_DMA44_IRQ_STATUS(val)	bfin_write32(DMA44_IRQ_STATUS, val)
-#define bfin_read_DMA44_CURR_X_COUNT()		bfin_read32(DMA44_CURR_X_COUNT)
-#define bfin_write_DMA44_CURR_X_COUNT(val)	bfin_write32(DMA44_CURR_X_COUNT, val)
-#define bfin_read_DMA44_CURR_Y_COUNT()		bfin_read32(DMA44_CURR_Y_COUNT)
-#define bfin_write_DMA44_CURR_Y_COUNT(val)	bfin_write32(DMA44_CURR_Y_COUNT, val)
-#define bfin_read_DMA44_BWL_COUNT()		bfin_read32(DMA44_BWL_COUNT)
-#define bfin_write_DMA44_BWL_COUNT(val)		bfin_write32(DMA44_BWL_COUNT, val)
-#define bfin_read_DMA44_CURR_BWL_COUNT()	bfin_read32(DMA44_CURR_BWL_COUNT)
-#define bfin_write_DMA44_CURR_BWL_COUNT(val)	bfin_write32(DMA44_CURR_BWL_COUNT, val)
-#define bfin_read_DMA44_BWM_COUNT()		bfin_read32(DMA44_BWM_COUNT)
-#define bfin_write_DMA44_BWM_COUNT(val)		bfin_write32(DMA44_BWM_COUNT, val)
-#define bfin_read_DMA44_CURR_BWM_COUNT()	bfin_read32(DMA44_CURR_BWM_COUNT)
-#define bfin_write_DMA44_CURR_BWM_COUNT(val)	bfin_write32(DMA44_CURR_BWM_COUNT, val)
-
-/* DMA Channel 45 Registers */
-
-#define bfin_read_DMA45_NEXT_DESC_PTR() 	bfin_read32(DMA45_NEXT_DESC_PTR)
-#define bfin_write_DMA45_NEXT_DESC_PTR(val) 	bfin_write32(DMA45_NEXT_DESC_PTR, val)
-#define bfin_read_DMA45_START_ADDR() 		bfin_read32(DMA45_START_ADDR)
-#define bfin_write_DMA45_START_ADDR(val) 	bfin_write32(DMA45_START_ADDR, val)
-#define bfin_read_DMA45_CONFIG()		bfin_read32(DMA45_CONFIG)
-#define bfin_write_DMA45_CONFIG(val)		bfin_write32(DMA45_CONFIG, val)
-#define bfin_read_DMA45_X_COUNT()		bfin_read32(DMA45_X_COUNT)
-#define bfin_write_DMA45_X_COUNT(val)		bfin_write32(DMA45_X_COUNT, val)
-#define bfin_read_DMA45_X_MODIFY()		bfin_read32(DMA45_X_MODIFY)
-#define bfin_write_DMA45_X_MODIFY(val) 		bfin_write32(DMA45_X_MODIFY, val)
-#define bfin_read_DMA45_Y_COUNT()		bfin_read32(DMA45_Y_COUNT)
-#define bfin_write_DMA45_Y_COUNT(val)		bfin_write32(DMA45_Y_COUNT, val)
-#define bfin_read_DMA45_Y_MODIFY()		bfin_read32(DMA45_Y_MODIFY)
-#define bfin_write_DMA45_Y_MODIFY(val) 		bfin_write32(DMA45_Y_MODIFY, val)
-#define bfin_read_DMA45_CURR_DESC_PTR() 	bfin_read32(DMA45_CURR_DESC_PTR)
-#define bfin_write_DMA45_CURR_DESC_PTR(val) 	bfin_write32(DMA45_CURR_DESC_PTR, val)
-#define bfin_read_DMA45_PREV_DESC_PTR() 	bfin_read32(DMA45_PREV_DESC_PTR)
-#define bfin_write_DMA45_PREV_DESC_PTR(val) 	bfin_write32(DMA45_PREV_DESC_PTR, val)
-#define bfin_read_DMA45_CURR_ADDR() 		bfin_read32(DMA45_CURR_ADDR)
-#define bfin_write_DMA45_CURR_ADDR(val) 	bfin_write32(DMA45_CURR_ADDR, val)
-#define bfin_read_DMA45_IRQ_STATUS()		bfin_read32(DMA45_IRQ_STATUS)
-#define bfin_write_DMA45_IRQ_STATUS(val)	bfin_write32(DMA45_IRQ_STATUS, val)
-#define bfin_read_DMA45_CURR_X_COUNT()		bfin_read32(DMA45_CURR_X_COUNT)
-#define bfin_write_DMA45_CURR_X_COUNT(val)	bfin_write32(DMA45_CURR_X_COUNT, val)
-#define bfin_read_DMA45_CURR_Y_COUNT()		bfin_read32(DMA45_CURR_Y_COUNT)
-#define bfin_write_DMA45_CURR_Y_COUNT(val)	bfin_write32(DMA45_CURR_Y_COUNT, val)
-#define bfin_read_DMA45_BWL_COUNT()		bfin_read32(DMA45_BWL_COUNT)
-#define bfin_write_DMA45_BWL_COUNT(val)		bfin_write32(DMA45_BWL_COUNT, val)
-#define bfin_read_DMA45_CURR_BWL_COUNT()	bfin_read32(DMA45_CURR_BWL_COUNT)
-#define bfin_write_DMA45_CURR_BWL_COUNT(val)	bfin_write32(DMA45_CURR_BWL_COUNT, val)
-#define bfin_read_DMA45_BWM_COUNT()		bfin_read32(DMA45_BWM_COUNT)
-#define bfin_write_DMA45_BWM_COUNT(val)		bfin_write32(DMA45_BWM_COUNT, val)
-#define bfin_read_DMA45_CURR_BWM_COUNT()	bfin_read32(DMA45_CURR_BWM_COUNT)
-#define bfin_write_DMA45_CURR_BWM_COUNT(val)	bfin_write32(DMA45_CURR_BWM_COUNT, val)
-
-/* DMA Channel 46 Registers */
-
-#define bfin_read_DMA46_NEXT_DESC_PTR() 	bfin_read32(DMA46_NEXT_DESC_PTR)
-#define bfin_write_DMA46_NEXT_DESC_PTR(val) 	bfin_write32(DMA46_NEXT_DESC_PTR, val)
-#define bfin_read_DMA46_START_ADDR() 		bfin_read32(DMA46_START_ADDR)
-#define bfin_write_DMA46_START_ADDR(val) 	bfin_write32(DMA46_START_ADDR, val)
-#define bfin_read_DMA46_CONFIG()		bfin_read32(DMA46_CONFIG)
-#define bfin_write_DMA46_CONFIG(val)		bfin_write32(DMA46_CONFIG, val)
-#define bfin_read_DMA46_X_COUNT()		bfin_read32(DMA46_X_COUNT)
-#define bfin_write_DMA46_X_COUNT(val)		bfin_write32(DMA46_X_COUNT, val)
-#define bfin_read_DMA46_X_MODIFY()		bfin_read32(DMA46_X_MODIFY)
-#define bfin_write_DMA46_X_MODIFY(val) 		bfin_write32(DMA46_X_MODIFY, val)
-#define bfin_read_DMA46_Y_COUNT()		bfin_read32(DMA46_Y_COUNT)
-#define bfin_write_DMA46_Y_COUNT(val)		bfin_write32(DMA46_Y_COUNT, val)
-#define bfin_read_DMA46_Y_MODIFY()		bfin_read32(DMA46_Y_MODIFY)
-#define bfin_write_DMA46_Y_MODIFY(val) 		bfin_write32(DMA46_Y_MODIFY, val)
-#define bfin_read_DMA46_CURR_DESC_PTR() 	bfin_read32(DMA46_CURR_DESC_PTR)
-#define bfin_write_DMA46_CURR_DESC_PTR(val) 	bfin_write32(DMA46_CURR_DESC_PTR, val)
-#define bfin_read_DMA46_PREV_DESC_PTR() 	bfin_read32(DMA46_PREV_DESC_PTR)
-#define bfin_write_DMA46_PREV_DESC_PTR(val) 	bfin_write32(DMA46_PREV_DESC_PTR, val)
-#define bfin_read_DMA46_CURR_ADDR() 		bfin_read32(DMA46_CURR_ADDR)
-#define bfin_write_DMA46_CURR_ADDR(val) 	bfin_write32(DMA46_CURR_ADDR, val)
-#define bfin_read_DMA46_IRQ_STATUS()		bfin_read32(DMA46_IRQ_STATUS)
-#define bfin_write_DMA46_IRQ_STATUS(val)	bfin_write32(DMA46_IRQ_STATUS, val)
-#define bfin_read_DMA46_CURR_X_COUNT()		bfin_read32(DMA46_CURR_X_COUNT)
-#define bfin_write_DMA46_CURR_X_COUNT(val)	bfin_write32(DMA46_CURR_X_COUNT, val)
-#define bfin_read_DMA46_CURR_Y_COUNT()		bfin_read32(DMA46_CURR_Y_COUNT)
-#define bfin_write_DMA46_CURR_Y_COUNT(val)	bfin_write32(DMA46_CURR_Y_COUNT, val)
-#define bfin_read_DMA46_BWL_COUNT()		bfin_read32(DMA46_BWL_COUNT)
-#define bfin_write_DMA46_BWL_COUNT(val)		bfin_write32(DMA46_BWL_COUNT, val)
-#define bfin_read_DMA46_CURR_BWL_COUNT()	bfin_read32(DMA46_CURR_BWL_COUNT)
-#define bfin_write_DMA46_CURR_BWL_COUNT(val)	bfin_write32(DMA46_CURR_BWL_COUNT, val)
-#define bfin_read_DMA46_BWM_COUNT()		bfin_read32(DMA46_BWM_COUNT)
-#define bfin_write_DMA46_BWM_COUNT(val)		bfin_write32(DMA46_BWM_COUNT, val)
-#define bfin_read_DMA46_CURR_BWM_COUNT()	bfin_read32(DMA46_CURR_BWM_COUNT)
-#define bfin_write_DMA46_CURR_BWM_COUNT(val)	bfin_write32(DMA46_CURR_BWM_COUNT, val)
-
-
-/* EPPI1 Registers */
-
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET()		bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val)		bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()		bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val)	bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST()		bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val)		bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN()		bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)		bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()		bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val)		bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()		bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val)	bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()		bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val)	bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR()		bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val)	bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()		bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val)		bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()			bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)		bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET()		bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val)		bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()		bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val)	bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST()		bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val)		bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN()		bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)		bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()		bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val)		bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()		bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val)	bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()		bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val)	bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR()		bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val)	bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()		bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val)		bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()			bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)		bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET()		bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val)		bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()		bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val)	bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST()		bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val)		bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN()		bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)		bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()		bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val)		bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()		bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val)	bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()		bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val)	bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR()		bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val)	bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()		bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val)		bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()			bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)		bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET()		bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val)		bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()		bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val)	bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST()		bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val)		bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN()		bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)		bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()		bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val)		bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()		bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val)	bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()		bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val)	bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR()		bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val)	bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()		bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val)		bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()			bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)		bfin_write32(PINT3_LATCH, val)
-
-/* Port Interrubfin_read_()t 4 Registers (32-bit) */
-
-#define bfin_read_PINT4_MASK_SET()		bfin_read32(PINT4_MASK_SET)
-#define bfin_write_PINT4_MASK_SET(val)		bfin_write32(PINT4_MASK_SET, val)
-#define bfin_read_PINT4_MASK_CLEAR()		bfin_read32(PINT4_MASK_CLEAR)
-#define bfin_write_PINT4_MASK_CLEAR(val)	bfin_write32(PINT4_MASK_CLEAR, val)
-#define bfin_read_PINT4_REQUEST()		bfin_read32(PINT4_REQUEST)
-#define bfin_write_PINT4_REQUEST(val)		bfin_write32(PINT4_REQUEST, val)
-#define bfin_read_PINT4_ASSIGN()		bfin_read32(PINT4_ASSIGN)
-#define bfin_write_PINT4_ASSIGN(val)		bfin_write32(PINT4_ASSIGN, val)
-#define bfin_read_PINT4_EDGE_SET()		bfin_read32(PINT4_EDGE_SET)
-#define bfin_write_PINT4_EDGE_SET(val)		bfin_write32(PINT4_EDGE_SET, val)
-#define bfin_read_PINT4_EDGE_CLEAR()		bfin_read32(PINT4_EDGE_CLEAR)
-#define bfin_write_PINT4_EDGE_CLEAR(val)	bfin_write32(PINT4_EDGE_CLEAR, val)
-#define bfin_read_PINT4_INVERT_SET()		bfin_read32(PINT4_INVERT_SET)
-#define bfin_write_PINT4_INVERT_SET(val)	bfin_write32(PINT4_INVERT_SET, val)
-#define bfin_read_PINT4_INVERT_CLEAR()		bfin_read32(PINT4_INVERT_CLEAR)
-#define bfin_write_PINT4_INVERT_CLEAR(val)	bfin_write32(PINT4_INVERT_CLEAR, val)
-#define bfin_read_PINT4_PINSTATE()		bfin_read32(PINT4_PINSTATE)
-#define bfin_write_PINT4_PINSTATE(val)		bfin_write32(PINT4_PINSTATE, val)
-#define bfin_read_PINT4_LATCH()			bfin_read32(PINT4_LATCH)
-#define bfin_write_PINT4_LATCH(val)		bfin_write32(PINT4_LATCH, val)
-
-/* Port Interrubfin_read_()t 5 Registers (32-bit) */
-
-#define bfin_read_PINT5_MASK_SET()		bfin_read32(PINT5_MASK_SET)
-#define bfin_write_PINT5_MASK_SET(val)		bfin_write32(PINT5_MASK_SET, val)
-#define bfin_read_PINT5_MASK_CLEAR()		bfin_read32(PINT5_MASK_CLEAR)
-#define bfin_write_PINT5_MASK_CLEAR(val)	bfin_write32(PINT5_MASK_CLEAR, val)
-#define bfin_read_PINT5_REQUEST()		bfin_read32(PINT5_REQUEST)
-#define bfin_write_PINT5_REQUEST(val)		bfin_write32(PINT5_REQUEST, val)
-#define bfin_read_PINT5_ASSIGN()		bfin_read32(PINT5_ASSIGN)
-#define bfin_write_PINT5_ASSIGN(val)		bfin_write32(PINT5_ASSIGN, val)
-#define bfin_read_PINT5_EDGE_SET()		bfin_read32(PINT5_EDGE_SET)
-#define bfin_write_PINT5_EDGE_SET(val)		bfin_write32(PINT5_EDGE_SET, val)
-#define bfin_read_PINT5_EDGE_CLEAR()		bfin_read32(PINT5_EDGE_CLEAR)
-#define bfin_write_PINT5_EDGE_CLEAR(val)	bfin_write32(PINT5_EDGE_CLEAR, val)
-#define bfin_read_PINT5_INVERT_SET()		bfin_read32(PINT5_INVERT_SET)
-#define bfin_write_PINT5_INVERT_SET(val)	bfin_write32(PINT5_INVERT_SET, val)
-#define bfin_read_PINT5_INVERT_CLEAR()		bfin_read32(PINT5_INVERT_CLEAR)
-#define bfin_write_PINT5_INVERT_CLEAR(val)	bfin_write32(PINT5_INVERT_CLEAR, val)
-#define bfin_read_PINT5_PINSTATE()		bfin_read32(PINT5_PINSTATE)
-#define bfin_write_PINT5_PINSTATE(val)		bfin_write32(PINT5_PINSTATE, val)
-#define bfin_read_PINT5_LATCH()			bfin_read32(PINT5_LATCH)
-#define bfin_write_PINT5_LATCH(val)		bfin_write32(PINT5_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER()		bfin_read32(PORTA_FER)
-#define bfin_write_PORTA_FER(val)	bfin_write32(PORTA_FER, val)
-#define bfin_read_PORTA_FER_SET()	bfin_read32(PORTA_FER_SET)
-#define bfin_write_PORTA_FER_SET(val)	bfin_write32(PORTA_FER_SET, val)
-#define bfin_read_PORTA_FER_CLEAR()	bfin_read32(PORTA_FER_CLEAR)
-#define bfin_write_PORTA_FER_CLEAR(val)	bfin_write32(PORTA_FER_CLEAR, val)
-#define bfin_read_PORTA()		bfin_read32(PORTA)
-#define bfin_write_PORTA(val)		bfin_write32(PORTA, val)
-#define bfin_read_PORTA_SET()		bfin_read32(PORTA_SET)
-#define bfin_write_PORTA_SET(val)	bfin_write32(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()		bfin_read32(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)	bfin_write32(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR()		bfin_read32(PORTA_DIR)
-#define bfin_write_PORTA_DIR(val)	bfin_write32(PORTA_DIR, val)
-#define bfin_read_PORTA_DIR_SET()	bfin_read32(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)	bfin_write32(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()	bfin_read32(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val)	bfin_write32(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()		bfin_read32(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)	bfin_write32(PORTA_INEN, val)
-#define bfin_read_PORTA_INEN_SET()	bfin_read32(PORTA_INEN_SET)
-#define bfin_write_PORTA_INEN_SET(val)	bfin_write32(PORTA_INEN_SET, val)
-#define bfin_read_PORTA_INEN_CLEAR()	bfin_read32(PORTA_INEN_CLEAR)
-#define bfin_write_PORTA_INEN_CLEAR(val)	bfin_write32(PORTA_INEN_CLEAR, val)
-#define bfin_read_PORTA_MUX()		bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)	bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTA_DATA_TGL()	bfin_read32(PORTA_DATA_TGL)
-#define bfin_write_PORTA_DATA_TGL(val)	bfin_write32(PORTA_DATA_TGL, val)
-#define bfin_read_PORTA_POL()		bfin_read32(PORTA_POL)
-#define bfin_write_PORTA_POL(val)	bfin_write32(PORTA_POL, val)
-#define bfin_read_PORTA_POL_SET()	bfin_read32(PORTA_POL_SET)
-#define bfin_write_PORTA_POL_SET(val)	bfin_write32(PORTA_POL_SET, val)
-#define bfin_read_PORTA_POL_CLEAR()	bfin_read32(PORTA_POL_CLEAR)
-#define bfin_write_PORTA_POL_CLEAR(val)	bfin_write32(PORTA_POL_CLEAR, val)
-#define bfin_read_PORTA_LOCK()		bfin_read32(PORTA_LOCK)
-#define bfin_write_PORTA_LOCK(val)	bfin_write32(PORTA_LOCK, val)
-#define bfin_read_PORTA_REVID()		bfin_read32(PORTA_REVID)
-#define bfin_write_PORTA_REVID(val)	bfin_write32(PORTA_REVID, val)
-
-
-
-/* Port B Registers */
-#define bfin_read_PORTB_FER()		bfin_read32(PORTB_FER)
-#define bfin_write_PORTB_FER(val)	bfin_write32(PORTB_FER, val)
-#define bfin_read_PORTB_FER_SET()	bfin_read32(PORTB_FER_SET)
-#define bfin_write_PORTB_FER_SET(val)	bfin_write32(PORTB_FER_SET, val)
-#define bfin_read_PORTB_FER_CLEAR()	bfin_read32(PORTB_FER_CLEAR)
-#define bfin_write_PORTB_FER_CLEAR(val)	bfin_write32(PORTB_FER_CLEAR, val)
-#define bfin_read_PORTB()		bfin_read32(PORTB)
-#define bfin_write_PORTB(val)		bfin_write32(PORTB, val)
-#define bfin_read_PORTB_SET()		bfin_read32(PORTB_SET)
-#define bfin_write_PORTB_SET(val)	bfin_write32(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()		bfin_read32(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)	bfin_write32(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR()		bfin_read32(PORTB_DIR)
-#define bfin_write_PORTB_DIR(val)	bfin_write32(PORTB_DIR, val)
-#define bfin_read_PORTB_DIR_SET()	bfin_read32(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)	bfin_write32(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()	bfin_read32(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val)	bfin_write32(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()		bfin_read32(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)	bfin_write32(PORTB_INEN, val)
-#define bfin_read_PORTB_INEN_SET()	bfin_read32(PORTB_INEN_SET)
-#define bfin_write_PORTB_INEN_SET(val)	bfin_write32(PORTB_INEN_SET, val)
-#define bfin_read_PORTB_INEN_CLEAR()	bfin_read32(PORTB_INEN_CLEAR)
-#define bfin_write_PORTB_INEN_CLEAR(val)	bfin_write32(PORTB_INEN_CLEAR, val)
-#define bfin_read_PORTB_MUX()		bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)	bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTB_DATA_TGL()	bfin_read32(PORTB_DATA_TGL)
-#define bfin_write_PORTB_DATA_TGL(val)	bfin_write32(PORTB_DATA_TGL, val)
-#define bfin_read_PORTB_POL()		bfin_read32(PORTB_POL)
-#define bfin_write_PORTB_POL(val)	bfin_write32(PORTB_POL, val)
-#define bfin_read_PORTB_POL_SET()	bfin_read32(PORTB_POL_SET)
-#define bfin_write_PORTB_POL_SET(val)	bfin_write32(PORTB_POL_SET, val)
-#define bfin_read_PORTB_POL_CLEAR()	bfin_read32(PORTB_POL_CLEAR)
-#define bfin_write_PORTB_POL_CLEAR(val)	bfin_write32(PORTB_POL_CLEAR, val)
-#define bfin_read_PORTB_LOCK()		bfin_read32(PORTB_LOCK)
-#define bfin_write_PORTB_LOCK(val)	bfin_write32(PORTB_LOCK, val)
-#define bfin_read_PORTB_REVID()		bfin_read32(PORTB_REVID)
-#define bfin_write_PORTB_REVID(val)	bfin_write32(PORTB_REVID, val)
-
-
-/* Port C Registers */
-#define bfin_read_PORTC_FER()		bfin_read32(PORTC_FER)
-#define bfin_write_PORTC_FER(val)	bfin_write32(PORTC_FER, val)
-#define bfin_read_PORTC_FER_SET()	bfin_read32(PORTC_FER_SET)
-#define bfin_write_PORTC_FER_SET(val)	bfin_write32(PORTC_FER_SET, val)
-#define bfin_read_PORTC_FER_CLEAR()	bfin_read32(PORTC_FER_CLEAR)
-#define bfin_write_PORTC_FER_CLEAR(val)	bfin_write32(PORTC_FER_CLEAR, val)
-#define bfin_read_PORTC()		bfin_read32(PORTC)
-#define bfin_write_PORTC(val)		bfin_write32(PORTC, val)
-#define bfin_read_PORTC_SET()		bfin_read32(PORTC_SET)
-#define bfin_write_PORTC_SET(val)	bfin_write32(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()		bfin_read32(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)	bfin_write32(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR()		bfin_read32(PORTC_DIR)
-#define bfin_write_PORTC_DIR(val)	bfin_write32(PORTC_DIR, val)
-#define bfin_read_PORTC_DIR_SET()	bfin_read32(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)	bfin_write32(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()	bfin_read32(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val)	bfin_write32(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()		bfin_read32(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)	bfin_write32(PORTC_INEN, val)
-#define bfin_read_PORTC_INEN_SET()	bfin_read32(PORTC_INEN_SET)
-#define bfin_write_PORTC_INEN_SET(val)	bfin_write32(PORTC_INEN_SET, val)
-#define bfin_read_PORTC_INEN_CLEAR()	bfin_read32(PORTC_INEN_CLEAR)
-#define bfin_write_PORTC_INEN_CLEAR(val)	bfin_write32(PORTC_INEN_CLEAR, val)
-#define bfin_read_PORTC_MUX()		bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)	bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTC_DATA_TGL()	bfin_read32(PORTC_DATA_TGL)
-#define bfin_write_PORTC_DATA_TGL(val)	bfin_write32(PORTC_DATA_TGL, val)
-#define bfin_read_PORTC_POL()		bfin_read32(PORTC_POL)
-#define bfin_write_PORTC_POL(val)	bfin_write32(PORTC_POL, val)
-#define bfin_read_PORTC_POL_SET()	bfin_read32(PORTC_POL_SET)
-#define bfin_write_PORTC_POL_SET(val)	bfin_write32(PORTC_POL_SET, val)
-#define bfin_read_PORTC_POL_CLEAR()	bfin_read32(PORTC_POL_CLEAR)
-#define bfin_write_PORTC_POL_CLEAR(val)	bfin_write32(PORTC_POL_CLEAR, val)
-#define bfin_read_PORTC_LOCK()		bfin_read32(PORTC_LOCK)
-#define bfin_write_PORTC_LOCK(val)	bfin_write32(PORTC_LOCK, val)
-#define bfin_read_PORTC_REVID()		bfin_read32(PORTC_REVID)
-#define bfin_write_PORTC_REVID(val)	bfin_write32(PORTC_REVID, val)
-
-
-/* Port D Registers */
-#define bfin_read_PORTD_FER()		bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER(val)	bfin_write32(PORTD_FER, val)
-#define bfin_read_PORTD_FER_SET()	bfin_read32(PORTD_FER_SET)
-#define bfin_write_PORTD_FER_SET(val)	bfin_write32(PORTD_FER_SET, val)
-#define bfin_read_PORTD_FER_CLEAR()	bfin_read32(PORTD_FER_CLEAR)
-#define bfin_write_PORTD_FER_CLEAR(val)	bfin_write32(PORTD_FER_CLEAR, val)
-#define bfin_read_PORTD()		bfin_read32(PORTD)
-#define bfin_write_PORTD(val)		bfin_write32(PORTD, val)
-#define bfin_read_PORTD_SET()		bfin_read32(PORTD_SET)
-#define bfin_write_PORTD_SET(val)	bfin_write32(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()		bfin_read32(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)	bfin_write32(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR()		bfin_read32(PORTD_DIR)
-#define bfin_write_PORTD_DIR(val)	bfin_write32(PORTD_DIR, val)
-#define bfin_read_PORTD_DIR_SET()	bfin_read32(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)	bfin_write32(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()	bfin_read32(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val)	bfin_write32(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()		bfin_read32(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)	bfin_write32(PORTD_INEN, val)
-#define bfin_read_PORTD_INEN_SET()	bfin_read32(PORTD_INEN_SET)
-#define bfin_write_PORTD_INEN_SET(val)	bfin_write32(PORTD_INEN_SET, val)
-#define bfin_read_PORTD_INEN_CLEAR()	bfin_read32(PORTD_INEN_CLEAR)
-#define bfin_write_PORTD_INEN_CLEAR(val)	bfin_write32(PORTD_INEN_CLEAR, val)
-#define bfin_read_PORTD_MUX()		bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)	bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTD_DATA_TGL()	bfin_read32(PORTD_DATA_TGL)
-#define bfin_write_PORTD_DATA_TGL(val)	bfin_write32(PORTD_DATA_TGL, val)
-#define bfin_read_PORTD_POL()		bfin_read32(PORTD_POL)
-#define bfin_write_PORTD_POL(val)	bfin_write32(PORTD_POL, val)
-#define bfin_read_PORTD_POL_SET()	bfin_read32(PORTD_POL_SET)
-#define bfin_write_PORTD_POL_SET(val)	bfin_write32(PORTD_POL_SET, val)
-#define bfin_read_PORTD_POL_CLEAR()	bfin_read32(PORTD_POL_CLEAR)
-#define bfin_write_PORTD_POL_CLEAR(val)	bfin_write32(PORTD_POL_CLEAR, val)
-#define bfin_read_PORTD_LOCK()		bfin_read32(PORTD_LOCK)
-#define bfin_write_PORTD_LOCK(val)	bfin_write32(PORTD_LOCK, val)
-#define bfin_read_PORTD_REVID()		bfin_read32(PORTD_REVID)
-#define bfin_write_PORTD_REVID(val)	bfin_write32(PORTD_REVID, val)
-
-
-/* Port E Registers */
-#define bfin_read_PORTE_FER()		bfin_read32(PORTE_FER)
-#define bfin_write_PORTE_FER(val)	bfin_write32(PORTE_FER, val)
-#define bfin_read_PORTE_FER_SET()	bfin_read32(PORTE_FER_SET)
-#define bfin_write_PORTE_FER_SET(val)	bfin_write32(PORTE_FER_SET, val)
-#define bfin_read_PORTE_FER_CLEAR()	bfin_read32(PORTE_FER_CLEAR)
-#define bfin_write_PORTE_FER_CLEAR(val)	bfin_write32(PORTE_FER_CLEAR, val)
-#define bfin_read_PORTE()		bfin_read32(PORTE)
-#define bfin_write_PORTE(val)		bfin_write32(PORTE, val)
-#define bfin_read_PORTE_SET()		bfin_read32(PORTE_SET)
-#define bfin_write_PORTE_SET(val)	bfin_write32(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()		bfin_read32(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)	bfin_write32(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR()		bfin_read32(PORTE_DIR)
-#define bfin_write_PORTE_DIR(val)	bfin_write32(PORTE_DIR, val)
-#define bfin_read_PORTE_DIR_SET()	bfin_read32(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)	bfin_write32(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()	bfin_read32(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val)	bfin_write32(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()		bfin_read32(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)	bfin_write32(PORTE_INEN, val)
-#define bfin_read_PORTE_INEN_SET()	bfin_read32(PORTE_INEN_SET)
-#define bfin_write_PORTE_INEN_SET(val)	bfin_write32(PORTE_INEN_SET, val)
-#define bfin_read_PORTE_INEN_CLEAR()	bfin_read32(PORTE_INEN_CLEAR)
-#define bfin_write_PORTE_INEN_CLEAR(val)	bfin_write32(PORTE_INEN_CLEAR, val)
-#define bfin_read_PORTE_MUX()		bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)	bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTE_DATA_TGL()	bfin_read32(PORTE_DATA_TGL)
-#define bfin_write_PORTE_DATA_TGL(val)	bfin_write32(PORTE_DATA_TGL, val)
-#define bfin_read_PORTE_POL()		bfin_read32(PORTE_POL)
-#define bfin_write_PORTE_POL(val)	bfin_write32(PORTE_POL, val)
-#define bfin_read_PORTE_POL_SET()	bfin_read32(PORTE_POL_SET)
-#define bfin_write_PORTE_POL_SET(val)	bfin_write32(PORTE_POL_SET, val)
-#define bfin_read_PORTE_POL_CLEAR()	bfin_read32(PORTE_POL_CLEAR)
-#define bfin_write_PORTE_POL_CLEAR(val)	bfin_write32(PORTE_POL_CLEAR, val)
-#define bfin_read_PORTE_LOCK()		bfin_read32(PORTE_LOCK)
-#define bfin_write_PORTE_LOCK(val)	bfin_write32(PORTE_LOCK, val)
-#define bfin_read_PORTE_REVID()		bfin_read32(PORTE_REVID)
-#define bfin_write_PORTE_REVID(val)	bfin_write32(PORTE_REVID, val)
-
-
-/* Port F Registers */
-#define bfin_read_PORTF_FER()		bfin_read32(PORTF_FER)
-#define bfin_write_PORTF_FER(val)	bfin_write32(PORTF_FER, val)
-#define bfin_read_PORTF_FER_SET()	bfin_read32(PORTF_FER_SET)
-#define bfin_write_PORTF_FER_SET(val)	bfin_write32(PORTF_FER_SET, val)
-#define bfin_read_PORTF_FER_CLEAR()	bfin_read32(PORTF_FER_CLEAR)
-#define bfin_write_PORTF_FER_CLEAR(val)	bfin_write32(PORTF_FER_CLEAR, val)
-#define bfin_read_PORTF()		bfin_read32(PORTF)
-#define bfin_write_PORTF(val)		bfin_write32(PORTF, val)
-#define bfin_read_PORTF_SET()		bfin_read32(PORTF_SET)
-#define bfin_write_PORTF_SET(val)	bfin_write32(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()		bfin_read32(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)	bfin_write32(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR()		bfin_read32(PORTF_DIR)
-#define bfin_write_PORTF_DIR(val)	bfin_write32(PORTF_DIR, val)
-#define bfin_read_PORTF_DIR_SET()	bfin_read32(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)	bfin_write32(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()	bfin_read32(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val)	bfin_write32(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()		bfin_read32(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)	bfin_write32(PORTF_INEN, val)
-#define bfin_read_PORTF_INEN_SET()	bfin_read32(PORTF_INEN_SET)
-#define bfin_write_PORTF_INEN_SET(val)	bfin_write32(PORTF_INEN_SET, val)
-#define bfin_read_PORTF_INEN_CLEAR()	bfin_read32(PORTF_INEN_CLEAR)
-#define bfin_write_PORTF_INEN_CLEAR(val)	bfin_write32(PORTF_INEN_CLEAR, val)
-#define bfin_read_PORTF_MUX()		bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)	bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTF_DATA_TGL()	bfin_read32(PORTF_DATA_TGL)
-#define bfin_write_PORTF_DATA_TGL(val)	bfin_write32(PORTF_DATA_TGL, val)
-#define bfin_read_PORTF_POL()		bfin_read32(PORTF_POL)
-#define bfin_write_PORTF_POL(val)	bfin_write32(PORTF_POL, val)
-#define bfin_read_PORTF_POL_SET()	bfin_read32(PORTF_POL_SET)
-#define bfin_write_PORTF_POL_SET(val)	bfin_write32(PORTF_POL_SET, val)
-#define bfin_read_PORTF_POL_CLEAR()	bfin_read32(PORTF_POL_CLEAR)
-#define bfin_write_PORTF_POL_CLEAR(val)	bfin_write32(PORTF_POL_CLEAR, val)
-#define bfin_read_PORTF_LOCK()		bfin_read32(PORTF_LOCK)
-#define bfin_write_PORTF_LOCK(val)	bfin_write32(PORTF_LOCK, val)
-#define bfin_read_PORTF_REVID()		bfin_read32(PORTF_REVID)
-#define bfin_write_PORTF_REVID(val)	bfin_write32(PORTF_REVID, val)
-
-
-/* Port G Registers */
-#define bfin_read_PORTG_FER()		bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER(val)	bfin_write32(PORTG_FER, val)
-#define bfin_read_PORTG_FER_SET()	bfin_read32(PORTG_FER_SET)
-#define bfin_write_PORTG_FER_SET(val)	bfin_write32(PORTG_FER_SET, val)
-#define bfin_read_PORTG_FER_CLEAR()	bfin_read32(PORTG_FER_CLEAR)
-#define bfin_write_PORTG_FER_CLEAR(val)	bfin_write32(PORTG_FER_CLEAR, val)
-#define bfin_read_PORTG()		bfin_read32(PORTG)
-#define bfin_write_PORTG(val)		bfin_write32(PORTG, val)
-#define bfin_read_PORTG_SET()		bfin_read32(PORTG_SET)
-#define bfin_write_PORTG_SET(val)	bfin_write32(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()		bfin_read32(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)	bfin_write32(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR()		bfin_read32(PORTG_DIR)
-#define bfin_write_PORTG_DIR(val)	bfin_write32(PORTG_DIR, val)
-#define bfin_read_PORTG_DIR_SET()	bfin_read32(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)	bfin_write32(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()	bfin_read32(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val)	bfin_write32(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()		bfin_read32(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)	bfin_write32(PORTG_INEN, val)
-#define bfin_read_PORTG_INEN_SET()	bfin_read32(PORTG_INEN_SET)
-#define bfin_write_PORTG_INEN_SET(val)	bfin_write32(PORTG_INEN_SET, val)
-#define bfin_read_PORTG_INEN_CLEAR()	bfin_read32(PORTG_INEN_CLEAR)
-#define bfin_write_PORTG_INEN_CLEAR(val)	bfin_write32(PORTG_INEN_CLEAR, val)
-#define bfin_read_PORTG_MUX()		bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)	bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTG_DATA_TGL()	bfin_read32(PORTG_DATA_TGL)
-#define bfin_write_PORTG_DATA_TGL(val)	bfin_write32(PORTG_DATA_TGL, val)
-#define bfin_read_PORTG_POL()		bfin_read32(PORTG_POL)
-#define bfin_write_PORTG_POL(val)	bfin_write32(PORTG_POL, val)
-#define bfin_read_PORTG_POL_SET()	bfin_read32(PORTG_POL_SET)
-#define bfin_write_PORTG_POL_SET(val)	bfin_write32(PORTG_POL_SET, val)
-#define bfin_read_PORTG_POL_CLEAR()	bfin_read32(PORTG_POL_CLEAR)
-#define bfin_write_PORTG_POL_CLEAR(val)	bfin_write32(PORTG_POL_CLEAR, val)
-#define bfin_read_PORTG_LOCK()		bfin_read32(PORTG_LOCK)
-#define bfin_write_PORTG_LOCK(val)	bfin_write32(PORTG_LOCK, val)
-#define bfin_read_PORTG_REVID()		bfin_read32(PORTG_REVID)
-#define bfin_write_PORTG_REVID(val)	bfin_write32(PORTG_REVID, val)
-
-
-
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1()		bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)	bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()		bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)	bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()		bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)	bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()		bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)	bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()		bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)	bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()		bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)	bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()		bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)	bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()		bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)	bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()		bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)	bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()		bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)	bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()		bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)	bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()		bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)	bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()		bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)	bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2()		bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)	bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()		bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)	bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()		bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)	bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()		bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)	bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()		bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)	bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()		bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)	bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()		bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)	bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()		bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)	bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()		bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)	bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()		bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)	bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()		bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)	bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()		bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)	bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()		bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)	bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK()		bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)	bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()		bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)	bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()		bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)	bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()		bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)	bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()		bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)	bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()		bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)	bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()		bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)	bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()		bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)	bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()	bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)	bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()		bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)	bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()		bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)	bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()		bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)	bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()		bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)	bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()		bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)	bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()		bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)	bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()		bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)	bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L()		bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)	bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()		bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)	bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()		bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)	bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()		bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)	bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()		bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)	bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()		bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)	bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()		bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)	bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()		bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)	bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()		bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)	bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()		bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)	bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()		bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)	bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()		bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)	bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()		bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)	bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()		bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)	bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()		bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)	bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()		bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)	bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()		bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)	bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()		bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)	bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()		bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)	bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()		bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)	bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()		bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)	bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()		bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)	bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()		bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)	bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()		bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)	bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()		bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)	bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()		bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)	bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()		bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)	bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()		bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)	bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()		bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)	bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()		bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)	bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()		bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)	bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()		bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)	bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L()		bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)	bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()		bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)	bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()		bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)	bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()		bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)	bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()		bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)	bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()		bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)	bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()		bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)	bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()		bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)	bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()		bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)	bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()		bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)	bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()		bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)	bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()		bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)	bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()		bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)	bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()		bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)	bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()		bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)	bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()		bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)	bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()		bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)	bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()		bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)	bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()		bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)	bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()		bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)	bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()		bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)	bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()		bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)	bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()		bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)	bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()		bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)	bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()		bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)	bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()		bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)	bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()		bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)	bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()		bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)	bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()		bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)	bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()		bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)	bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()		bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)	bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()		bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)	bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0()		bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val)		bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()		bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val)		bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()		bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val)		bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()		bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val)		bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()		bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val)	bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP()		bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val)	bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()		bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)		bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()		bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)		bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()		bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val)		bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()		bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val)		bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()		bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val)		bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()		bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val)		bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()		bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val)	bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP()		bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val)	bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()		bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)		bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()		bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)		bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()		bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val)		bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()		bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val)		bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()		bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val)		bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()		bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val)		bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()		bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val)	bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP()		bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val)	bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()		bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)		bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()		bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)		bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()		bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val)		bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()		bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val)		bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()		bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val)		bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()		bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val)		bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()		bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val)	bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP()		bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val)	bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()		bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)		bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()		bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)		bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()		bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val)		bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()		bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val)		bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()		bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val)		bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()		bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val)		bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()		bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val)	bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP()		bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val)	bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()		bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)		bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()		bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)		bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()		bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val)		bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()		bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val)		bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()		bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val)		bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()		bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val)		bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()		bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val)	bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP()		bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val)	bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()		bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)		bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()		bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)		bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()		bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val)		bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()		bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val)		bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()		bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val)		bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()		bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val)		bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()		bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val)	bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP()		bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val)	bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()		bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)		bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()		bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)		bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()		bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val)		bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()		bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val)		bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()		bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val)		bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()		bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val)		bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()		bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val)	bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP()		bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val)	bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()		bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)		bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()		bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)		bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()		bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val)		bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()		bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val)		bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()		bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val)		bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()		bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val)		bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()		bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val)	bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP()		bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val)	bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()		bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)		bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()		bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)		bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()		bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val)		bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()		bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val)		bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()		bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val)		bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()		bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val)		bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()		bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val)	bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP()		bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val)	bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()		bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)		bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()		bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)		bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()		bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val)		bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()		bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val)		bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()		bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val)		bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()		bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val)		bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()		bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val)	bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP()		bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val)	bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()		bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)		bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()		bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)		bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()		bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val)		bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()		bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val)		bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()		bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val)		bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()		bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val)		bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()		bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val)	bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP()		bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val)	bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()		bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)		bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()		bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)		bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()		bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val)		bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()		bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val)		bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()		bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val)		bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()		bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val)		bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()		bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val)	bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP()		bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val)	bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()		bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)		bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()		bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)		bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()		bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val)		bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()		bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val)		bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()		bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val)		bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()		bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val)		bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()		bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val)	bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP()		bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val)	bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()		bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)		bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()		bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)		bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()		bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val)		bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()		bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val)		bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()		bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val)		bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()		bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val)		bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()		bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val)	bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP()		bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val)	bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()		bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)		bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()		bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)		bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()		bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val)		bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()		bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val)		bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()		bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val)		bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()		bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val)		bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()		bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val)	bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP()		bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val)	bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()		bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)		bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()		bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)		bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0()		bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val)		bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()		bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val)		bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()		bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val)		bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()		bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val)		bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()		bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val)	bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP()		bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val)	bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()		bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)		bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()		bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)		bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()		bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val)		bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()		bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val)		bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()		bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val)		bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()		bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val)		bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()		bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val)	bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP()		bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val)	bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()		bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)		bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()		bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)		bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()		bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val)		bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()		bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val)		bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()		bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val)		bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()		bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val)		bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()		bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val)	bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP()		bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val)	bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()		bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)		bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()		bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)		bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()		bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val)		bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()		bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val)		bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()		bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val)		bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()		bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val)		bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()		bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val)	bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP()		bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val)	bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()		bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)		bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()		bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)		bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()		bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val)		bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()		bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val)		bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()		bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val)		bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()		bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val)		bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()		bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val)	bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP()		bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val)	bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()		bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)		bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()		bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)		bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()		bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val)		bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()		bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val)		bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()		bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val)		bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()		bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val)		bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()		bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val)	bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP()		bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val)	bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()		bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)		bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()		bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)		bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()		bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val)		bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()		bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val)		bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()		bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val)		bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()		bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val)		bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()		bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val)	bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP()		bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val)	bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()		bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)		bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()		bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)		bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()		bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val)		bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()		bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val)		bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()		bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val)		bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()		bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val)		bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()		bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val)	bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP()		bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val)	bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()		bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)		bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()		bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)		bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()		bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val)		bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()		bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val)		bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()		bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val)		bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()		bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val)		bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()		bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val)	bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP()		bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val)	bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()		bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)		bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()		bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)		bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()		bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val)		bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()		bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val)		bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()		bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val)		bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()		bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val)		bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()		bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val)	bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP()		bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val)	bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()		bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)		bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()		bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)		bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()		bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val)		bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()		bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val)		bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()		bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val)		bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()		bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val)		bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()		bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val)	bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP()		bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val)	bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()		bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)		bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()		bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)		bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()		bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val)		bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()		bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val)		bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()		bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val)		bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()		bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val)		bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()		bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val)	bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP()		bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val)	bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()		bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)		bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()		bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)		bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()		bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val)		bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()		bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val)		bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()		bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val)		bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()		bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val)		bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()		bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val)	bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP()		bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val)	bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()		bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)		bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()		bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)		bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()		bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val)		bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()		bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val)		bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()		bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val)		bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()		bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val)		bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()		bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val)	bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP()		bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val)	bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()		bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)		bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()		bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)		bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()		bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val)		bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()		bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val)		bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()		bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val)		bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()		bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val)		bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()		bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val)	bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP()		bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val)	bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()		bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)		bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()		bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)		bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()		bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val)		bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()		bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val)		bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()		bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val)		bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()		bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val)		bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()		bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val)	bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP()		bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val)	bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()		bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)		bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()		bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)		bfin_write16(CAN0_MB31_ID1, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()		bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)	bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()		bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)	bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()		bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)	bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()		bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)	bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()	bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)	bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()		bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)	bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()		bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)		bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()		bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)		bfin_write32(CNT_MIN, val)
-
-/* RSI Register */
-#define bfin_read_RSI_CLK_CTL()		bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val)	bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()	bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)	bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()		bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)	bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()	bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)	bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()	bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)	bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()	bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)	bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()	bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)	bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()	bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)	bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()	bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val)	bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()	bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)	bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL()	bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val)	bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()	bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)	bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()		bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)	bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR()	bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val)	bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()		bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)	bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()		bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)	bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()	bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)	bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL()	bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val)	bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ()		bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val)	bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO()		bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)	bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS()	bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val)	bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK()		bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val)	bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CFG()		bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val)		bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()	bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val)	bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()		bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)	bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()		bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)	bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()		bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)	bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()		bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)	bfin_write16(RSI_PID3, val)
-
-/* usb register */
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#endif /* _CDEF_BF60X_H */
-
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
deleted file mode 100644
index 8045ade34370..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
-#include "defBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-/* =========================
-	PIXC Registers
-   ========================= */
-
-/* =========================
-	PIXC0
-   ========================= */
-#define PIXC0_CTL                   0xFFC19000         /* PIXC0 Control Register */
-#define PIXC0_PPL                   0xFFC19004         /* PIXC0 Pixels Per Line Register */
-#define PIXC0_LPF                   0xFFC19008         /* PIXC0 Line Per Frame Register */
-#define PIXC0_HSTART_A              0xFFC1900C         /* PIXC0 Overlay A Horizontal Start Register */
-#define PIXC0_HEND_A                0xFFC19010         /* PIXC0 Overlay A Horizontal End Register */
-#define PIXC0_VSTART_A              0xFFC19014         /* PIXC0 Overlay A Vertical Start Register */
-#define PIXC0_VEND_A                0xFFC19018         /* PIXC0 Overlay A Vertical End Register */
-#define PIXC0_TRANSP_A              0xFFC1901C         /* PIXC0 Overlay A Transparency Ratio Register */
-#define PIXC0_HSTART_B              0xFFC19020         /* PIXC0 Overlay B Horizontal Start Register */
-#define PIXC0_HEND_B                0xFFC19024         /* PIXC0 Overlay B Horizontal End Register */
-#define PIXC0_VSTART_B              0xFFC19028         /* PIXC0 Overlay B Vertical Start Register */
-#define PIXC0_VEND_B                0xFFC1902C         /* PIXC0 Overlay B Vertical End Register */
-#define PIXC0_TRANSP_B              0xFFC19030         /* PIXC0 Overlay B Transparency Ratio Register */
-#define PIXC0_IRQSTAT               0xFFC1903C         /* PIXC0 Interrupt Status Register */
-#define PIXC0_CONRY                 0xFFC19040         /* PIXC0 RY Conversion Component Register */
-#define PIXC0_CONGU                 0xFFC19044         /* PIXC0 GU Conversion Component Register */
-#define PIXC0_CONBV                 0xFFC19048         /* PIXC0 BV Conversion Component Register */
-#define PIXC0_CCBIAS                0xFFC1904C         /* PIXC0 Conversion Bias Register */
-#define PIXC0_TC                    0xFFC19050         /* PIXC0 Transparency Register */
-#define PIXC0_REVID                 0xFFC19054         /* PIXC0 PIXC Revision Id */
-
-/* =========================
-	PVP Registers
-   ========================= */
-
-/* =========================
-	PVP0
-   ========================= */
-#define PVP0_REVID                  0xFFC1A000         /* PVP0 Revision ID */
-#define PVP0_CTL                    0xFFC1A004         /* PVP0 Control */
-#define PVP0_IMSK0                  0xFFC1A008         /* PVP0 INTn interrupt line masks */
-#define PVP0_IMSK1                  0xFFC1A00C         /* PVP0 INTn interrupt line masks */
-#define PVP0_STAT                   0xFFC1A010         /* PVP0 Status */
-#define PVP0_ILAT                   0xFFC1A014         /* PVP0 Latched status */
-#define PVP0_IREQ0                  0xFFC1A018         /* PVP0 INT0 masked latched status */
-#define PVP0_IREQ1                  0xFFC1A01C         /* PVP0 INT0 masked latched status */
-#define PVP0_OPF0_CFG               0xFFC1A020         /* PVP0 Config */
-#define PVP0_OPF1_CFG               0xFFC1A040         /* PVP0 Config */
-#define PVP0_OPF2_CFG               0xFFC1A060         /* PVP0 Config */
-#define PVP0_OPF0_CTL               0xFFC1A024         /* PVP0 Control */
-#define PVP0_OPF1_CTL               0xFFC1A044         /* PVP0 Control */
-#define PVP0_OPF2_CTL               0xFFC1A064         /* PVP0 Control */
-#define PVP0_OPF3_CFG               0xFFC1A080         /* PVP0 Config */
-#define PVP0_OPF3_CTL               0xFFC1A084         /* PVP0 Control */
-#define PVP0_PEC_CFG                0xFFC1A0A0         /* PVP0 Config */
-#define PVP0_PEC_CTL                0xFFC1A0A4         /* PVP0 Control */
-#define PVP0_PEC_D1TH0              0xFFC1A0A8         /* PVP0 Lower Hysteresis Threshold */
-#define PVP0_PEC_D1TH1              0xFFC1A0AC         /* PVP0 Upper Hysteresis Threshold */
-#define PVP0_PEC_D2TH0              0xFFC1A0B0         /* PVP0 Weak Zero Crossing Threshold */
-#define PVP0_PEC_D2TH1              0xFFC1A0B4         /* PVP0 Strong Zero Crossing Threshold */
-#define PVP0_IIM0_CFG               0xFFC1A0C0         /* PVP0 Config */
-#define PVP0_IIM1_CFG               0xFFC1A0E0         /* PVP0 Config */
-#define PVP0_IIM0_CTL               0xFFC1A0C4         /* PVP0 Control */
-#define PVP0_IIM1_CTL               0xFFC1A0E4         /* PVP0 Control */
-#define PVP0_IIM0_SCALE             0xFFC1A0C8         /* PVP0 Scaler Values */
-#define PVP0_IIM1_SCALE             0xFFC1A0E8         /* PVP0 Scaler Values */
-#define PVP0_IIM0_SOVF_STAT         0xFFC1A0CC         /* PVP0 Signed Overflow Status */
-#define PVP0_IIM1_SOVF_STAT         0xFFC1A0EC         /* PVP0 Signed Overflow Status */
-#define PVP0_IIM0_UOVF_STAT         0xFFC1A0D0         /* PVP0 Unsigned Overflow Status */
-#define PVP0_IIM1_UOVF_STAT         0xFFC1A0F0         /* PVP0 Unsigned Overflow Status */
-#define PVP0_ACU_CFG                0xFFC1A100         /* PVP0 ACU Configuration Register */
-#define PVP0_ACU_CTL                0xFFC1A104         /* PVP0 ACU Control Register */
-#define PVP0_ACU_OFFSET             0xFFC1A108         /* PVP0 SUM constant register */
-#define PVP0_ACU_FACTOR             0xFFC1A10C         /* PVP0 PROD constant register */
-#define PVP0_ACU_SHIFT              0xFFC1A110         /* PVP0 Shift constant register */
-#define PVP0_ACU_MIN                0xFFC1A114         /* PVP0 Lower saturation threshold set to MIN */
-#define PVP0_ACU_MAX                0xFFC1A118         /* PVP0 Upper saturation threshold set to MAX */
-#define PVP0_UDS_CFG                0xFFC1A140         /* PVP0 UDS Configuration Register */
-#define PVP0_UDS_CTL                0xFFC1A144         /* PVP0 UDS Control Register */
-#define PVP0_UDS_OHCNT              0xFFC1A148         /* PVP0 UDS Output H Dimension */
-#define PVP0_UDS_OVCNT              0xFFC1A14C         /* PVP0 UDS Output V Dimension */
-#define PVP0_UDS_HAVG               0xFFC1A150         /* PVP0 UDS H Taps */
-#define PVP0_UDS_VAVG               0xFFC1A154         /* PVP0 UDS V Taps */
-#define PVP0_IPF0_CFG               0xFFC1A180         /* PVP0 Configuration */
-#define PVP0_IPF0_PIPECTL           0xFFC1A184         /* PVP0 Pipe Control */
-#define PVP0_IPF1_PIPECTL           0xFFC1A1C4         /* PVP0 Pipe Control */
-#define PVP0_IPF0_CTL               0xFFC1A188         /* PVP0 Control */
-#define PVP0_IPF1_CTL               0xFFC1A1C8         /* PVP0 Control */
-#define PVP0_IPF0_TAG               0xFFC1A18C         /* PVP0 TAG Value */
-#define PVP0_IPF1_TAG               0xFFC1A1CC         /* PVP0 TAG Value */
-#define PVP0_IPF0_FCNT              0xFFC1A190         /* PVP0 Frame Count */
-#define PVP0_IPF1_FCNT              0xFFC1A1D0         /* PVP0 Frame Count */
-#define PVP0_IPF0_HCNT              0xFFC1A194         /* PVP0 Horizontal Count */
-#define PVP0_IPF1_HCNT              0xFFC1A1D4         /* PVP0 Horizontal Count */
-#define PVP0_IPF0_VCNT              0xFFC1A198         /* PVP0 Vertical Count */
-#define PVP0_IPF1_VCNT              0xFFC1A1D8         /* PVP0 Vertical Count */
-#define PVP0_IPF0_HPOS              0xFFC1A19C         /* PVP0 Horizontal Position */
-#define PVP0_IPF0_VPOS              0xFFC1A1A0         /* PVP0 Vertical Position */
-#define PVP0_IPF0_TAG_STAT          0xFFC1A1A4         /* PVP0 TAG Status */
-#define PVP0_IPF1_TAG_STAT          0xFFC1A1E4         /* PVP0 TAG Status */
-#define PVP0_IPF1_CFG               0xFFC1A1C0         /* PVP0 Configuration */
-#define PVP0_CNV0_CFG               0xFFC1A200         /* PVP0 Configuration */
-#define PVP0_CNV1_CFG               0xFFC1A280         /* PVP0 Configuration */
-#define PVP0_CNV2_CFG               0xFFC1A300         /* PVP0 Configuration */
-#define PVP0_CNV3_CFG               0xFFC1A380         /* PVP0 Configuration */
-#define PVP0_CNV0_CTL               0xFFC1A204         /* PVP0 Control */
-#define PVP0_CNV1_CTL               0xFFC1A284         /* PVP0 Control */
-#define PVP0_CNV2_CTL               0xFFC1A304         /* PVP0 Control */
-#define PVP0_CNV3_CTL               0xFFC1A384         /* PVP0 Control */
-#define PVP0_CNV0_C00C01            0xFFC1A208         /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV1_C00C01            0xFFC1A288         /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV2_C00C01            0xFFC1A308         /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV3_C00C01            0xFFC1A388         /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV0_C02C03            0xFFC1A20C         /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV1_C02C03            0xFFC1A28C         /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV2_C02C03            0xFFC1A30C         /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV3_C02C03            0xFFC1A38C         /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV0_C04               0xFFC1A210         /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV1_C04               0xFFC1A290         /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV2_C04               0xFFC1A310         /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV3_C04               0xFFC1A390         /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV0_C10C11            0xFFC1A214         /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV1_C10C11            0xFFC1A294         /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV2_C10C11            0xFFC1A314         /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV3_C10C11            0xFFC1A394         /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV0_C12C13            0xFFC1A218         /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV1_C12C13            0xFFC1A298         /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV2_C12C13            0xFFC1A318         /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV3_C12C13            0xFFC1A398         /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV0_C14               0xFFC1A21C         /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV1_C14               0xFFC1A29C         /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV2_C14               0xFFC1A31C         /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV3_C14               0xFFC1A39C         /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV0_C20C21            0xFFC1A220         /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV1_C20C21            0xFFC1A2A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV2_C20C21            0xFFC1A320         /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV3_C20C21            0xFFC1A3A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV0_C22C23            0xFFC1A224         /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV1_C22C23            0xFFC1A2A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV2_C22C23            0xFFC1A324         /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV3_C22C23            0xFFC1A3A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV0_C24               0xFFC1A228         /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV1_C24               0xFFC1A2A8         /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV2_C24               0xFFC1A328         /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV3_C24               0xFFC1A3A8         /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV0_C30C31            0xFFC1A22C         /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV1_C30C31            0xFFC1A2AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV2_C30C31            0xFFC1A32C         /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV3_C30C31            0xFFC1A3AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV0_C32C33            0xFFC1A230         /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV1_C32C33            0xFFC1A2B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV2_C32C33            0xFFC1A330         /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV3_C32C33            0xFFC1A3B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV0_C34               0xFFC1A234         /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV1_C34               0xFFC1A2B4         /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV2_C34               0xFFC1A334         /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV3_C34               0xFFC1A3B4         /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV0_C40C41            0xFFC1A238         /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV1_C40C41            0xFFC1A2B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV2_C40C41            0xFFC1A338         /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV3_C40C41            0xFFC1A3B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV0_C42C43            0xFFC1A23C         /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV1_C42C43            0xFFC1A2BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV2_C42C43            0xFFC1A33C         /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV3_C42C43            0xFFC1A3BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV0_C44               0xFFC1A240         /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV1_C44               0xFFC1A2C0         /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV2_C44               0xFFC1A340         /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV3_C44               0xFFC1A3C0         /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV0_SCALE             0xFFC1A244         /* PVP0 Scaling factor */
-#define PVP0_CNV1_SCALE             0xFFC1A2C4         /* PVP0 Scaling factor */
-#define PVP0_CNV2_SCALE             0xFFC1A344         /* PVP0 Scaling factor */
-#define PVP0_CNV3_SCALE             0xFFC1A3C4         /* PVP0 Scaling factor */
-#define PVP0_THC0_CFG               0xFFC1A400         /* PVP0 Configuration */
-#define PVP0_THC1_CFG               0xFFC1A500         /* PVP0 Configuration */
-#define PVP0_THC0_CTL               0xFFC1A404         /* PVP0 Control */
-#define PVP0_THC1_CTL               0xFFC1A504         /* PVP0 Control */
-#define PVP0_THC0_HFCNT             0xFFC1A408         /* PVP0 Number of frames */
-#define PVP0_THC1_HFCNT             0xFFC1A508         /* PVP0 Number of frames */
-#define PVP0_THC0_RMAXREP           0xFFC1A40C         /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC1_RMAXREP           0xFFC1A50C         /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC0_CMINVAL           0xFFC1A410         /* PVP0 Min clip value */
-#define PVP0_THC1_CMINVAL           0xFFC1A510         /* PVP0 Min clip value */
-#define PVP0_THC0_CMINTH            0xFFC1A414         /* PVP0 Clip Min Threshold */
-#define PVP0_THC1_CMINTH            0xFFC1A514         /* PVP0 Clip Min Threshold */
-#define PVP0_THC0_CMAXTH            0xFFC1A418         /* PVP0 Clip Max Threshold */
-#define PVP0_THC1_CMAXTH            0xFFC1A518         /* PVP0 Clip Max Threshold */
-#define PVP0_THC0_CMAXVAL           0xFFC1A41C         /* PVP0 Max clip value */
-#define PVP0_THC1_CMAXVAL           0xFFC1A51C         /* PVP0 Max clip value */
-#define PVP0_THC0_TH0               0xFFC1A420         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH0               0xFFC1A520         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH1               0xFFC1A424         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH1               0xFFC1A524         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH2               0xFFC1A428         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH2               0xFFC1A528         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH3               0xFFC1A42C         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH3               0xFFC1A52C         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH4               0xFFC1A430         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH4               0xFFC1A530         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH5               0xFFC1A434         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH5               0xFFC1A534         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH6               0xFFC1A438         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH6               0xFFC1A538         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH7               0xFFC1A43C         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH7               0xFFC1A53C         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH8               0xFFC1A440         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH8               0xFFC1A540         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH9               0xFFC1A444         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH9               0xFFC1A544         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH10              0xFFC1A448         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH10              0xFFC1A548         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH11              0xFFC1A44C         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH11              0xFFC1A54C         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH12              0xFFC1A450         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH12              0xFFC1A550         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH13              0xFFC1A454         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH13              0xFFC1A554         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH14              0xFFC1A458         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH14              0xFFC1A558         /* PVP0 Threshold Value */
-#define PVP0_THC0_TH15              0xFFC1A45C         /* PVP0 Threshold Value */
-#define PVP0_THC1_TH15              0xFFC1A55C         /* PVP0 Threshold Value */
-#define PVP0_THC0_HHPOS             0xFFC1A460         /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_HHPOS             0xFFC1A560         /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_HVPOS             0xFFC1A464         /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_HVPOS             0xFFC1A564         /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_HHCNT             0xFFC1A468         /* PVP0 Window width in X dimension */
-#define PVP0_THC1_HHCNT             0xFFC1A568         /* PVP0 Window width in X dimension */
-#define PVP0_THC0_HVCNT             0xFFC1A46C         /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_HVCNT             0xFFC1A56C         /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_RHPOS             0xFFC1A470         /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_RHPOS             0xFFC1A570         /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_RVPOS             0xFFC1A474         /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_RVPOS             0xFFC1A574         /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_RHCNT             0xFFC1A478         /* PVP0 Window width in X dimension */
-#define PVP0_THC1_RHCNT             0xFFC1A578         /* PVP0 Window width in X dimension */
-#define PVP0_THC0_RVCNT             0xFFC1A47C         /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_RVCNT             0xFFC1A57C         /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_HFCNT_STAT        0xFFC1A480         /* PVP0 Current Frame counter */
-#define PVP0_THC1_HFCNT_STAT        0xFFC1A580         /* PVP0 Current Frame counter */
-#define PVP0_THC0_HCNT0_STAT        0xFFC1A484         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT0_STAT        0xFFC1A584         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT1_STAT        0xFFC1A488         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT1_STAT        0xFFC1A588         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT2_STAT        0xFFC1A48C         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT2_STAT        0xFFC1A58C         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT3_STAT        0xFFC1A490         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT3_STAT        0xFFC1A590         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT4_STAT        0xFFC1A494         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT4_STAT        0xFFC1A594         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT5_STAT        0xFFC1A498         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT5_STAT        0xFFC1A598         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT6_STAT        0xFFC1A49C         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT6_STAT        0xFFC1A59C         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT7_STAT        0xFFC1A4A0         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT7_STAT        0xFFC1A5A0         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT8_STAT        0xFFC1A4A4         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT8_STAT        0xFFC1A5A4         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT9_STAT        0xFFC1A4A8         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT9_STAT        0xFFC1A5A8         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT10_STAT       0xFFC1A4AC         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT10_STAT       0xFFC1A5AC         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT11_STAT       0xFFC1A4B0         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT11_STAT       0xFFC1A5B0         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT12_STAT       0xFFC1A4B4         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT12_STAT       0xFFC1A5B4         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT13_STAT       0xFFC1A4B8         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT13_STAT       0xFFC1A5B8         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT14_STAT       0xFFC1A4BC         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT14_STAT       0xFFC1A5BC         /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT15_STAT       0xFFC1A4C0         /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT15_STAT       0xFFC1A5C0         /* PVP0 Histogram counter value */
-#define PVP0_THC0_RREP_STAT         0xFFC1A4C4         /* PVP0 Number of RLE Reports */
-#define PVP0_THC1_RREP_STAT         0xFFC1A5C4         /* PVP0 Number of RLE Reports */
-#define PVP0_PMA_CFG                0xFFC1A600         /* PVP0 PMA Configuration Register */
-
-#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
deleted file mode 100644
index 3933e912cacd..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ /dev/null
@@ -1,3596 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF60X_H
-#define _DEF_BF60X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
-/* ************************************************************** */
-
-
-/* =========================
-        CNT Registers
-   ========================= */
-
-/* =========================
-        CNT0
-   ========================= */
-#define CNT_CONFIG                 0xFFC00400         /* CNT0 Configuration Register */
-#define CNT_IMASK                  0xFFC00404         /* CNT0 Interrupt Mask Register */
-#define CNT_STATUS                 0xFFC00408         /* CNT0 Status Register */
-#define CNT_COMMAND                0xFFC0040C         /* CNT0 Command Register */
-#define CNT_DEBOUNCE               0xFFC00410         /* CNT0 Debounce Register */
-#define CNT_COUNTER                0xFFC00414         /* CNT0 Counter Register */
-#define CNT_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
-#define CNT_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
-
-
-/* =========================
-        RSI Registers
-   ========================= */
-
-#define RSI_CLK_CONTROL            0xFFC00604         /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT               0xFFC00608         /* RSI0 Argument Register */
-#define RSI_COMMAND                0xFFC0060C         /* RSI0 Command Register */
-#define RSI_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
-#define RSI_RESPONSE0              0xFFC00614         /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1              0xFFC00618         /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2              0xFFC0061C         /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3              0xFFC00620         /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER             0xFFC00624         /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH              0xFFC00628         /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL           0xFFC0062C         /* RSI0 Data Control Register */
-#define RSI_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
-#define RSI_STATUS                 0xFFC00634         /* RSI0 Status Register */
-#define RSI_STATUSCL               0xFFC00638         /* RSI0 Status Clear Register */
-#define RSI_MASK0                  0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
-#define RSI_MASK1                  0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL          0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
-#define RSI_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
-#define RSI_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
-#define RSI_ESTAT                  0xFFC006C0         /* RSI0 Exception Status Register */
-#define RSI_EMASK                  0xFFC006C4         /* RSI0 Exception Mask Register */
-#define RSI_CONFIG                 0xFFC006C8         /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN             0xFFC006CC         /* RSI0 Read Wait Enable Register */
-#define RSI_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
-#define RSI_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
-#define RSI_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
-#define RSI_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
-
-/* =========================
-        CAN Registers
-   ========================= */
-
-/* =========================
-        CAN0
-   ========================= */
-#define CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration Register 1 */
-#define CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction Register 1 */
-#define CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set Register 1 */
-#define CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset Register 1 */
-#define CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge Register 1 */
-#define CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending Register 1 */
-#define CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling Register 1 */
-#define CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
-#define CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration Register 2 */
-#define CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction Register 2 */
-#define CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set Register 2 */
-#define CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset Register 2 */
-#define CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge Register 2 */
-#define CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending Register 2 */
-#define CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling Register 2 */
-#define CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
-#define CAN0_CLOCK                    0xFFC00A80         /* CAN0 Clock Register */
-#define CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
-#define CAN0_DEBUG                    0xFFC00A88         /* CAN0 Debug Register */
-#define CAN0_STATUS                   0xFFC00A8C         /* CAN0 Status Register */
-#define CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
-#define CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status */
-#define CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask */
-#define CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag */
-#define CAN0_CONTROL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
-#define CAN0_INTR                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
-#define CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
-#define CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
-#define CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
-#define CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
-#define CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
-#define CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
-#define CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox Word 7 Register */
-
-/* =========================
-	LINK PORT Registers
-   ========================= */
-#define LP0_CTL                     0xFFC01000         /* LP0 Control Register */
-#define LP0_STAT                    0xFFC01004         /* LP0 Status Register */
-#define LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
-#define LP0_CNT                     0xFFC0100C         /* LP0 Current Count Value of Clock Divider */
-#define LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
-#define LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
-#define LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
-#define LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
-#define LP1_CTL                     0xFFC01100         /* LP1 Control Register */
-#define LP1_STAT                    0xFFC01104         /* LP1 Status Register */
-#define LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
-#define LP1_CNT                     0xFFC0110C         /* LP1 Current Count Value of Clock Divider */
-#define LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
-#define LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
-#define LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
-#define LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
-#define LP2_CTL                     0xFFC01200         /* LP2 Control Register */
-#define LP2_STAT                    0xFFC01204         /* LP2 Status Register */
-#define LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
-#define LP2_CNT                     0xFFC0120C         /* LP2 Current Count Value of Clock Divider */
-#define LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
-#define LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
-#define LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
-#define LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
-#define LP3_CTL                     0xFFC01300         /* LP3 Control Register */
-#define LP3_STAT                    0xFFC01304         /* LP3 Status Register */
-#define LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
-#define LP3_CNT                     0xFFC0130C         /* LP3 Current Count Value of Clock Divider */
-#define LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
-#define LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
-#define LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
-#define LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
-        TIMER Registers
-   ========================= */
-#define TIMER_REVID                0xFFC01400         /* GPTIMER Timer IP Version ID */
-#define TIMER_RUN                  0xFFC01404         /* GPTIMER Timer Run Register */
-#define TIMER_RUN_SET              0xFFC01408         /* GPTIMER Run Register Alias to Set */
-#define TIMER_RUN_CLR              0xFFC0140C         /* GPTIMER Run Register Alias to Clear */
-#define TIMER_STOP_CFG             0xFFC01410         /* GPTIMER Stop Config Register */
-#define TIMER_STOP_CFG_SET         0xFFC01414         /* GPTIMER Stop Config Alias to Set */
-#define TIMER_STOP_CFG_CLR         0xFFC01418         /* GPTIMER Stop Config Alias to Clear */
-#define TIMER_DATA_IMSK            0xFFC0141C         /* GPTIMER Data Interrupt Mask register */
-#define TIMER_STAT_IMSK            0xFFC01420         /* GPTIMER Status Interrupt Mask register */
-#define TIMER_TRG_MSK              0xFFC01424         /* GPTIMER Output Trigger Mask register */
-#define TIMER_TRG_IE               0xFFC01428         /* GPTIMER Slave Trigger Enable register */
-#define TIMER_DATA_ILAT            0xFFC0142C         /* GPTIMER Data Interrupt Register */
-#define TIMER_STAT_ILAT            0xFFC01430         /* GPTIMER Status (Error) Interrupt Register */
-#define TIMER_ERR_TYPE             0xFFC01434         /* GPTIMER Register Indicating Type of Error */
-#define TIMER_BCAST_PER            0xFFC01438         /* GPTIMER Broadcast Period */
-#define TIMER_BCAST_WID            0xFFC0143C         /* GPTIMER Broadcast Width */
-#define TIMER_BCAST_DLY            0xFFC01440         /* GPTIMER Broadcast Delay */
-
-/* =========================
-	TIMER0~7
-   ========================= */
-#define TIMER0_CONFIG             0xFFC01460         /* TIMER0 Per Timer Config Register */
-#define TIMER0_COUNTER            0xFFC01464         /* TIMER0 Per Timer Counter Register */
-#define TIMER0_PERIOD             0xFFC01468         /* TIMER0 Per Timer Period Register */
-#define TIMER0_WIDTH              0xFFC0146C         /* TIMER0 Per Timer Width Register */
-#define TIMER0_DELAY              0xFFC01470         /* TIMER0 Per Timer Delay Register */
-
-#define TIMER1_CONFIG             0xFFC01480         /* TIMER1 Per Timer Config Register */
-#define TIMER1_COUNTER            0xFFC01484         /* TIMER1 Per Timer Counter Register */
-#define TIMER1_PERIOD             0xFFC01488         /* TIMER1 Per Timer Period Register */
-#define TIMER1_WIDTH              0xFFC0148C         /* TIMER1 Per Timer Width Register */
-#define TIMER1_DELAY              0xFFC01490         /* TIMER1 Per Timer Delay Register */
-
-#define TIMER2_CONFIG             0xFFC014A0         /* TIMER2 Per Timer Config Register */
-#define TIMER2_COUNTER            0xFFC014A4         /* TIMER2 Per Timer Counter Register */
-#define TIMER2_PERIOD             0xFFC014A8         /* TIMER2 Per Timer Period Register */
-#define TIMER2_WIDTH              0xFFC014AC         /* TIMER2 Per Timer Width Register */
-#define TIMER2_DELAY              0xFFC014B0         /* TIMER2 Per Timer Delay Register */
-
-#define TIMER3_CONFIG             0xFFC014C0         /* TIMER3 Per Timer Config Register */
-#define TIMER3_COUNTER            0xFFC014C4         /* TIMER3 Per Timer Counter Register */
-#define TIMER3_PERIOD             0xFFC014C8         /* TIMER3 Per Timer Period Register */
-#define TIMER3_WIDTH              0xFFC014CC         /* TIMER3 Per Timer Width Register */
-#define TIMER3_DELAY              0xFFC014D0         /* TIMER3 Per Timer Delay Register */
-
-#define TIMER4_CONFIG             0xFFC014E0         /* TIMER4 Per Timer Config Register */
-#define TIMER4_COUNTER            0xFFC014E4         /* TIMER4 Per Timer Counter Register */
-#define TIMER4_PERIOD             0xFFC014E8         /* TIMER4 Per Timer Period Register */
-#define TIMER4_WIDTH              0xFFC014EC         /* TIMER4 Per Timer Width Register */
-#define TIMER4_DELAY              0xFFC014F0         /* TIMER4 Per Timer Delay Register */
-
-#define TIMER5_CONFIG             0xFFC01500         /* TIMER5 Per Timer Config Register */
-#define TIMER5_COUNTER            0xFFC01504         /* TIMER5 Per Timer Counter Register */
-#define TIMER5_PERIOD             0xFFC01508         /* TIMER5 Per Timer Period Register */
-#define TIMER5_WIDTH              0xFFC0150C         /* TIMER5 Per Timer Width Register */
-#define TIMER5_DELAY              0xFFC01510         /* TIMER5 Per Timer Delay Register */
-
-#define TIMER6_CONFIG             0xFFC01520         /* TIMER6 Per Timer Config Register */
-#define TIMER6_COUNTER            0xFFC01524         /* TIMER6 Per Timer Counter Register */
-#define TIMER6_PERIOD             0xFFC01528         /* TIMER6 Per Timer Period Register */
-#define TIMER6_WIDTH              0xFFC0152C         /* TIMER6 Per Timer Width Register */
-#define TIMER6_DELAY              0xFFC01530         /* TIMER6 Per Timer Delay Register */
-
-#define TIMER7_CONFIG             0xFFC01540         /* TIMER7 Per Timer Config Register */
-#define TIMER7_COUNTER            0xFFC01544         /* TIMER7 Per Timer Counter Register */
-#define TIMER7_PERIOD             0xFFC01548         /* TIMER7 Per Timer Period Register */
-#define TIMER7_WIDTH              0xFFC0154C         /* TIMER7 Per Timer Width Register */
-#define TIMER7_DELAY              0xFFC01550         /* TIMER7 Per Timer Delay Register */
-
-/* =========================
-	CRC Registers
-   ========================= */
-
-/* =========================
-	CRC0
-   ========================= */
-#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
-#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 DATA Compare Register */
-#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 DATA FIFO Register */
-#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 DATA Count Capture Register */
-#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 Final CRC Result Register */
-#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 Current CRC Result Register */
-#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
-
-/* =========================
-	CRC1
-   ========================= */
-#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
-#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 DATA Compare Register */
-#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 DATA FIFO Register */
-#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 DATA Count Capture Register */
-#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 Final CRC Result Register */
-#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 Current CRC Result Register */
-#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
-
-/* =========================
-        TWI Registers
-   ========================= */
-
-/* =========================
-        TWI0
-   ========================= */
-#define TWI0_CLKDIV                    0xFFC01E00         /* TWI0 SCL Clock Divider */
-#define TWI0_CONTROL                   0xFFC01E04         /* TWI0 Control Register */
-#define TWI0_SLAVE_CTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
-#define TWI0_SLAVE_STAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
-#define TWI0_MASTER_CTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
-#define TWI0_MASTER_STAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
-#define TWI0_MASTER_ADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
-#define TWI0_INT_STAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
-#define TWI0_INT_MASK                  0xFFC01E24         /* TWI0 Interrupt Mask Register */
-#define TWI0_FIFO_CTL                  0xFFC01E28         /* TWI0 FIFO Control Register */
-#define TWI0_FIFO_STAT                 0xFFC01E2C         /* TWI0 FIFO Status Register */
-#define TWI0_XMT_DATA8                 0xFFC01E80         /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_XMT_DATA16                0xFFC01E84         /* TWI0 FIFO Transmit Data Double-Byte Register */
-#define TWI0_RCV_DATA8                 0xFFC01E88         /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_RCV_DATA16                0xFFC01E8C         /* TWI0 FIFO Transmit Data Double-Byte Register */
-
-/* =========================
-        TWI1
-   ========================= */
-#define TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider */
-#define TWI1_CONTROL                    0xFFC01F04         /* TWI1 Control Register */
-#define TWI1_SLAVE_CTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
-#define TWI1_SLAVE_STAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
-#define TWI1_MASTER_CTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
-#define TWI1_MASTER_STAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
-#define TWI1_MASTER_ADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
-#define TWI1_INT_STAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
-#define TWI1_INT_MASK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
-#define TWI1_FIFO_CTL                0xFFC01F28         /* TWI1 FIFO Control Register */
-#define TWI1_FIFO_STAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
-#define TWI1_XMT_DATA8                0xFFC01F80         /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_XMT_DATA16               0xFFC01F84         /* TWI1 FIFO Transmit Data Double-Byte Register */
-#define TWI1_RCV_DATA8                0xFFC01F88         /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_RCV_DATA16               0xFFC01F8C         /* TWI1 FIFO Transmit Data Double-Byte Register */
-
-
-/* =========================
-        UART Registers
-   ========================= */
-
-/* =========================
-        UART0
-   ========================= */
-#define UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
-#define UART0_CTL                   0xFFC02004         /* UART0 Control Register */
-#define UART0_STAT                  0xFFC02008         /* UART0 Status Register */
-#define UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
-#define UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
-#define UART0_IER                   0xFFC02014         /* UART0 Interrupt Mask Register */
-#define UART0_IER_SET               0xFFC02018         /* UART0 Interrupt Mask Set Register */
-#define UART0_IER_CLR               0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
-#define UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
-#define UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
-#define UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
-#define UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
-#define UART0_TXDIV                 0xFFC02034         /* UART0 Transmit Clock Devider Register */
-#define UART0_RXDIV                 0xFFC02038         /* UART0 Receive Clock Devider Register */
-
-/* =========================
-        UART1
-   ========================= */
-#define UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
-#define UART1_CTL                   0xFFC02404         /* UART1 Control Register */
-#define UART1_STAT                  0xFFC02408         /* UART1 Status Register */
-#define UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
-#define UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
-#define UART1_IER                   0xFFC02414         /* UART1 Interrupt Mask Register */
-#define UART1_IER_SET               0xFFC02418         /* UART1 Interrupt Mask Set Register */
-#define UART1_IER_CLR               0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
-#define UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
-#define UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
-#define UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
-#define UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
-#define UART1_TXDIV                 0xFFC02434         /* UART1 Transmit Clock Devider Register */
-#define UART1_RXDIV                 0xFFC02438         /* UART1 Receive Clock Devider Register */
-
-
-/* =========================
-        PORT Registers
-   ========================= */
-
-/* =========================
-        PORTA
-   ========================= */
-#define PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
-#define PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
-#define PORTA_FER_CLEAR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
-#define PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
-#define PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
-#define PORTA_DATA_CLEAR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
-#define PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
-#define PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
-#define PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
-#define PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
-#define PORTA_INEN_CLEAR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
-#define PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
-#define PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
-#define PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Programming Inversion Register */
-#define PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Programming Inversion Set Register */
-#define PORTA_POL_CLEAR               0xFFC03040         /* PORTA Port x GPIO Programming Inversion Clear Register */
-#define PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
-#define PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
-
-/* =========================
-        PORTB
-   ========================= */
-#define PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
-#define PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
-#define PORTB_FER_CLEAR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
-#define PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
-#define PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
-#define PORTB_DATA_CLEAR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
-#define PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
-#define PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
-#define PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
-#define PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
-#define PORTB_INEN_CLEAR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
-#define PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
-#define PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
-#define PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Programming Inversion Register */
-#define PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Programming Inversion Set Register */
-#define PORTB_POL_CLEAR               0xFFC030C0         /* PORTB Port x GPIO Programming Inversion Clear Register */
-#define PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
-#define PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
-
-/* =========================
-        PORTC
-   ========================= */
-#define PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
-#define PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
-#define PORTC_FER_CLEAR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
-#define PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
-#define PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
-#define PORTC_DATA_CLEAR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
-#define PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
-#define PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
-#define PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
-#define PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
-#define PORTC_INEN_CLEAR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
-#define PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
-#define PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
-#define PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Programming Inversion Register */
-#define PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Programming Inversion Set Register */
-#define PORTC_POL_CLEAR               0xFFC03140         /* PORTC Port x GPIO Programming Inversion Clear Register */
-#define PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
-#define PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
-
-/* =========================
-        PORTD
-   ========================= */
-#define PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
-#define PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
-#define PORTD_FER_CLEAR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
-#define PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
-#define PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
-#define PORTD_DATA_CLEAR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
-#define PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
-#define PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
-#define PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
-#define PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
-#define PORTD_INEN_CLEAR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
-#define PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
-#define PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
-#define PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Programming Inversion Register */
-#define PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Programming Inversion Set Register */
-#define PORTD_POL_CLEAR               0xFFC031C0         /* PORTD Port x GPIO Programming Inversion Clear Register */
-#define PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
-#define PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
-
-/* =========================
-        PORTE
-   ========================= */
-#define PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
-#define PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
-#define PORTE_FER_CLEAR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
-#define PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
-#define PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
-#define PORTE_DATA_CLEAR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
-#define PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
-#define PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
-#define PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
-#define PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
-#define PORTE_INEN_CLEAR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
-#define PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
-#define PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
-#define PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Programming Inversion Register */
-#define PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Programming Inversion Set Register */
-#define PORTE_POL_CLEAR               0xFFC03240         /* PORTE Port x GPIO Programming Inversion Clear Register */
-#define PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
-#define PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
-
-/* =========================
-        PORTF
-   ========================= */
-#define PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
-#define PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
-#define PORTF_FER_CLEAR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
-#define PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
-#define PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
-#define PORTF_DATA_CLEAR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
-#define PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
-#define PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
-#define PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
-#define PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
-#define PORTF_INEN_CLEAR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
-#define PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
-#define PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
-#define PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Programming Inversion Register */
-#define PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Programming Inversion Set Register */
-#define PORTF_POL_CLEAR               0xFFC032C0         /* PORTF Port x GPIO Programming Inversion Clear Register */
-#define PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
-#define PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
-
-/* =========================
-        PORTG
-   ========================= */
-#define PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
-#define PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
-#define PORTG_FER_CLEAR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
-#define PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
-#define PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
-#define PORTG_DATA_CLEAR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
-#define PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
-#define PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
-#define PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
-#define PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
-#define PORTG_INEN_CLEAR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
-#define PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
-#define PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
-#define PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Programming Inversion Register */
-#define PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Programming Inversion Set Register */
-#define PORTG_POL_CLEAR               0xFFC03340         /* PORTG Port x GPIO Programming Inversion Clear Register */
-#define PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
-#define PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
-
-/* ==================================================
-        Pads Controller Registers
-   ================================================== */
-
-/* =========================
-        PADS0
-   ========================= */
-#define PADS0_EMAC_PTP_CLKSEL	    0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
-#define PADS0_TWI_VSEL		    0xFFC03408         /* PADS0 TWI Voltage Selection */
-#define PADS0_PORTS_HYST	    0xFFC03440         /* PADS0 Hysteresis Enable Register */
-
-/* =========================
-        PINT Registers
-   ========================= */
-
-/* =========================
-        PINT0
-   ========================= */
-#define PINT0_MASK_SET              0xFFC04000         /* PINT0 Pint Mask Set Register */
-#define PINT0_MASK_CLEAR            0xFFC04004         /* PINT0 Pint Mask Clear Register */
-#define PINT0_REQUEST               0xFFC04008         /* PINT0 Pint Request Register */
-#define PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
-#define PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
-#define PINT0_EDGE_CLEAR            0xFFC04014         /* PINT0 Pint Edge Clear Register */
-#define PINT0_INVERT_SET            0xFFC04018         /* PINT0 Pint Invert Set Register */
-#define PINT0_INVERT_CLEAR          0xFFC0401C         /* PINT0 Pint Invert Clear Register */
-#define PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
-#define PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
-
-/* =========================
-        PINT1
-   ========================= */
-#define PINT1_MASK_SET              0xFFC04100         /* PINT1 Pint Mask Set Register */
-#define PINT1_MASK_CLEAR            0xFFC04104         /* PINT1 Pint Mask Clear Register */
-#define PINT1_REQUEST               0xFFC04108         /* PINT1 Pint Request Register */
-#define PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
-#define PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
-#define PINT1_EDGE_CLEAR            0xFFC04114         /* PINT1 Pint Edge Clear Register */
-#define PINT1_INVERT_SET            0xFFC04118         /* PINT1 Pint Invert Set Register */
-#define PINT1_INVERT_CLEAR          0xFFC0411C         /* PINT1 Pint Invert Clear Register */
-#define PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
-#define PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
-
-/* =========================
-        PINT2
-   ========================= */
-#define PINT2_MASK_SET              0xFFC04200         /* PINT2 Pint Mask Set Register */
-#define PINT2_MASK_CLEAR            0xFFC04204         /* PINT2 Pint Mask Clear Register */
-#define PINT2_REQUEST               0xFFC04208         /* PINT2 Pint Request Register */
-#define PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
-#define PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
-#define PINT2_EDGE_CLEAR            0xFFC04214         /* PINT2 Pint Edge Clear Register */
-#define PINT2_INVERT_SET            0xFFC04218         /* PINT2 Pint Invert Set Register */
-#define PINT2_INVERT_CLEAR          0xFFC0421C         /* PINT2 Pint Invert Clear Register */
-#define PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
-#define PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
-
-/* =========================
-        PINT3
-   ========================= */
-#define PINT3_MASK_SET              0xFFC04300         /* PINT3 Pint Mask Set Register */
-#define PINT3_MASK_CLEAR            0xFFC04304         /* PINT3 Pint Mask Clear Register */
-#define PINT3_REQUEST               0xFFC04308         /* PINT3 Pint Request Register */
-#define PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
-#define PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
-#define PINT3_EDGE_CLEAR            0xFFC04314         /* PINT3 Pint Edge Clear Register */
-#define PINT3_INVERT_SET            0xFFC04318         /* PINT3 Pint Invert Set Register */
-#define PINT3_INVERT_CLEAR          0xFFC0431C         /* PINT3 Pint Invert Clear Register */
-#define PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
-#define PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
-
-/* =========================
-        PINT4
-   ========================= */
-#define PINT4_MASK_SET              0xFFC04400         /* PINT4 Pint Mask Set Register */
-#define PINT4_MASK_CLEAR            0xFFC04404         /* PINT4 Pint Mask Clear Register */
-#define PINT4_REQUEST               0xFFC04408         /* PINT4 Pint Request Register */
-#define PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
-#define PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
-#define PINT4_EDGE_CLEAR            0xFFC04414         /* PINT4 Pint Edge Clear Register */
-#define PINT4_INVERT_SET            0xFFC04418         /* PINT4 Pint Invert Set Register */
-#define PINT4_INVERT_CLEAR          0xFFC0441C         /* PINT4 Pint Invert Clear Register */
-#define PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
-#define PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
-
-/* =========================
-        PINT5
-   ========================= */
-#define PINT5_MASK_SET              0xFFC04500         /* PINT5 Pint Mask Set Register */
-#define PINT5_MASK_CLEAR            0xFFC04504         /* PINT5 Pint Mask Clear Register */
-#define PINT5_REQUEST               0xFFC04508         /* PINT5 Pint Request Register */
-#define PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
-#define PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
-#define PINT5_EDGE_CLEAR            0xFFC04514         /* PINT5 Pint Edge Clear Register */
-#define PINT5_INVERT_SET            0xFFC04518         /* PINT5 Pint Invert Set Register */
-#define PINT5_INVERT_CLEAR          0xFFC0451C         /* PINT5 Pint Invert Clear Register */
-#define PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
-#define PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
-
-
-/* =========================
-        SMC Registers
-   ========================= */
-
-/* =========================
-        SMC0
-   ========================= */
-#define SMC_GCTL                   0xFFC16004         /* SMC0 SMC Control Register */
-#define SMC_GSTAT                  0xFFC16008         /* SMC0 SMC Status Register */
-#define SMC_B0CTL                  0xFFC1600C         /* SMC0 SMC Bank0 Control Register */
-#define SMC_B0TIM                  0xFFC16010         /* SMC0 SMC Bank0 Timing Register */
-#define SMC_B0ETIM                 0xFFC16014         /* SMC0 SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL                  0xFFC1601C         /* SMC0 SMC BANK1 Control Register */
-#define SMC_B1TIM                  0xFFC16020         /* SMC0 SMC BANK1 Timing Register */
-#define SMC_B1ETIM                 0xFFC16024         /* SMC0 SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL                  0xFFC1602C         /* SMC0 SMC BANK2 Control Register */
-#define SMC_B2TIM                  0xFFC16030         /* SMC0 SMC BANK2 Timing Register */
-#define SMC_B2ETIM                 0xFFC16034         /* SMC0 SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL                  0xFFC1603C         /* SMC0 SMC BANK3 Control Register */
-#define SMC_B3TIM                  0xFFC16040         /* SMC0 SMC BANK3 Timing Register */
-#define SMC_B3ETIM                 0xFFC16044         /* SMC0 SMC BANK3 Extended Timing Register */
-
-
-/* =========================
-        WDOG Registers
-   ========================= */
-
-/* =========================
-        WDOG0
-   ========================= */
-#define WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
-#define WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
-#define WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
-#define WDOG_CTL		WDOG0_CTL
-#define WDOG_CNT		WDOG0_CNT
-#define WDOG_STAT		WDOG0_STAT
-
-/* =========================
-        WDOG1
-   ========================= */
-#define WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
-#define WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
-#define WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================
-        SDU Registers
-   ========================= */
-
-/* =========================
-        SDU0
-   ========================= */
-#define SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
-#define SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
-#define SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
-#define SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
-#define SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
-#define SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
-#define SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
-#define SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
-#define SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
-#define SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
-#define SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
-#define SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
-
-
-/* =========================
-        EMAC Registers
-   ========================= */
-/* =========================
-        EMAC0
-   ========================= */
-#define EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
-#define EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 Filter Register for filtering Received Frames */
-#define EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Contains the Upper 32 bits of the hash table */
-#define EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Contains the lower 32 bits of the hash table */
-#define EMAC0_GMII_ADDR             0xFFC20010         /* EMAC0 Management Address Register */
-#define EMAC0_GMII_DATA             0xFFC20014         /* EMAC0 Management Data Register */
-#define EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 MAC FLow Control Register */
-#define EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
-#define EMAC0_VER                   0xFFC20020         /* EMAC0 EMAC Version Register */
-#define EMAC0_DBG                   0xFFC20024         /* EMAC0 EMAC Debug Register */
-#define EMAC0_RMTWKUP               0xFFC20028         /* EMAC0 Remote wake up frame register */
-#define EMAC0_PMT_CTLSTAT           0xFFC2002C         /* EMAC0 PMT Control and Status Register */
-#define EMAC0_ISTAT                 0xFFC20038         /* EMAC0 EMAC Interrupt Status Register */
-#define EMAC0_IMSK                  0xFFC2003C         /* EMAC0 EMAC Interrupt Mask Register */
-#define EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 EMAC Address0 High Register */
-#define EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 EMAC Address0 Low Register */
-#define EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
-#define EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC RX Interrupt Register */
-#define EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC TX Interrupt Register */
-#define EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC RX Interrupt Mask Register */
-#define EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
-#define EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Num bytes transmitted exclusive of preamble */
-#define EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Num frames transmitted exclusive of retired */
-#define EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Number of good broadcast frames transmitted. */
-#define EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Number of good multicast frames transmitted. */
-#define EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Number of 64 byte length frames */
-#define EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Number of good and bad unicast frames transmitted */
-#define EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Number of good and bad multicast frames transmitted */
-#define EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Number of good and bad broadcast frames transmitted */
-#define EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Number of frames aborted due to frame underflow error */
-#define EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Number of transmitted frames after single collision */
-#define EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Number of transmitted frames with more than one collision */
-#define EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Number of transmitted frames after deferral */
-#define EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Number of frames aborted due to late collision error */
-#define EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Number of aborted frames due to excessive collisions */
-#define EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Number of aborted frames due to carrier sense error */
-#define EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Number of bytes transmitted in good frames only */
-#define EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Number of good frames transmitted. */
-#define EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Number of frames aborted due to excessive deferral */
-#define EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Number of good PAUSE frames transmitted. */
-#define EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Number of VLAN frames transmitted */
-#define EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Number of good and bad frames received. */
-#define EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Number of bytes received in good and bad frames */
-#define EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Number of bytes received only in good frames */
-#define EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Number of good broadcast frames received. */
-#define EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Number of good multicast frames received */
-#define EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Number of frames received with CRC error */
-#define EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Number of frames with alignment error */
-#define EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Number of frames received with runt error. */
-#define EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Number of frames received with length greater than 1518 */
-#define EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Number of frames received with length 64 */
-#define EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Number of frames received with length greater than maxium */
-#define EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Number of good and bad frames of lengh 64 bytes */
-#define EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Number of good and bad frames received between 512-1023 */
-#define EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Number of frames received between 1024 and maxsize */
-#define EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Number of good unicast frames received. */
-#define EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Number of frames received with length error */
-#define EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Number of frames with length not equal to valid frame size */
-#define EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Number of good and valid PAUSE frames received. */
-#define EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Number of good and bad VLAN frames received. */
-#define EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Frames received with error due to watchdog timeout */
-#define EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC RX Interrupt Mask Register */
-#define EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC RX Interrupt Register */
-#define EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Number of good IPv4 datagrams */
-#define EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Number of IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Number of IPv4 datagrams without checksum */
-#define EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Number of good IPv4 datagrams with fragmentation */
-#define EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Number of IPv6 datagrams with header errors */
-#define EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Number of good IP datagrames with good UDP payload */
-#define EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Number of good IP datagrams with UDP checksum errors */
-#define EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Number of good IP datagrams with a good TCP payload */
-#define EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Number of good IP datagrams with TCP checksum errors */
-#define EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Number of good IP datagrams with a good ICMP payload */
-#define EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Bytes received in IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Bytes received in fragmented IPv4 datagrams */
-#define EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Bytes received in UDP segment with checksum disabled */
-#define EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Bytes received in good IPv6  including tcp,udp or icmp load */
-#define EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Number of bytes received in IPv6 with header errors */
-#define EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Number of bytes received in good UDP segments */
-#define EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Number of bytes received in UDP segment with checksum err */
-#define EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Number of bytes received in a good TCP segment */
-#define EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Number of bytes received in TCP segment with checksum err */
-#define EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Number of bytes received in a good ICMP segment */
-#define EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Bytes received in an ICMP segment with checksum errors */
-#define EMAC0_TM_CTL                0xFFC20700         /* EMAC0 EMAC Time Stamp Control Register */
-#define EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 EMAC Time Stamp Sub Second Increment */
-#define EMAC0_TM_SEC                0xFFC20708         /* EMAC0 EMAC Time Stamp Second Register */
-#define EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 EMAC Time Stamp Nano Second Register */
-#define EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 EMAC Time Stamp Seconds Update */
-#define EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 EMAC Time Stamp Nano Seconds Update */
-#define EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 EMAC Time Stamp Addend Register */
-#define EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 EMAC Time Stamp Target Time Sec. */
-#define EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 EMAC Time Stamp High Second Register */
-#define EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 EMAC Time Stamp Status Register */
-#define EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 EMAC PPS Control Register */
-#define EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 Bus Operating Modes for EMAC DMA */
-#define EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 TX DMA Poll demand register */
-#define EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 RX DMA Poll demand register */
-#define EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 RX Descriptor List Address */
-#define EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 TX Descriptor List Address */
-#define EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
-#define EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
-#define EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
-#define EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA missed frame and buffer overflow counter */
-#define EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA RX Interrupt Watch Dog timer */
-#define EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 AXI Bus Mode Register */
-#define EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 AXI Status Register */
-#define EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 TX current descriptor register */
-#define EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 RX current descriptor register */
-#define EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 TX current buffer pointer register */
-#define EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 RX current buffer pointer register */
-#define EMAC0_HWFEAT                0xFFC21058         /* EMAC0 Hardware Feature Register */
-
-/* =========================
-        EMAC1
-   ========================= */
-#define EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
-#define EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 Filter Register for filtering Received Frames */
-#define EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Contains the Upper 32 bits of the hash table */
-#define EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Contains the lower 32 bits of the hash table */
-#define EMAC1_GMII_ADDR             0xFFC22010         /* EMAC1 Management Address Register */
-#define EMAC1_GMII_DATA             0xFFC22014         /* EMAC1 Management Data Register */
-#define EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 MAC FLow Control Register */
-#define EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
-#define EMAC1_VER                   0xFFC22020         /* EMAC1 EMAC Version Register */
-#define EMAC1_DBG                   0xFFC22024         /* EMAC1 EMAC Debug Register */
-#define EMAC1_RMTWKUP               0xFFC22028         /* EMAC1 Remote wake up frame register */
-#define EMAC1_PMT_CTLSTAT           0xFFC2202C         /* EMAC1 PMT Control and Status Register */
-#define EMAC1_ISTAT                 0xFFC22038         /* EMAC1 EMAC Interrupt Status Register */
-#define EMAC1_IMSK                  0xFFC2203C         /* EMAC1 EMAC Interrupt Mask Register */
-#define EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 EMAC Address0 High Register */
-#define EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 EMAC Address0 Low Register */
-#define EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
-#define EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC RX Interrupt Register */
-#define EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC TX Interrupt Register */
-#define EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC RX Interrupt Mask Register */
-#define EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
-#define EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Num bytes transmitted exclusive of preamble */
-#define EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Num frames transmitted exclusive of retired */
-#define EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Number of good broadcast frames transmitted. */
-#define EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Number of good multicast frames transmitted. */
-#define EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Number of 64 byte length frames */
-#define EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Number of good and bad unicast frames transmitted */
-#define EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Number of good and bad multicast frames transmitted */
-#define EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Number of good and bad broadcast frames transmitted */
-#define EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Number of frames aborted due to frame underflow error */
-#define EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Number of transmitted frames after single collision */
-#define EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Number of transmitted frames with more than one collision */
-#define EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Number of transmitted frames after deferral */
-#define EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Number of frames aborted due to late collision error */
-#define EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Number of aborted frames due to excessive collisions */
-#define EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Number of aborted frames due to carrier sense error */
-#define EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Number of bytes transmitted in good frames only */
-#define EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Number of good frames transmitted. */
-#define EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Number of frames aborted due to excessive deferral */
-#define EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Number of good PAUSE frames transmitted. */
-#define EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Number of VLAN frames transmitted */
-#define EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Number of good and bad frames received. */
-#define EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Number of bytes received in good and bad frames */
-#define EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Number of bytes received only in good frames */
-#define EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Number of good broadcast frames received. */
-#define EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Number of good multicast frames received */
-#define EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Number of frames received with CRC error */
-#define EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Number of frames with alignment error */
-#define EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Number of frames received with runt error. */
-#define EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Number of frames received with length greater than 1518 */
-#define EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Number of frames received with length 64 */
-#define EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Number of frames received with length greater than maxium */
-#define EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Number of good and bad frames of lengh 64 bytes */
-#define EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Number of good and bad frames received between 512-1023 */
-#define EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Number of frames received between 1024 and maxsize */
-#define EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Number of good unicast frames received. */
-#define EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Number of frames received with length error */
-#define EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Number of frames with length not equal to valid frame size */
-#define EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Number of good and valid PAUSE frames received. */
-#define EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Number of good and bad VLAN frames received. */
-#define EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Frames received with error due to watchdog timeout */
-#define EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC RX Interrupt Mask Register */
-#define EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC RX Interrupt Register */
-#define EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Number of good IPv4 datagrams */
-#define EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Number of IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Number of IPv4 datagrams without checksum */
-#define EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Number of good IPv4 datagrams with fragmentation */
-#define EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Number of IPv6 datagrams with header errors */
-#define EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Number of good IP datagrames with good UDP payload */
-#define EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Number of good IP datagrams with UDP checksum errors */
-#define EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Number of good IP datagrams with a good TCP payload */
-#define EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Number of good IP datagrams with TCP checksum errors */
-#define EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Number of good IP datagrams with a good ICMP payload */
-#define EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Bytes received in IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Bytes received in fragmented IPv4 datagrams */
-#define EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Bytes received in UDP segment with checksum disabled */
-#define EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Bytes received in good IPv6  including tcp,udp or icmp load */
-#define EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Number of bytes received in IPv6 with header errors */
-#define EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Number of bytes received in good UDP segments */
-#define EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Number of bytes received in UDP segment with checksum err */
-#define EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Number of bytes received in a good TCP segment */
-#define EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Number of bytes received in TCP segment with checksum err */
-#define EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Number of bytes received in a good ICMP segment */
-#define EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Bytes received in an ICMP segment with checksum errors */
-#define EMAC1_TM_CTL                0xFFC22700         /* EMAC1 EMAC Time Stamp Control Register */
-#define EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 EMAC Time Stamp Sub Second Increment */
-#define EMAC1_TM_SEC                0xFFC22708         /* EMAC1 EMAC Time Stamp Second Register */
-#define EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 EMAC Time Stamp Nano Second Register */
-#define EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 EMAC Time Stamp Seconds Update */
-#define EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 EMAC Time Stamp Nano Seconds Update */
-#define EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 EMAC Time Stamp Addend Register */
-#define EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 EMAC Time Stamp Target Time Sec. */
-#define EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 EMAC Time Stamp High Second Register */
-#define EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 EMAC Time Stamp Status Register */
-#define EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 EMAC PPS Control Register */
-#define EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 Bus Operating Modes for EMAC DMA */
-#define EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 TX DMA Poll demand register */
-#define EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 RX DMA Poll demand register */
-#define EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 RX Descriptor List Address */
-#define EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 TX Descriptor List Address */
-#define EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
-#define EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
-#define EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
-#define EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA missed frame and buffer overflow counter */
-#define EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA RX Interrupt Watch Dog timer */
-#define EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 AXI Bus Mode Register */
-#define EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 AXI Status Register */
-#define EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 TX current descriptor register */
-#define EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 RX current descriptor register */
-#define EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 TX current buffer pointer register */
-#define EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 RX current buffer pointer register */
-#define EMAC1_HWFEAT                0xFFC23058         /* EMAC1 Hardware Feature Register */
-
-
-/* =========================
-        SPI Registers
-   ========================= */
-
-/* =========================
-        SPI0
-   ========================= */
-#define SPI0_REGBASE                0xFFC40400
-#define SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
-#define SPI0_RXCTL                  0xFFC40408         /* SPI0 RX Control Register */
-#define SPI0_TXCTL                  0xFFC4040C         /* SPI0 TX Control Register */
-#define SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
-#define SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
-#define SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
-#define SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word-Count Register */
-#define SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word-Count Reload Register */
-#define SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word-Count Register */
-#define SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word-Count Reload Register */
-#define SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
-#define SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
-#define SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
-#define SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
-#define SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
-#define SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
-#define SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
-#define SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
-        SPI1
-   ========================= */
-#define SPI1_REGBASE                0xFFC40500
-#define SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
-#define SPI1_RXCTL                  0xFFC40508         /* SPI1 RX Control Register */
-#define SPI1_TXCTL                  0xFFC4050C         /* SPI1 TX Control Register */
-#define SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
-#define SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
-#define SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
-#define SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word-Count Register */
-#define SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word-Count Reload Register */
-#define SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word-Count Register */
-#define SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word-Count Reload Register */
-#define SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
-#define SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
-#define SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
-#define SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
-#define SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
-#define SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
-#define SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
-#define SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
-	SPORT Registers
-   ========================= */
-
-/* =========================
-	SPORT0
-   ========================= */
-#define SPORT0_CTL_A                0xFFC40000         /* SPORT0 'A' Control Register */
-#define SPORT0_DIV_A                0xFFC40004         /* SPORT0 'A' Clock and FS Divide Register */
-#define SPORT0_MCTL_A               0xFFC40008         /* SPORT0 'A' Multichannel Control Register */
-#define SPORT0_CS0_A                0xFFC4000C         /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_A                0xFFC40010         /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_A                0xFFC40014         /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_A                0xFFC40018         /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_A                0xFFC4001C         /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_A                0xFFC40020         /* SPORT0 'A' Error Register */
-#define SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 'A' Multichannel Mode Status Register */
-#define SPORT0_CTL2_A               0xFFC40028         /* SPORT0 'A' Control Register 2 */
-#define SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 'A' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 'A' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 'A' Secondary Channel Receive Buffer Register */
-#define SPORT0_CTL_B                0xFFC40080         /* SPORT0 'B' Control Register */
-#define SPORT0_DIV_B                0xFFC40084         /* SPORT0 'B' Clock and FS Divide Register */
-#define SPORT0_MCTL_B               0xFFC40088         /* SPORT0 'B' Multichannel Control Register */
-#define SPORT0_CS0_B                0xFFC4008C         /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_B                0xFFC40090         /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_B                0xFFC40094         /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_B                0xFFC40098         /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_B                0xFFC4009C         /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_B                0xFFC400A0         /* SPORT0 'B' Error Register */
-#define SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 'B' Multichannel Mode Status Register */
-#define SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 'B' Control Register 2 */
-#define SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 'B' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 'B' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
-	SPORT1
-   ========================= */
-#define SPORT1_CTL_A                0xFFC40100         /* SPORT1 'A' Control Register */
-#define SPORT1_DIV_A                0xFFC40104         /* SPORT1 'A' Clock and FS Divide Register */
-#define SPORT1_MCTL_A               0xFFC40108         /* SPORT1 'A' Multichannel Control Register */
-#define SPORT1_CS0_A                0xFFC4010C         /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_A                0xFFC40110         /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_A                0xFFC40114         /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_A                0xFFC40118         /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_A                0xFFC4011C         /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_A                0xFFC40120         /* SPORT1 'A' Error Register */
-#define SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 'A' Multichannel Mode Status Register */
-#define SPORT1_CTL2_A               0xFFC40128         /* SPORT1 'A' Control Register 2 */
-#define SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 'A' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 'A' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 'A' Secondary Channel Receive Buffer Register */
-#define SPORT1_CTL_B                0xFFC40180         /* SPORT1 'B' Control Register */
-#define SPORT1_DIV_B                0xFFC40184         /* SPORT1 'B' Clock and FS Divide Register */
-#define SPORT1_MCTL_B               0xFFC40188         /* SPORT1 'B' Multichannel Control Register */
-#define SPORT1_CS0_B                0xFFC4018C         /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_B                0xFFC40190         /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_B                0xFFC40194         /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_B                0xFFC40198         /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_B                0xFFC4019C         /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_B                0xFFC401A0         /* SPORT1 'B' Error Register */
-#define SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 'B' Multichannel Mode Status Register */
-#define SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 'B' Control Register 2 */
-#define SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 'B' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 'B' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
-	SPORT2
-   ========================= */
-#define SPORT2_CTL_A                0xFFC40200         /* SPORT2 'A' Control Register */
-#define SPORT2_DIV_A                0xFFC40204         /* SPORT2 'A' Clock and FS Divide Register */
-#define SPORT2_MCTL_A               0xFFC40208         /* SPORT2 'A' Multichannel Control Register */
-#define SPORT2_CS0_A                0xFFC4020C         /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_A                0xFFC40210         /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_A                0xFFC40214         /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_A                0xFFC40218         /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_A                0xFFC4021C         /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_A                0xFFC40220         /* SPORT2 'A' Error Register */
-#define SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 'A' Multichannel Mode Status Register */
-#define SPORT2_CTL2_A               0xFFC40228         /* SPORT2 'A' Control Register 2 */
-#define SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 'A' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 'A' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 'A' Secondary Channel Receive Buffer Register */
-#define SPORT2_CTL_B                0xFFC40280         /* SPORT2 'B' Control Register */
-#define SPORT2_DIV_B                0xFFC40284         /* SPORT2 'B' Clock and FS Divide Register */
-#define SPORT2_MCTL_B               0xFFC40288         /* SPORT2 'B' Multichannel Control Register */
-#define SPORT2_CS0_B                0xFFC4028C         /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_B                0xFFC40290         /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_B                0xFFC40294         /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_B                0xFFC40298         /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_B                0xFFC4029C         /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_B                0xFFC402A0         /* SPORT2 'B' Error Register */
-#define SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 'B' Multichannel Mode Status Register */
-#define SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 'B' Control Register 2 */
-#define SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 'B' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 'B' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
-	EPPI Registers
-   ========================= */
-
-/* =========================
-	EPPI0
-   ========================= */
-#define EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
-#define EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
-#define EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
-#define EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
-#define EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
-#define EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
-#define EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
-#define EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
-#define EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
-
-/* =========================
-	EPPI1
-   ========================= */
-#define EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
-#define EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
-#define EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
-#define EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
-#define EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
-#define EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
-#define EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
-#define EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
-#define EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
-
-/* =========================
-	EPPI2
-   ========================= */
-#define EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
-#define EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
-#define EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
-#define EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
-#define EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
-#define EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
-#define EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
-#define EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
-#define EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
-
-
-
-/* =========================
-        DDE Registers
-   ========================= */
-
-/* =========================
-        DMA0
-   ========================= */
-#define DMA0_NEXT_DESC_PTR          0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
-#define DMA0_START_ADDR             0xFFC41004         /* DMA0 Start Address of Current Buffer */
-#define DMA0_CONFIG                 0xFFC41008         /* DMA0 Configuration Register */
-#define DMA0_X_COUNT                0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
-#define DMA0_X_MODIFY               0xFFC41010         /* DMA0 Inner Loop Address Increment */
-#define DMA0_Y_COUNT                0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
-#define DMA0_Y_MODIFY               0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
-#define DMA0_CURR_DESC_PTR          0xFFC41024         /* DMA0 Current Descriptor Pointer */
-#define DMA0_PREV_DESC_PTR          0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
-#define DMA0_CURR_ADDR              0xFFC4102C         /* DMA0 Current Address */
-#define DMA0_IRQ_STATUS             0xFFC41030         /* DMA0 Status Register */
-#define DMA0_CURR_X_COUNT           0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA0_CURR_Y_COUNT           0xFFC41038         /* DMA0 Current Row Count (2D only) */
-#define DMA0_BWL_COUNT              0xFFC41040         /* DMA0 Bandwidth Limit Count */
-#define DMA0_CURR_BWL_COUNT         0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
-#define DMA0_BWM_COUNT              0xFFC41048         /* DMA0 Bandwidth Monitor Count */
-#define DMA0_CURR_BWM_COUNT         0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA1
-   ========================= */
-#define DMA1_NEXT_DESC_PTR             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
-#define DMA1_START_ADDR              0xFFC41084         /* DMA1 Start Address of Current Buffer */
-#define DMA1_CONFIG                    0xFFC41088         /* DMA1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
-#define DMA1_X_MODIFY                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
-#define DMA1_Y_COUNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
-#define DMA1_Y_MODIFY                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
-#define DMA1_CURR_DESC_PTR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
-#define DMA1_PREV_DESC_PTR             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
-#define DMA1_CURR_ADDR               0xFFC410AC         /* DMA1 Current Address */
-#define DMA1_IRQ_STATUS                   0xFFC410B0         /* DMA1 Status Register */
-#define DMA1_CURR_X_COUNT               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA1_CURR_Y_COUNT               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
-#define DMA1_BWL_COUNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
-#define DMA1_CURR_BWL_COUNT             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
-#define DMA1_BWM_COUNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
-#define DMA1_CURR_BWM_COUNT             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA2
-   ========================= */
-#define DMA2_NEXT_DESC_PTR             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
-#define DMA2_START_ADDR              0xFFC41104         /* DMA2 Start Address of Current Buffer */
-#define DMA2_CONFIG                    0xFFC41108         /* DMA2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
-#define DMA2_X_MODIFY                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
-#define DMA2_Y_COUNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
-#define DMA2_Y_MODIFY                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
-#define DMA2_CURR_DESC_PTR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
-#define DMA2_PREV_DESC_PTR             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
-#define DMA2_CURR_ADDR               0xFFC4112C         /* DMA2 Current Address */
-#define DMA2_IRQ_STATUS                   0xFFC41130         /* DMA2 Status Register */
-#define DMA2_CURR_X_COUNT               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA2_CURR_Y_COUNT               0xFFC41138         /* DMA2 Current Row Count (2D only) */
-#define DMA2_BWL_COUNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
-#define DMA2_CURR_BWL_COUNT             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
-#define DMA2_BWM_COUNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
-#define DMA2_CURR_BWM_COUNT             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA3
-   ========================= */
-#define DMA3_NEXT_DESC_PTR             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
-#define DMA3_START_ADDR              0xFFC41184         /* DMA3 Start Address of Current Buffer */
-#define DMA3_CONFIG                    0xFFC41188         /* DMA3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
-#define DMA3_X_MODIFY                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
-#define DMA3_Y_COUNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
-#define DMA3_Y_MODIFY                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
-#define DMA3_CURR_DESC_PTR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
-#define DMA3_PREV_DESC_PTR             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
-#define DMA3_CURR_ADDR               0xFFC411AC         /* DMA3 Current Address */
-#define DMA3_IRQ_STATUS                   0xFFC411B0         /* DMA3 Status Register */
-#define DMA3_CURR_X_COUNT               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA3_CURR_Y_COUNT               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
-#define DMA3_BWL_COUNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
-#define DMA3_CURR_BWL_COUNT             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
-#define DMA3_BWM_COUNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
-#define DMA3_CURR_BWM_COUNT             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA4
-   ========================= */
-#define DMA4_NEXT_DESC_PTR             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
-#define DMA4_START_ADDR              0xFFC41204         /* DMA4 Start Address of Current Buffer */
-#define DMA4_CONFIG                    0xFFC41208         /* DMA4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
-#define DMA4_X_MODIFY                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
-#define DMA4_Y_COUNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
-#define DMA4_Y_MODIFY                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
-#define DMA4_CURR_DESC_PTR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
-#define DMA4_PREV_DESC_PTR             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
-#define DMA4_CURR_ADDR               0xFFC4122C         /* DMA4 Current Address */
-#define DMA4_IRQ_STATUS                   0xFFC41230         /* DMA4 Status Register */
-#define DMA4_CURR_X_COUNT               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA4_CURR_Y_COUNT               0xFFC41238         /* DMA4 Current Row Count (2D only) */
-#define DMA4_BWL_COUNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
-#define DMA4_CURR_BWL_COUNT             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
-#define DMA4_BWM_COUNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
-#define DMA4_CURR_BWM_COUNT             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA5
-   ========================= */
-#define DMA5_NEXT_DESC_PTR             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
-#define DMA5_START_ADDR              0xFFC41284         /* DMA5 Start Address of Current Buffer */
-#define DMA5_CONFIG                    0xFFC41288         /* DMA5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
-#define DMA5_X_MODIFY                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
-#define DMA5_Y_COUNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
-#define DMA5_Y_MODIFY                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
-#define DMA5_CURR_DESC_PTR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
-#define DMA5_PREV_DESC_PTR             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
-#define DMA5_CURR_ADDR               0xFFC412AC         /* DMA5 Current Address */
-#define DMA5_IRQ_STATUS                   0xFFC412B0         /* DMA5 Status Register */
-#define DMA5_CURR_X_COUNT               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA5_CURR_Y_COUNT               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
-#define DMA5_BWL_COUNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
-#define DMA5_CURR_BWL_COUNT             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
-#define DMA5_BWM_COUNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
-#define DMA5_CURR_BWM_COUNT             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA6
-   ========================= */
-#define DMA6_NEXT_DESC_PTR             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
-#define DMA6_START_ADDR              0xFFC41304         /* DMA6 Start Address of Current Buffer */
-#define DMA6_CONFIG                    0xFFC41308         /* DMA6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
-#define DMA6_X_MODIFY                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
-#define DMA6_Y_COUNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
-#define DMA6_Y_MODIFY                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
-#define DMA6_CURR_DESC_PTR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
-#define DMA6_PREV_DESC_PTR             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
-#define DMA6_CURR_ADDR               0xFFC4132C         /* DMA6 Current Address */
-#define DMA6_IRQ_STATUS                   0xFFC41330         /* DMA6 Status Register */
-#define DMA6_CURR_X_COUNT               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA6_CURR_Y_COUNT               0xFFC41338         /* DMA6 Current Row Count (2D only) */
-#define DMA6_BWL_COUNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
-#define DMA6_CURR_BWL_COUNT             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
-#define DMA6_BWM_COUNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
-#define DMA6_CURR_BWM_COUNT             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA7
-   ========================= */
-#define DMA7_NEXT_DESC_PTR             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
-#define DMA7_START_ADDR              0xFFC41384         /* DMA7 Start Address of Current Buffer */
-#define DMA7_CONFIG                    0xFFC41388         /* DMA7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
-#define DMA7_X_MODIFY                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
-#define DMA7_Y_COUNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
-#define DMA7_Y_MODIFY                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
-#define DMA7_CURR_DESC_PTR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
-#define DMA7_PREV_DESC_PTR             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
-#define DMA7_CURR_ADDR               0xFFC413AC         /* DMA7 Current Address */
-#define DMA7_IRQ_STATUS                   0xFFC413B0         /* DMA7 Status Register */
-#define DMA7_CURR_X_COUNT               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA7_CURR_Y_COUNT               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
-#define DMA7_BWL_COUNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
-#define DMA7_CURR_BWL_COUNT             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
-#define DMA7_BWM_COUNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
-#define DMA7_CURR_BWM_COUNT             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA8
-   ========================= */
-#define DMA8_NEXT_DESC_PTR             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
-#define DMA8_START_ADDR              0xFFC41404         /* DMA8 Start Address of Current Buffer */
-#define DMA8_CONFIG                    0xFFC41408         /* DMA8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
-#define DMA8_X_MODIFY                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
-#define DMA8_Y_COUNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
-#define DMA8_Y_MODIFY                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
-#define DMA8_CURR_DESC_PTR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
-#define DMA8_PREV_DESC_PTR             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
-#define DMA8_CURR_ADDR               0xFFC4142C         /* DMA8 Current Address */
-#define DMA8_IRQ_STATUS                   0xFFC41430         /* DMA8 Status Register */
-#define DMA8_CURR_X_COUNT               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA8_CURR_Y_COUNT               0xFFC41438         /* DMA8 Current Row Count (2D only) */
-#define DMA8_BWL_COUNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
-#define DMA8_CURR_BWL_COUNT             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
-#define DMA8_BWM_COUNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
-#define DMA8_CURR_BWM_COUNT             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA9
-   ========================= */
-#define DMA9_NEXT_DESC_PTR             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
-#define DMA9_START_ADDR              0xFFC41484         /* DMA9 Start Address of Current Buffer */
-#define DMA9_CONFIG                    0xFFC41488         /* DMA9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
-#define DMA9_X_MODIFY                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
-#define DMA9_Y_COUNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
-#define DMA9_Y_MODIFY                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
-#define DMA9_CURR_DESC_PTR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
-#define DMA9_PREV_DESC_PTR             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
-#define DMA9_CURR_ADDR               0xFFC414AC         /* DMA9 Current Address */
-#define DMA9_IRQ_STATUS                   0xFFC414B0         /* DMA9 Status Register */
-#define DMA9_CURR_X_COUNT               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA9_CURR_Y_COUNT               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
-#define DMA9_BWL_COUNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
-#define DMA9_CURR_BWL_COUNT             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
-#define DMA9_BWM_COUNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
-#define DMA9_CURR_BWM_COUNT             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA10
-   ========================= */
-#define DMA10_NEXT_DESC_PTR            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
-#define DMA10_START_ADDR             0xFFC05004         /* DMA10 Start Address of Current Buffer */
-#define DMA10_CONFIG                   0xFFC05008         /* DMA10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
-#define DMA10_X_MODIFY                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
-#define DMA10_Y_COUNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
-#define DMA10_Y_MODIFY                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
-#define DMA10_CURR_DESC_PTR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
-#define DMA10_PREV_DESC_PTR            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
-#define DMA10_CURR_ADDR              0xFFC0502C         /* DMA10 Current Address */
-#define DMA10_IRQ_STATUS                  0xFFC05030         /* DMA10 Status Register */
-#define DMA10_CURR_X_COUNT              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA10_CURR_Y_COUNT              0xFFC05038         /* DMA10 Current Row Count (2D only) */
-#define DMA10_BWL_COUNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
-#define DMA10_CURR_BWL_COUNT            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWM_COUNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
-#define DMA10_CURR_BWM_COUNT            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA11
-   ========================= */
-#define DMA11_NEXT_DESC_PTR            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
-#define DMA11_START_ADDR             0xFFC05084         /* DMA11 Start Address of Current Buffer */
-#define DMA11_CONFIG                   0xFFC05088         /* DMA11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
-#define DMA11_X_MODIFY                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
-#define DMA11_Y_COUNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
-#define DMA11_Y_MODIFY                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
-#define DMA11_CURR_DESC_PTR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
-#define DMA11_PREV_DESC_PTR            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
-#define DMA11_CURR_ADDR              0xFFC050AC         /* DMA11 Current Address */
-#define DMA11_IRQ_STATUS                  0xFFC050B0         /* DMA11 Status Register */
-#define DMA11_CURR_X_COUNT              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA11_CURR_Y_COUNT              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
-#define DMA11_BWL_COUNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
-#define DMA11_CURR_BWL_COUNT            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
-#define DMA11_BWM_COUNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
-#define DMA11_CURR_BWM_COUNT            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA12
-   ========================= */
-#define DMA12_NEXT_DESC_PTR            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
-#define DMA12_START_ADDR             0xFFC05104         /* DMA12 Start Address of Current Buffer */
-#define DMA12_CONFIG                   0xFFC05108         /* DMA12 Configuration Register */
-#define DMA12_X_COUNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
-#define DMA12_X_MODIFY                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
-#define DMA12_Y_COUNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
-#define DMA12_Y_MODIFY                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
-#define DMA12_CURR_DESC_PTR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
-#define DMA12_PREV_DESC_PTR            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
-#define DMA12_CURR_ADDR              0xFFC0512C         /* DMA12 Current Address */
-#define DMA12_IRQ_STATUS                  0xFFC05130         /* DMA12 Status Register */
-#define DMA12_CURR_X_COUNT              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA12_CURR_Y_COUNT              0xFFC05138         /* DMA12 Current Row Count (2D only) */
-#define DMA12_BWL_COUNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
-#define DMA12_CURR_BWL_COUNT            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
-#define DMA12_BWM_COUNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
-#define DMA12_CURR_BWM_COUNT            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA13
-   ========================= */
-#define DMA13_NEXT_DESC_PTR            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
-#define DMA13_START_ADDR             0xFFC07004         /* DMA13 Start Address of Current Buffer */
-#define DMA13_CONFIG                   0xFFC07008         /* DMA13 Configuration Register */
-#define DMA13_X_COUNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
-#define DMA13_X_MODIFY                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
-#define DMA13_Y_COUNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
-#define DMA13_Y_MODIFY                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
-#define DMA13_CURR_DESC_PTR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
-#define DMA13_PREV_DESC_PTR            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
-#define DMA13_CURR_ADDR              0xFFC0702C         /* DMA13 Current Address */
-#define DMA13_IRQ_STATUS                  0xFFC07030         /* DMA13 Status Register */
-#define DMA13_CURR_X_COUNT              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA13_CURR_Y_COUNT              0xFFC07038         /* DMA13 Current Row Count (2D only) */
-#define DMA13_BWL_COUNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
-#define DMA13_CURR_BWL_COUNT            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
-#define DMA13_BWM_COUNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
-#define DMA13_CURR_BWM_COUNT            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA14
-   ========================= */
-#define DMA14_NEXT_DESC_PTR            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
-#define DMA14_START_ADDR             0xFFC07084         /* DMA14 Start Address of Current Buffer */
-#define DMA14_CONFIG                   0xFFC07088         /* DMA14 Configuration Register */
-#define DMA14_X_COUNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
-#define DMA14_X_MODIFY                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
-#define DMA14_Y_COUNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
-#define DMA14_Y_MODIFY                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
-#define DMA14_CURR_DESC_PTR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
-#define DMA14_PREV_DESC_PTR            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
-#define DMA14_CURR_ADDR              0xFFC070AC         /* DMA14 Current Address */
-#define DMA14_IRQ_STATUS                  0xFFC070B0         /* DMA14 Status Register */
-#define DMA14_CURR_X_COUNT              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA14_CURR_Y_COUNT              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
-#define DMA14_BWL_COUNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
-#define DMA14_CURR_BWL_COUNT            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
-#define DMA14_BWM_COUNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
-#define DMA14_CURR_BWM_COUNT            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA15
-   ========================= */
-#define DMA15_NEXT_DESC_PTR            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
-#define DMA15_START_ADDR             0xFFC07104         /* DMA15 Start Address of Current Buffer */
-#define DMA15_CONFIG                   0xFFC07108         /* DMA15 Configuration Register */
-#define DMA15_X_COUNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
-#define DMA15_X_MODIFY                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
-#define DMA15_Y_COUNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
-#define DMA15_Y_MODIFY                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
-#define DMA15_CURR_DESC_PTR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
-#define DMA15_PREV_DESC_PTR            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
-#define DMA15_CURR_ADDR              0xFFC0712C         /* DMA15 Current Address */
-#define DMA15_IRQ_STATUS                  0xFFC07130         /* DMA15 Status Register */
-#define DMA15_CURR_X_COUNT              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA15_CURR_Y_COUNT              0xFFC07138         /* DMA15 Current Row Count (2D only) */
-#define DMA15_BWL_COUNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
-#define DMA15_CURR_BWL_COUNT            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
-#define DMA15_BWM_COUNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
-#define DMA15_CURR_BWM_COUNT            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA16
-   ========================= */
-#define DMA16_NEXT_DESC_PTR            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
-#define DMA16_START_ADDR             0xFFC07184         /* DMA16 Start Address of Current Buffer */
-#define DMA16_CONFIG                   0xFFC07188         /* DMA16 Configuration Register */
-#define DMA16_X_COUNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
-#define DMA16_X_MODIFY                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
-#define DMA16_Y_COUNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
-#define DMA16_Y_MODIFY                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
-#define DMA16_CURR_DESC_PTR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
-#define DMA16_PREV_DESC_PTR            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
-#define DMA16_CURR_ADDR              0xFFC071AC         /* DMA16 Current Address */
-#define DMA16_IRQ_STATUS                  0xFFC071B0         /* DMA16 Status Register */
-#define DMA16_CURR_X_COUNT              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA16_CURR_Y_COUNT              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
-#define DMA16_BWL_COUNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
-#define DMA16_CURR_BWL_COUNT            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
-#define DMA16_BWM_COUNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
-#define DMA16_CURR_BWM_COUNT            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA17
-   ========================= */
-#define DMA17_NEXT_DESC_PTR            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
-#define DMA17_START_ADDR             0xFFC07204         /* DMA17 Start Address of Current Buffer */
-#define DMA17_CONFIG                   0xFFC07208         /* DMA17 Configuration Register */
-#define DMA17_X_COUNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
-#define DMA17_X_MODIFY                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
-#define DMA17_Y_COUNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
-#define DMA17_Y_MODIFY                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
-#define DMA17_CURR_DESC_PTR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
-#define DMA17_PREV_DESC_PTR            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
-#define DMA17_CURR_ADDR              0xFFC0722C         /* DMA17 Current Address */
-#define DMA17_IRQ_STATUS                  0xFFC07230         /* DMA17 Status Register */
-#define DMA17_CURR_X_COUNT              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA17_CURR_Y_COUNT              0xFFC07238         /* DMA17 Current Row Count (2D only) */
-#define DMA17_BWL_COUNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
-#define DMA17_CURR_BWL_COUNT            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
-#define DMA17_BWM_COUNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
-#define DMA17_CURR_BWM_COUNT            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA18
-   ========================= */
-#define DMA18_NEXT_DESC_PTR            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
-#define DMA18_START_ADDR             0xFFC07284         /* DMA18 Start Address of Current Buffer */
-#define DMA18_CONFIG                   0xFFC07288         /* DMA18 Configuration Register */
-#define DMA18_X_COUNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
-#define DMA18_X_MODIFY                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
-#define DMA18_Y_COUNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
-#define DMA18_Y_MODIFY                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
-#define DMA18_CURR_DESC_PTR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
-#define DMA18_PREV_DESC_PTR            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
-#define DMA18_CURR_ADDR              0xFFC072AC         /* DMA18 Current Address */
-#define DMA18_IRQ_STATUS                  0xFFC072B0         /* DMA18 Status Register */
-#define DMA18_CURR_X_COUNT              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA18_CURR_Y_COUNT              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
-#define DMA18_BWL_COUNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
-#define DMA18_CURR_BWL_COUNT            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
-#define DMA18_BWM_COUNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
-#define DMA18_CURR_BWM_COUNT            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA19
-   ========================= */
-#define DMA19_NEXT_DESC_PTR            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
-#define DMA19_START_ADDR             0xFFC07304         /* DMA19 Start Address of Current Buffer */
-#define DMA19_CONFIG                   0xFFC07308         /* DMA19 Configuration Register */
-#define DMA19_X_COUNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
-#define DMA19_X_MODIFY                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
-#define DMA19_Y_COUNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
-#define DMA19_Y_MODIFY                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
-#define DMA19_CURR_DESC_PTR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
-#define DMA19_PREV_DESC_PTR            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
-#define DMA19_CURR_ADDR              0xFFC0732C         /* DMA19 Current Address */
-#define DMA19_IRQ_STATUS                  0xFFC07330         /* DMA19 Status Register */
-#define DMA19_CURR_X_COUNT              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA19_CURR_Y_COUNT              0xFFC07338         /* DMA19 Current Row Count (2D only) */
-#define DMA19_BWL_COUNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
-#define DMA19_CURR_BWL_COUNT            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
-#define DMA19_BWM_COUNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
-#define DMA19_CURR_BWM_COUNT            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA20
-   ========================= */
-#define DMA20_NEXT_DESC_PTR            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
-#define DMA20_START_ADDR             0xFFC07384         /* DMA20 Start Address of Current Buffer */
-#define DMA20_CONFIG                   0xFFC07388         /* DMA20 Configuration Register */
-#define DMA20_X_COUNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
-#define DMA20_X_MODIFY                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
-#define DMA20_Y_COUNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
-#define DMA20_Y_MODIFY                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
-#define DMA20_CURR_DESC_PTR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
-#define DMA20_PREV_DESC_PTR            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
-#define DMA20_CURR_ADDR              0xFFC073AC         /* DMA20 Current Address */
-#define DMA20_IRQ_STATUS                  0xFFC073B0         /* DMA20 Status Register */
-#define DMA20_CURR_X_COUNT              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA20_CURR_Y_COUNT              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
-#define DMA20_BWL_COUNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
-#define DMA20_CURR_BWL_COUNT            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
-#define DMA20_BWM_COUNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
-#define DMA20_CURR_BWM_COUNT            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA21
-   ========================= */
-#define DMA21_NEXT_DESC_PTR            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
-#define DMA21_START_ADDR             0xFFC09004         /* DMA21 Start Address of Current Buffer */
-#define DMA21_CONFIG                   0xFFC09008         /* DMA21 Configuration Register */
-#define DMA21_X_COUNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
-#define DMA21_X_MODIFY                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
-#define DMA21_Y_COUNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
-#define DMA21_Y_MODIFY                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
-#define DMA21_CURR_DESC_PTR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
-#define DMA21_PREV_DESC_PTR            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
-#define DMA21_CURR_ADDR              0xFFC0902C         /* DMA21 Current Address */
-#define DMA21_IRQ_STATUS                  0xFFC09030         /* DMA21 Status Register */
-#define DMA21_CURR_X_COUNT              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA21_CURR_Y_COUNT              0xFFC09038         /* DMA21 Current Row Count (2D only) */
-#define DMA21_BWL_COUNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
-#define DMA21_CURR_BWL_COUNT            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
-#define DMA21_BWM_COUNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
-#define DMA21_CURR_BWM_COUNT            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA22
-   ========================= */
-#define DMA22_NEXT_DESC_PTR            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
-#define DMA22_START_ADDR             0xFFC09084         /* DMA22 Start Address of Current Buffer */
-#define DMA22_CONFIG                   0xFFC09088         /* DMA22 Configuration Register */
-#define DMA22_X_COUNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
-#define DMA22_X_MODIFY                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
-#define DMA22_Y_COUNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
-#define DMA22_Y_MODIFY                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
-#define DMA22_CURR_DESC_PTR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
-#define DMA22_PREV_DESC_PTR            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
-#define DMA22_CURR_ADDR              0xFFC090AC         /* DMA22 Current Address */
-#define DMA22_IRQ_STATUS                  0xFFC090B0         /* DMA22 Status Register */
-#define DMA22_CURR_X_COUNT              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA22_CURR_Y_COUNT              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
-#define DMA22_BWL_COUNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
-#define DMA22_CURR_BWL_COUNT            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
-#define DMA22_BWM_COUNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
-#define DMA22_CURR_BWM_COUNT            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA23
-   ========================= */
-#define DMA23_NEXT_DESC_PTR            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
-#define DMA23_START_ADDR             0xFFC09104         /* DMA23 Start Address of Current Buffer */
-#define DMA23_CONFIG                   0xFFC09108         /* DMA23 Configuration Register */
-#define DMA23_X_COUNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
-#define DMA23_X_MODIFY                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
-#define DMA23_Y_COUNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
-#define DMA23_Y_MODIFY                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
-#define DMA23_CURR_DESC_PTR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
-#define DMA23_PREV_DESC_PTR            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
-#define DMA23_CURR_ADDR              0xFFC0912C         /* DMA23 Current Address */
-#define DMA23_IRQ_STATUS                  0xFFC09130         /* DMA23 Status Register */
-#define DMA23_CURR_X_COUNT              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA23_CURR_Y_COUNT              0xFFC09138         /* DMA23 Current Row Count (2D only) */
-#define DMA23_BWL_COUNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
-#define DMA23_CURR_BWL_COUNT            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
-#define DMA23_BWM_COUNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
-#define DMA23_CURR_BWM_COUNT            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA24
-   ========================= */
-#define DMA24_NEXT_DESC_PTR            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
-#define DMA24_START_ADDR             0xFFC09184         /* DMA24 Start Address of Current Buffer */
-#define DMA24_CONFIG                   0xFFC09188         /* DMA24 Configuration Register */
-#define DMA24_X_COUNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
-#define DMA24_X_MODIFY                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
-#define DMA24_Y_COUNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
-#define DMA24_Y_MODIFY                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
-#define DMA24_CURR_DESC_PTR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
-#define DMA24_PREV_DESC_PTR            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
-#define DMA24_CURR_ADDR              0xFFC091AC         /* DMA24 Current Address */
-#define DMA24_IRQ_STATUS                  0xFFC091B0         /* DMA24 Status Register */
-#define DMA24_CURR_X_COUNT              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA24_CURR_Y_COUNT              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
-#define DMA24_BWL_COUNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
-#define DMA24_CURR_BWL_COUNT            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
-#define DMA24_BWM_COUNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
-#define DMA24_CURR_BWM_COUNT            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA25
-   ========================= */
-#define DMA25_NEXT_DESC_PTR            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
-#define DMA25_START_ADDR             0xFFC09204         /* DMA25 Start Address of Current Buffer */
-#define DMA25_CONFIG                   0xFFC09208         /* DMA25 Configuration Register */
-#define DMA25_X_COUNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
-#define DMA25_X_MODIFY                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
-#define DMA25_Y_COUNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
-#define DMA25_Y_MODIFY                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
-#define DMA25_CURR_DESC_PTR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
-#define DMA25_PREV_DESC_PTR            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
-#define DMA25_CURR_ADDR              0xFFC0922C         /* DMA25 Current Address */
-#define DMA25_IRQ_STATUS                  0xFFC09230         /* DMA25 Status Register */
-#define DMA25_CURR_X_COUNT              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA25_CURR_Y_COUNT              0xFFC09238         /* DMA25 Current Row Count (2D only) */
-#define DMA25_BWL_COUNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
-#define DMA25_CURR_BWL_COUNT            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
-#define DMA25_BWM_COUNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
-#define DMA25_CURR_BWM_COUNT            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA26
-   ========================= */
-#define DMA26_NEXT_DESC_PTR            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
-#define DMA26_START_ADDR             0xFFC09284         /* DMA26 Start Address of Current Buffer */
-#define DMA26_CONFIG                   0xFFC09288         /* DMA26 Configuration Register */
-#define DMA26_X_COUNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
-#define DMA26_X_MODIFY                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
-#define DMA26_Y_COUNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
-#define DMA26_Y_MODIFY                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
-#define DMA26_CURR_DESC_PTR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
-#define DMA26_PREV_DESC_PTR            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
-#define DMA26_CURR_ADDR              0xFFC092AC         /* DMA26 Current Address */
-#define DMA26_IRQ_STATUS                  0xFFC092B0         /* DMA26 Status Register */
-#define DMA26_CURR_X_COUNT              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA26_CURR_Y_COUNT              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
-#define DMA26_BWL_COUNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
-#define DMA26_CURR_BWL_COUNT            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
-#define DMA26_BWM_COUNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
-#define DMA26_CURR_BWM_COUNT            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA27
-   ========================= */
-#define DMA27_NEXT_DESC_PTR            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
-#define DMA27_START_ADDR             0xFFC09304         /* DMA27 Start Address of Current Buffer */
-#define DMA27_CONFIG                   0xFFC09308         /* DMA27 Configuration Register */
-#define DMA27_X_COUNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
-#define DMA27_X_MODIFY                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
-#define DMA27_Y_COUNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
-#define DMA27_Y_MODIFY                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
-#define DMA27_CURR_DESC_PTR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
-#define DMA27_PREV_DESC_PTR            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
-#define DMA27_CURR_ADDR              0xFFC0932C         /* DMA27 Current Address */
-#define DMA27_IRQ_STATUS                  0xFFC09330         /* DMA27 Status Register */
-#define DMA27_CURR_X_COUNT              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA27_CURR_Y_COUNT              0xFFC09338         /* DMA27 Current Row Count (2D only) */
-#define DMA27_BWL_COUNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
-#define DMA27_CURR_BWL_COUNT            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
-#define DMA27_BWM_COUNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
-#define DMA27_CURR_BWM_COUNT            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA28
-   ========================= */
-#define DMA28_NEXT_DESC_PTR            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
-#define DMA28_START_ADDR             0xFFC09384         /* DMA28 Start Address of Current Buffer */
-#define DMA28_CONFIG                   0xFFC09388         /* DMA28 Configuration Register */
-#define DMA28_X_COUNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
-#define DMA28_X_MODIFY                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
-#define DMA28_Y_COUNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
-#define DMA28_Y_MODIFY                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
-#define DMA28_CURR_DESC_PTR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
-#define DMA28_PREV_DESC_PTR            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
-#define DMA28_CURR_ADDR              0xFFC093AC         /* DMA28 Current Address */
-#define DMA28_IRQ_STATUS                  0xFFC093B0         /* DMA28 Status Register */
-#define DMA28_CURR_X_COUNT              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA28_CURR_Y_COUNT              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
-#define DMA28_BWL_COUNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
-#define DMA28_CURR_BWL_COUNT            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
-#define DMA28_BWM_COUNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
-#define DMA28_CURR_BWM_COUNT            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA29
-   ========================= */
-#define DMA29_NEXT_DESC_PTR            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
-#define DMA29_START_ADDR             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
-#define DMA29_CONFIG                   0xFFC0B008         /* DMA29 Configuration Register */
-#define DMA29_X_COUNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
-#define DMA29_X_MODIFY                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
-#define DMA29_Y_COUNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
-#define DMA29_Y_MODIFY                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
-#define DMA29_CURR_DESC_PTR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
-#define DMA29_PREV_DESC_PTR            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
-#define DMA29_CURR_ADDR              0xFFC0B02C         /* DMA29 Current Address */
-#define DMA29_IRQ_STATUS                  0xFFC0B030         /* DMA29 Status Register */
-#define DMA29_CURR_X_COUNT              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA29_CURR_Y_COUNT              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
-#define DMA29_BWL_COUNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
-#define DMA29_CURR_BWL_COUNT            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
-#define DMA29_BWM_COUNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
-#define DMA29_CURR_BWM_COUNT            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA30
-   ========================= */
-#define DMA30_NEXT_DESC_PTR            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
-#define DMA30_START_ADDR             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
-#define DMA30_CONFIG                   0xFFC0B088         /* DMA30 Configuration Register */
-#define DMA30_X_COUNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
-#define DMA30_X_MODIFY                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
-#define DMA30_Y_COUNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
-#define DMA30_Y_MODIFY                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
-#define DMA30_CURR_DESC_PTR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
-#define DMA30_PREV_DESC_PTR            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
-#define DMA30_CURR_ADDR              0xFFC0B0AC         /* DMA30 Current Address */
-#define DMA30_IRQ_STATUS                  0xFFC0B0B0         /* DMA30 Status Register */
-#define DMA30_CURR_X_COUNT              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA30_CURR_Y_COUNT              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
-#define DMA30_BWL_COUNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
-#define DMA30_CURR_BWL_COUNT            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
-#define DMA30_BWM_COUNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
-#define DMA30_CURR_BWM_COUNT            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA31
-   ========================= */
-#define DMA31_NEXT_DESC_PTR            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
-#define DMA31_START_ADDR             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
-#define DMA31_CONFIG                   0xFFC0B108         /* DMA31 Configuration Register */
-#define DMA31_X_COUNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
-#define DMA31_X_MODIFY                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
-#define DMA31_Y_COUNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
-#define DMA31_Y_MODIFY                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
-#define DMA31_CURR_DESC_PTR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
-#define DMA31_PREV_DESC_PTR            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
-#define DMA31_CURR_ADDR              0xFFC0B12C         /* DMA31 Current Address */
-#define DMA31_IRQ_STATUS                  0xFFC0B130         /* DMA31 Status Register */
-#define DMA31_CURR_X_COUNT              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA31_CURR_Y_COUNT              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
-#define DMA31_BWL_COUNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
-#define DMA31_CURR_BWL_COUNT            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
-#define DMA31_BWM_COUNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
-#define DMA31_CURR_BWM_COUNT            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA32
-   ========================= */
-#define DMA32_NEXT_DESC_PTR            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
-#define DMA32_START_ADDR             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
-#define DMA32_CONFIG                   0xFFC0B188         /* DMA32 Configuration Register */
-#define DMA32_X_COUNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
-#define DMA32_X_MODIFY                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
-#define DMA32_Y_COUNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
-#define DMA32_Y_MODIFY                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
-#define DMA32_CURR_DESC_PTR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
-#define DMA32_PREV_DESC_PTR            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
-#define DMA32_CURR_ADDR              0xFFC0B1AC         /* DMA32 Current Address */
-#define DMA32_IRQ_STATUS                  0xFFC0B1B0         /* DMA32 Status Register */
-#define DMA32_CURR_X_COUNT              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA32_CURR_Y_COUNT              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
-#define DMA32_BWL_COUNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
-#define DMA32_CURR_BWL_COUNT            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
-#define DMA32_BWM_COUNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
-#define DMA32_CURR_BWM_COUNT            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA33
-   ========================= */
-#define DMA33_NEXT_DESC_PTR            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
-#define DMA33_START_ADDR             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
-#define DMA33_CONFIG                   0xFFC0D008         /* DMA33 Configuration Register */
-#define DMA33_X_COUNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
-#define DMA33_X_MODIFY                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
-#define DMA33_Y_COUNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
-#define DMA33_Y_MODIFY                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
-#define DMA33_CURR_DESC_PTR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
-#define DMA33_PREV_DESC_PTR            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
-#define DMA33_CURR_ADDR              0xFFC0D02C         /* DMA33 Current Address */
-#define DMA33_IRQ_STATUS                  0xFFC0D030         /* DMA33 Status Register */
-#define DMA33_CURR_X_COUNT              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA33_CURR_Y_COUNT              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
-#define DMA33_BWL_COUNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
-#define DMA33_CURR_BWL_COUNT            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
-#define DMA33_BWM_COUNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
-#define DMA33_CURR_BWM_COUNT            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA34
-   ========================= */
-#define DMA34_NEXT_DESC_PTR            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
-#define DMA34_START_ADDR             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
-#define DMA34_CONFIG                   0xFFC0D088         /* DMA34 Configuration Register */
-#define DMA34_X_COUNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
-#define DMA34_X_MODIFY                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
-#define DMA34_Y_COUNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
-#define DMA34_Y_MODIFY                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
-#define DMA34_CURR_DESC_PTR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
-#define DMA34_PREV_DESC_PTR            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
-#define DMA34_CURR_ADDR              0xFFC0D0AC         /* DMA34 Current Address */
-#define DMA34_IRQ_STATUS                  0xFFC0D0B0         /* DMA34 Status Register */
-#define DMA34_CURR_X_COUNT              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA34_CURR_Y_COUNT              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
-#define DMA34_BWL_COUNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
-#define DMA34_CURR_BWL_COUNT            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
-#define DMA34_BWM_COUNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
-#define DMA34_CURR_BWM_COUNT            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA35
-   ========================= */
-#define DMA35_NEXT_DESC_PTR            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
-#define DMA35_START_ADDR             0xFFC10004         /* DMA35 Start Address of Current Buffer */
-#define DMA35_CONFIG                   0xFFC10008         /* DMA35 Configuration Register */
-#define DMA35_X_COUNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
-#define DMA35_X_MODIFY                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
-#define DMA35_Y_COUNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
-#define DMA35_Y_MODIFY                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
-#define DMA35_CURR_DESC_PTR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
-#define DMA35_PREV_DESC_PTR            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
-#define DMA35_CURR_ADDR              0xFFC1002C         /* DMA35 Current Address */
-#define DMA35_IRQ_STATUS                  0xFFC10030         /* DMA35 Status Register */
-#define DMA35_CURR_X_COUNT              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA35_CURR_Y_COUNT              0xFFC10038         /* DMA35 Current Row Count (2D only) */
-#define DMA35_BWL_COUNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
-#define DMA35_CURR_BWL_COUNT            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
-#define DMA35_BWM_COUNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
-#define DMA35_CURR_BWM_COUNT            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA36
-   ========================= */
-#define DMA36_NEXT_DESC_PTR            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
-#define DMA36_START_ADDR             0xFFC10084         /* DMA36 Start Address of Current Buffer */
-#define DMA36_CONFIG                   0xFFC10088         /* DMA36 Configuration Register */
-#define DMA36_X_COUNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
-#define DMA36_X_MODIFY                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
-#define DMA36_Y_COUNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
-#define DMA36_Y_MODIFY                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
-#define DMA36_CURR_DESC_PTR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
-#define DMA36_PREV_DESC_PTR            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
-#define DMA36_CURR_ADDR              0xFFC100AC         /* DMA36 Current Address */
-#define DMA36_IRQ_STATUS                  0xFFC100B0         /* DMA36 Status Register */
-#define DMA36_CURR_X_COUNT              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA36_CURR_Y_COUNT              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
-#define DMA36_BWL_COUNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
-#define DMA36_CURR_BWL_COUNT            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
-#define DMA36_BWM_COUNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
-#define DMA36_CURR_BWM_COUNT            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA37
-   ========================= */
-#define DMA37_NEXT_DESC_PTR            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
-#define DMA37_START_ADDR             0xFFC10104         /* DMA37 Start Address of Current Buffer */
-#define DMA37_CONFIG                   0xFFC10108         /* DMA37 Configuration Register */
-#define DMA37_X_COUNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
-#define DMA37_X_MODIFY                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
-#define DMA37_Y_COUNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
-#define DMA37_Y_MODIFY                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
-#define DMA37_CURR_DESC_PTR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
-#define DMA37_PREV_DESC_PTR            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
-#define DMA37_CURR_ADDR              0xFFC1012C         /* DMA37 Current Address */
-#define DMA37_IRQ_STATUS                  0xFFC10130         /* DMA37 Status Register */
-#define DMA37_CURR_X_COUNT              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA37_CURR_Y_COUNT              0xFFC10138         /* DMA37 Current Row Count (2D only) */
-#define DMA37_BWL_COUNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
-#define DMA37_CURR_BWL_COUNT            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
-#define DMA37_BWM_COUNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
-#define DMA37_CURR_BWM_COUNT            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA38
-   ========================= */
-#define DMA38_NEXT_DESC_PTR            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
-#define DMA38_START_ADDR             0xFFC12004         /* DMA38 Start Address of Current Buffer */
-#define DMA38_CONFIG                   0xFFC12008         /* DMA38 Configuration Register */
-#define DMA38_X_COUNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
-#define DMA38_X_MODIFY                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
-#define DMA38_Y_COUNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
-#define DMA38_Y_MODIFY                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
-#define DMA38_CURR_DESC_PTR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
-#define DMA38_PREV_DESC_PTR            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
-#define DMA38_CURR_ADDR              0xFFC1202C         /* DMA38 Current Address */
-#define DMA38_IRQ_STATUS                  0xFFC12030         /* DMA38 Status Register */
-#define DMA38_CURR_X_COUNT              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA38_CURR_Y_COUNT              0xFFC12038         /* DMA38 Current Row Count (2D only) */
-#define DMA38_BWL_COUNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
-#define DMA38_CURR_BWL_COUNT            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
-#define DMA38_BWM_COUNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
-#define DMA38_CURR_BWM_COUNT            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA39
-   ========================= */
-#define DMA39_NEXT_DESC_PTR            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
-#define DMA39_START_ADDR             0xFFC12084         /* DMA39 Start Address of Current Buffer */
-#define DMA39_CONFIG                   0xFFC12088         /* DMA39 Configuration Register */
-#define DMA39_X_COUNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
-#define DMA39_X_MODIFY                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
-#define DMA39_Y_COUNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
-#define DMA39_Y_MODIFY                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
-#define DMA39_CURR_DESC_PTR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
-#define DMA39_PREV_DESC_PTR            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
-#define DMA39_CURR_ADDR              0xFFC120AC         /* DMA39 Current Address */
-#define DMA39_IRQ_STATUS                  0xFFC120B0         /* DMA39 Status Register */
-#define DMA39_CURR_X_COUNT              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA39_CURR_Y_COUNT              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
-#define DMA39_BWL_COUNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
-#define DMA39_CURR_BWL_COUNT            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
-#define DMA39_BWM_COUNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
-#define DMA39_CURR_BWM_COUNT            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA40
-   ========================= */
-#define DMA40_NEXT_DESC_PTR            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
-#define DMA40_START_ADDR             0xFFC12104         /* DMA40 Start Address of Current Buffer */
-#define DMA40_CONFIG                   0xFFC12108         /* DMA40 Configuration Register */
-#define DMA40_X_COUNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
-#define DMA40_X_MODIFY                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
-#define DMA40_Y_COUNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
-#define DMA40_Y_MODIFY                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
-#define DMA40_CURR_DESC_PTR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
-#define DMA40_PREV_DESC_PTR            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
-#define DMA40_CURR_ADDR              0xFFC1212C         /* DMA40 Current Address */
-#define DMA40_IRQ_STATUS                  0xFFC12130         /* DMA40 Status Register */
-#define DMA40_CURR_X_COUNT              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA40_CURR_Y_COUNT              0xFFC12138         /* DMA40 Current Row Count (2D only) */
-#define DMA40_BWL_COUNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
-#define DMA40_CURR_BWL_COUNT            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
-#define DMA40_BWM_COUNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
-#define DMA40_CURR_BWM_COUNT            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA41
-   ========================= */
-#define DMA41_NEXT_DESC_PTR            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
-#define DMA41_START_ADDR             0xFFC12184         /* DMA41 Start Address of Current Buffer */
-#define DMA41_CONFIG                   0xFFC12188         /* DMA41 Configuration Register */
-#define DMA41_X_COUNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
-#define DMA41_X_MODIFY                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
-#define DMA41_Y_COUNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
-#define DMA41_Y_MODIFY                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
-#define DMA41_CURR_DESC_PTR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
-#define DMA41_PREV_DESC_PTR            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
-#define DMA41_CURR_ADDR              0xFFC121AC         /* DMA41 Current Address */
-#define DMA41_IRQ_STATUS                  0xFFC121B0         /* DMA41 Status Register */
-#define DMA41_CURR_X_COUNT              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA41_CURR_Y_COUNT              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
-#define DMA41_BWL_COUNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
-#define DMA41_CURR_BWL_COUNT            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
-#define DMA41_BWM_COUNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
-#define DMA41_CURR_BWM_COUNT            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA42
-   ========================= */
-#define DMA42_NEXT_DESC_PTR            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
-#define DMA42_START_ADDR             0xFFC14004         /* DMA42 Start Address of Current Buffer */
-#define DMA42_CONFIG                   0xFFC14008         /* DMA42 Configuration Register */
-#define DMA42_X_COUNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
-#define DMA42_X_MODIFY                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
-#define DMA42_Y_COUNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
-#define DMA42_Y_MODIFY                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
-#define DMA42_CURR_DESC_PTR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
-#define DMA42_PREV_DESC_PTR            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
-#define DMA42_CURR_ADDR              0xFFC1402C         /* DMA42 Current Address */
-#define DMA42_IRQ_STATUS                  0xFFC14030         /* DMA42 Status Register */
-#define DMA42_CURR_X_COUNT              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA42_CURR_Y_COUNT              0xFFC14038         /* DMA42 Current Row Count (2D only) */
-#define DMA42_BWL_COUNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
-#define DMA42_CURR_BWL_COUNT            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
-#define DMA42_BWM_COUNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
-#define DMA42_CURR_BWM_COUNT            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA43
-   ========================= */
-#define DMA43_NEXT_DESC_PTR            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
-#define DMA43_START_ADDR             0xFFC14084         /* DMA43 Start Address of Current Buffer */
-#define DMA43_CONFIG                   0xFFC14088         /* DMA43 Configuration Register */
-#define DMA43_X_COUNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
-#define DMA43_X_MODIFY                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
-#define DMA43_Y_COUNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
-#define DMA43_Y_MODIFY                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
-#define DMA43_CURR_DESC_PTR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
-#define DMA43_PREV_DESC_PTR            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
-#define DMA43_CURR_ADDR              0xFFC140AC         /* DMA43 Current Address */
-#define DMA43_IRQ_STATUS                  0xFFC140B0         /* DMA43 Status Register */
-#define DMA43_CURR_X_COUNT              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA43_CURR_Y_COUNT              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
-#define DMA43_BWL_COUNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
-#define DMA43_CURR_BWL_COUNT            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
-#define DMA43_BWM_COUNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
-#define DMA43_CURR_BWM_COUNT            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA44
-   ========================= */
-#define DMA44_NEXT_DESC_PTR            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
-#define DMA44_START_ADDR             0xFFC14104         /* DMA44 Start Address of Current Buffer */
-#define DMA44_CONFIG                   0xFFC14108         /* DMA44 Configuration Register */
-#define DMA44_X_COUNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
-#define DMA44_X_MODIFY                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
-#define DMA44_Y_COUNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
-#define DMA44_Y_MODIFY                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
-#define DMA44_CURR_DESC_PTR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
-#define DMA44_PREV_DESC_PTR            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
-#define DMA44_CURR_ADDR              0xFFC1412C         /* DMA44 Current Address */
-#define DMA44_IRQ_STATUS                  0xFFC14130         /* DMA44 Status Register */
-#define DMA44_CURR_X_COUNT              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA44_CURR_Y_COUNT              0xFFC14138         /* DMA44 Current Row Count (2D only) */
-#define DMA44_BWL_COUNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
-#define DMA44_CURR_BWL_COUNT            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
-#define DMA44_BWM_COUNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
-#define DMA44_CURR_BWM_COUNT            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA45
-   ========================= */
-#define DMA45_NEXT_DESC_PTR            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
-#define DMA45_START_ADDR             0xFFC14184         /* DMA45 Start Address of Current Buffer */
-#define DMA45_CONFIG                   0xFFC14188         /* DMA45 Configuration Register */
-#define DMA45_X_COUNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
-#define DMA45_X_MODIFY                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
-#define DMA45_Y_COUNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
-#define DMA45_Y_MODIFY                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
-#define DMA45_CURR_DESC_PTR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
-#define DMA45_PREV_DESC_PTR            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
-#define DMA45_CURR_ADDR              0xFFC141AC         /* DMA45 Current Address */
-#define DMA45_IRQ_STATUS                  0xFFC141B0         /* DMA45 Status Register */
-#define DMA45_CURR_X_COUNT              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA45_CURR_Y_COUNT              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
-#define DMA45_BWL_COUNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
-#define DMA45_CURR_BWL_COUNT            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
-#define DMA45_BWM_COUNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
-#define DMA45_CURR_BWM_COUNT            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA46
-   ========================= */
-#define DMA46_NEXT_DESC_PTR            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
-#define DMA46_START_ADDR             0xFFC14204         /* DMA46 Start Address of Current Buffer */
-#define DMA46_CONFIG                   0xFFC14208         /* DMA46 Configuration Register */
-#define DMA46_X_COUNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
-#define DMA46_X_MODIFY                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
-#define DMA46_Y_COUNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
-#define DMA46_Y_MODIFY                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
-#define DMA46_CURR_DESC_PTR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
-#define DMA46_PREV_DESC_PTR            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
-#define DMA46_CURR_ADDR              0xFFC1422C         /* DMA46 Current Address */
-#define DMA46_IRQ_STATUS                  0xFFC14230         /* DMA46 Status Register */
-#define DMA46_CURR_X_COUNT              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA46_CURR_Y_COUNT              0xFFC14238         /* DMA46 Current Row Count (2D only) */
-#define DMA46_BWL_COUNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
-#define DMA46_CURR_BWL_COUNT            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
-#define DMA46_BWM_COUNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
-#define DMA46_CURR_BWM_COUNT            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
-
-
-/********************************************************************************
-    DMA Alias Definitions
- ********************************************************************************/
-#define MDMA0_DEST_CRC0_NEXT_DESC_PTR   (DMA22_NEXT_DESC_PTR)
-#define MDMA0_DEST_CRC0_START_ADDR    (DMA22_START_ADDR)
-#define MDMA0_DEST_CRC0_CONFIG          (DMA22_CONFIG)
-#define MDMA0_DEST_CRC0_X_COUNT         (DMA22_X_COUNT)
-#define MDMA0_DEST_CRC0_X_MODIFY         (DMA22_X_MODIFY)
-#define MDMA0_DEST_CRC0_Y_COUNT         (DMA22_Y_COUNT)
-#define MDMA0_DEST_CRC0_Y_MODIFY         (DMA22_Y_MODIFY)
-#define MDMA0_DEST_CRC0_CURR_DESC_PTR   (DMA22_CURR_DESC_PTR)
-#define MDMA0_DEST_CRC0_PREV_DESC_PTR   (DMA22_PREV_DESC_PTR)
-#define MDMA0_DEST_CRC0_CURR_ADDR     (DMA22_CURR_ADDR)
-#define MDMA0_DEST_CRC0_IRQ_STATUS         (DMA22_IRQ_STATUS)
-#define MDMA0_DEST_CRC0_CURR_X_COUNT     (DMA22_CURR_X_COUNT)
-#define MDMA0_DEST_CRC0_CURR_Y_COUNT     (DMA22_CURR_Y_COUNT)
-#define MDMA0_DEST_CRC0_BWL_COUNT       (DMA22_BWL_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWL_COUNT   (DMA22_CURR_BWL_COUNT)
-#define MDMA0_DEST_CRC0_BWM_COUNT       (DMA22_BWM_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWM_COUNT   (DMA22_CURR_BWM_COUNT)
-#define MDMA0_SRC_CRC0_NEXT_DESC_PTR    (DMA21_NEXT_DESC_PTR)
-#define MDMA0_SRC_CRC0_START_ADDR     (DMA21_START_ADDR)
-#define MDMA0_SRC_CRC0_CONFIG           (DMA21_CONFIG)
-#define MDMA0_SRC_CRC0_X_COUNT          (DMA21_X_COUNT)
-#define MDMA0_SRC_CRC0_X_MODIFY          (DMA21_X_MODIFY)
-#define MDMA0_SRC_CRC0_Y_COUNT          (DMA21_Y_COUNT)
-#define MDMA0_SRC_CRC0_Y_MODIFY          (DMA21_Y_MODIFY)
-#define MDMA0_SRC_CRC0_CURR_DESC_PTR    (DMA21_CURR_DESC_PTR)
-#define MDMA0_SRC_CRC0_PREV_DESC_PTR    (DMA21_PREV_DESC_PTR)
-#define MDMA0_SRC_CRC0_CURR_ADDR      (DMA21_CURR_ADDR)
-#define MDMA0_SRC_CRC0_IRQ_STATUS          (DMA21_IRQ_STATUS)
-#define MDMA0_SRC_CRC0_CURR_X_COUNT      (DMA21_CURR_X_COUNT)
-#define MDMA0_SRC_CRC0_CURR_Y_COUNT      (DMA21_CURR_Y_COUNT)
-#define MDMA0_SRC_CRC0_BWL_COUNT        (DMA21_BWL_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWL_COUNT    (DMA21_CURR_BWL_COUNT)
-#define MDMA0_SRC_CRC0_BWM_COUNT        (DMA21_BWM_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWM_COUNT    (DMA21_CURR_BWM_COUNT)
-#define MDMA1_DEST_CRC1_NEXT_DESC_PTR   (DMA24_NEXT_DESC_PTR)
-#define MDMA1_DEST_CRC1_START_ADDR    (DMA24_START_ADDR)
-#define MDMA1_DEST_CRC1_CONFIG          (DMA24_CONFIG)
-#define MDMA1_DEST_CRC1_X_COUNT         (DMA24_X_COUNT)
-#define MDMA1_DEST_CRC1_X_MODIFY         (DMA24_X_MODIFY)
-#define MDMA1_DEST_CRC1_Y_COUNT         (DMA24_Y_COUNT)
-#define MDMA1_DEST_CRC1_Y_MODIFY         (DMA24_Y_MODIFY)
-#define MDMA1_DEST_CRC1_CURR_DESC_PTR   (DMA24_CURR_DESC_PTR)
-#define MDMA1_DEST_CRC1_PREV_DESC_PTR   (DMA24_PREV_DESC_PTR)
-#define MDMA1_DEST_CRC1_CURR_ADDR     (DMA24_CURR_ADDR)
-#define MDMA1_DEST_CRC1_IRQ_STATUS         (DMA24_IRQ_STATUS)
-#define MDMA1_DEST_CRC1_CURR_X_COUNT     (DMA24_CURR_X_COUNT)
-#define MDMA1_DEST_CRC1_CURR_Y_COUNT     (DMA24_CURR_Y_COUNT)
-#define MDMA1_DEST_CRC1_BWL_COUNT       (DMA24_BWL_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWL_COUNT   (DMA24_CURR_BWL_COUNT)
-#define MDMA1_DEST_CRC1_BWM_COUNT       (DMA24_BWM_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWM_COUNT   (DMA24_CURR_BWM_COUNT)
-#define MDMA1_SRC_CRC1_NEXT_DESC_PTR    (DMA23_NEXT_DESC_PTR)
-#define MDMA1_SRC_CRC1_START_ADDR     (DMA23_START_ADDR)
-#define MDMA1_SRC_CRC1_CONFIG           (DMA23_CONFIG)
-#define MDMA1_SRC_CRC1_X_COUNT          (DMA23_X_COUNT)
-#define MDMA1_SRC_CRC1_X_MODIFY          (DMA23_X_MODIFY)
-#define MDMA1_SRC_CRC1_Y_COUNT          (DMA23_Y_COUNT)
-#define MDMA1_SRC_CRC1_Y_MODIFY          (DMA23_Y_MODIFY)
-#define MDMA1_SRC_CRC1_CURR_DESC_PTR    (DMA23_CURR_DESC_PTR)
-#define MDMA1_SRC_CRC1_PREV_DESC_PTR    (DMA23_PREV_DESC_PTR)
-#define MDMA1_SRC_CRC1_CURR_ADDR      (DMA23_CURR_ADDR)
-#define MDMA1_SRC_CRC1_IRQ_STATUS          (DMA23_IRQ_STATUS)
-#define MDMA1_SRC_CRC1_CURR_X_COUNT      (DMA23_CURR_X_COUNT)
-#define MDMA1_SRC_CRC1_CURR_Y_COUNT      (DMA23_CURR_Y_COUNT)
-#define MDMA1_SRC_CRC1_BWL_COUNT        (DMA23_BWL_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWL_COUNT    (DMA23_CURR_BWL_COUNT)
-#define MDMA1_SRC_CRC1_BWM_COUNT        (DMA23_BWM_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWM_COUNT    (DMA23_CURR_BWM_COUNT)
-#define MDMA2_DEST_NEXT_DESC_PTR            (DMA26_NEXT_DESC_PTR)
-#define MDMA2_DEST_START_ADDR             (DMA26_START_ADDR)
-#define MDMA2_DEST_CONFIG                   (DMA26_CONFIG)
-#define MDMA2_DEST_X_COUNT                  (DMA26_X_COUNT)
-#define MDMA2_DEST_X_MODIFY                  (DMA26_X_MODIFY)
-#define MDMA2_DEST_Y_COUNT                  (DMA26_Y_COUNT)
-#define MDMA2_DEST_Y_MODIFY                  (DMA26_Y_MODIFY)
-#define MDMA2_DEST_CURR_DESC_PTR            (DMA26_CURR_DESC_PTR)
-#define MDMA2_DEST_PREV_DESC_PTR            (DMA26_PREV_DESC_PTR)
-#define MDMA2_DEST_CURR_ADDR              (DMA26_CURR_ADDR)
-#define MDMA2_DEST_IRQ_STATUS                  (DMA26_IRQ_STATUS)
-#define MDMA2_DEST_CURR_X_COUNT              (DMA26_CURR_X_COUNT)
-#define MDMA2_DEST_CURR_Y_COUNT              (DMA26_CURR_Y_COUNT)
-#define MDMA2_DEST_BWL_COUNT                (DMA26_BWL_COUNT)
-#define MDMA2_DEST_CURR_BWL_COUNT            (DMA26_CURR_BWL_COUNT)
-#define MDMA2_DEST_BWM_COUNT                (DMA26_BWM_COUNT)
-#define MDMA2_DEST_CURR_BWM_COUNT            (DMA26_CURR_BWM_COUNT)
-#define MDMA2_SRC_NEXT_DESC_PTR            (DMA25_NEXT_DESC_PTR)
-#define MDMA2_SRC_START_ADDR             (DMA25_START_ADDR)
-#define MDMA2_SRC_CONFIG                   (DMA25_CONFIG)
-#define MDMA2_SRC_X_COUNT                  (DMA25_X_COUNT)
-#define MDMA2_SRC_X_MODIFY                  (DMA25_X_MODIFY)
-#define MDMA2_SRC_Y_COUNT                  (DMA25_Y_COUNT)
-#define MDMA2_SRC_Y_MODIFY                  (DMA25_Y_MODIFY)
-#define MDMA2_SRC_CURR_DESC_PTR            (DMA25_CURR_DESC_PTR)
-#define MDMA2_SRC_PREV_DESC_PTR            (DMA25_PREV_DESC_PTR)
-#define MDMA2_SRC_CURR_ADDR              (DMA25_CURR_ADDR)
-#define MDMA2_SRC_IRQ_STATUS                  (DMA25_IRQ_STATUS)
-#define MDMA2_SRC_CURR_X_COUNT              (DMA25_CURR_X_COUNT)
-#define MDMA2_SRC_CURR_Y_COUNT              (DMA25_CURR_Y_COUNT)
-#define MDMA2_SRC_BWL_COUNT                (DMA25_BWL_COUNT)
-#define MDMA2_SRC_CURR_BWL_COUNT            (DMA25_CURR_BWL_COUNT)
-#define MDMA2_SRC_BWM_COUNT                (DMA25_BWM_COUNT)
-#define MDMA2_SRC_CURR_BWM_COUNT            (DMA25_CURR_BWM_COUNT)
-#define MDMA3_DEST_NEXT_DESC_PTR            (DMA28_NEXT_DESC_PTR)
-#define MDMA3_DEST_START_ADDR             (DMA28_START_ADDR)
-#define MDMA3_DEST_CONFIG                   (DMA28_CONFIG)
-#define MDMA3_DEST_X_COUNT                  (DMA28_X_COUNT)
-#define MDMA3_DEST_X_MODIFY                  (DMA28_X_MODIFY)
-#define MDMA3_DEST_Y_COUNT                  (DMA28_Y_COUNT)
-#define MDMA3_DEST_Y_MODIFY                  (DMA28_Y_MODIFY)
-#define MDMA3_DEST_CURR_DESC_PTR            (DMA28_CURR_DESC_PTR)
-#define MDMA3_DEST_PREV_DESC_PTR            (DMA28_PREV_DESC_PTR)
-#define MDMA3_DEST_CURR_ADDR              (DMA28_CURR_ADDR)
-#define MDMA3_DEST_IRQ_STATUS                  (DMA28_IRQ_STATUS)
-#define MDMA3_DEST_CURR_X_COUNT              (DMA28_CURR_X_COUNT)
-#define MDMA3_DEST_CURR_Y_COUNT              (DMA28_CURR_Y_COUNT)
-#define MDMA3_DEST_BWL_COUNT                (DMA28_BWL_COUNT)
-#define MDMA3_DEST_CURR_BWL_COUNT            (DMA28_CURR_BWL_COUNT)
-#define MDMA3_DEST_BWM_COUNT                (DMA28_BWM_COUNT)
-#define MDMA3_DEST_CURR_BWM_COUNT            (DMA28_CURR_BWM_COUNT)
-#define MDMA3_SRC_NEXT_DESC_PTR            (DMA27_NEXT_DESC_PTR)
-#define MDMA3_SRC_START_ADDR             (DMA27_START_ADDR)
-#define MDMA3_SRC_CONFIG                   (DMA27_CONFIG)
-#define MDMA3_SRC_X_COUNT                  (DMA27_X_COUNT)
-#define MDMA3_SRC_X_MODIFY                  (DMA27_X_MODIFY)
-#define MDMA3_SRC_Y_COUNT                  (DMA27_Y_COUNT)
-#define MDMA3_SRC_Y_MODIFY                  (DMA27_Y_MODIFY)
-#define MDMA3_SRC_CURR_DESC_PTR            (DMA27_CURR_DESC_PTR)
-#define MDMA3_SRC_PREV_DESC_PTR            (DMA27_PREV_DESC_PTR)
-#define MDMA3_SRC_CURR_ADDR              (DMA27_CURR_ADDR)
-#define MDMA3_SRC_IRQ_STATUS                  (DMA27_IRQ_STATUS)
-#define MDMA3_SRC_CURR_X_COUNT              (DMA27_CURR_X_COUNT)
-#define MDMA3_SRC_CURR_Y_COUNT              (DMA27_CURR_Y_COUNT)
-#define MDMA3_SRC_BWL_COUNT                (DMA27_BWL_COUNT)
-#define MDMA3_SRC_CURR_BWL_COUNT            (DMA27_CURR_BWL_COUNT)
-#define MDMA3_SRC_BWM_COUNT                (DMA27_BWM_COUNT)
-#define MDMA3_SRC_CURR_BWM_COUNT            (DMA27_CURR_BWM_COUNT)
-
-
-/* =========================
-        DMC Registers
-   ========================= */
-
-/* =========================
-        DMC0
-   ========================= */
-#define DMC0_ID                     0xFFC80000         /* DMC0 Identification Register */
-#define DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
-#define DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
-#define DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Controller */
-#define DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask */
-#define DMC0_CFG                    0xFFC80040         /* DMC0 SDRAM Configuration */
-#define DMC0_TR0                    0xFFC80044         /* DMC0 Timing Register 0 */
-#define DMC0_TR1                    0xFFC80048         /* DMC0 Timing Register 1 */
-#define DMC0_TR2                    0xFFC8004C         /* DMC0 Timing Register 2 */
-#define DMC0_MSK                    0xFFC8005C         /* DMC0 Mode Register Mask */
-#define DMC0_MR                     0xFFC80060         /* DMC0 Mode Shadow register */
-#define DMC0_EMR1                   0xFFC80064         /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2                   0xFFC80068         /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3                   0xFFC8006C         /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
-#define DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register 0 */
-
-#define DEVSZ_64                0x000         /* DMC External Bank Size = 64Mbit */
-#define DEVSZ_128               0x100         /* DMC External Bank Size = 128Mbit */
-#define DEVSZ_256               0x200         /* DMC External Bank Size = 256Mbit */
-#define DEVSZ_512               0x300         /* DMC External Bank Size = 512Mbit */
-#define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */
-#define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */
-
-/* =========================
-        L2CTL Registers
-   ========================= */
-
-/* =========================
-        L2CTL0
-   ========================= */
-#define L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 L2 Control Register */
-#define L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 L2 Core 0 Access Control Register */
-#define L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 L2 Core 1 Access Control Register */
-#define L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 L2 System Access Control Register */
-#define L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 L2 Status Register */
-#define L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 L2 Read Priority Count Register */
-#define L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 L2 Write Priority Count Register */
-#define L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Register */
-#define L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 L2 Bank 0 ECC Error Address Register */
-#define L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 L2 Bank 1 ECC Error Address Register */
-#define L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 L2 Bank 2 ECC Error Address Register */
-#define L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 L2 Bank 3 ECC Error Address Register */
-#define L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 L2 Bank 4 ECC Error Address Register */
-#define L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 L2 Bank 5 ECC Error Address Register */
-#define L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 L2 Bank 6 ECC Error Address Register */
-#define L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 L2 Bank 7 ECC Error Address Register */
-#define L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 L2 AXI Error 0 Type Register */
-#define L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 L2 AXI Error 0 Address Register */
-#define L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 L2 AXI Error 1 Type Register */
-#define L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 L2 AXI Error 1 Address Register */
-
-
-/* =========================
-        SEC Registers
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Core Interface (SCI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-
-#define SEC_SCI_BASE 0xFFCA4400
-#define SEC_SCI_OFF 0x40
-#define SEC_CCTL 0x0         /* SEC Core Control Register n */
-#define SEC_CSTAT 0x4         /* SEC Core Status Register n */
-#define SEC_CPND 0x8         /* SEC Core Pending IRQ Register n */
-#define SEC_CACT 0xC         /* SEC Core Active IRQ Register n */
-#define SEC_CPMSK 0x10         /* SEC Core IRQ Priority Mask Register n */
-#define SEC_CGMSK 0x14         /* SEC Core IRQ Group Mask Register n */
-#define SEC_CPLVL 0x18         /* SEC Core IRQ Priority Level Register n */
-#define SEC_CSID 0x1C         /* SEC Core IRQ Source ID Register n */
-
-#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
-#define bfin_write_SEC_SCI(n, reg, val) \
-	bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Fault Management Interface (SFI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL                   0xFFCA4010         /* SEC Fault Control Register */
-#define SEC_FSTAT                  0xFFCA4014         /* SEC Fault Status Register */
-#define SEC_FSID                   0xFFCA4018         /* SEC Fault Source ID Register */
-#define SEC_FEND                   0xFFCA401C         /* SEC Fault End Register */
-#define SEC_FDLY                   0xFFCA4020         /* SEC Fault Delay Register */
-#define SEC_FDLY_CUR               0xFFCA4024         /* SEC Fault Delay Current Register */
-#define SEC_FSRDLY                 0xFFCA4028         /* SEC Fault System Reset Delay Register */
-#define SEC_FSRDLY_CUR             0xFFCA402C         /* SEC Fault System Reset Delay Current Register */
-#define SEC_FCOPP                  0xFFCA4030         /* SEC Fault COP Period Register */
-#define SEC_FCOPP_CUR              0xFFCA4034         /* SEC Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Global Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL                   0xFFCA4000         /* SEC Global Control Register */
-#define SEC_GSTAT                  0xFFCA4004         /* SEC Global Status Register */
-#define SEC_RAISE                  0xFFCA4008         /* SEC Global Raise Register */
-#define SEC_END                    0xFFCA400C         /* SEC Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Source Interface (SSI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL0                  0xFFCA4800         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL1                  0xFFCA4808         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL2                  0xFFCA4810         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL3                  0xFFCA4818         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL4                  0xFFCA4820         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL5                  0xFFCA4828         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL6                  0xFFCA4830         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL7                  0xFFCA4838         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL8                  0xFFCA4840         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL9                  0xFFCA4848         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL10                 0xFFCA4850         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL11                 0xFFCA4858         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL12                 0xFFCA4860         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL13                 0xFFCA4868         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL14                 0xFFCA4870         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL15                 0xFFCA4878         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL16                 0xFFCA4880         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL17                 0xFFCA4888         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL18                 0xFFCA4890         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL19                 0xFFCA4898         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL20                 0xFFCA48A0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL21                 0xFFCA48A8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL22                 0xFFCA48B0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL23                 0xFFCA48B8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL24                 0xFFCA48C0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL25                 0xFFCA48C8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL26                 0xFFCA48D0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL27                 0xFFCA48D8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL28                 0xFFCA48E0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL29                 0xFFCA48E8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL30                 0xFFCA48F0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL31                 0xFFCA48F8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL32                 0xFFCA4900         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL33                 0xFFCA4908         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL34                 0xFFCA4910         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL35                 0xFFCA4918         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL36                 0xFFCA4920         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL37                 0xFFCA4928         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL38                 0xFFCA4930         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL39                 0xFFCA4938         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL40                 0xFFCA4940         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL41                 0xFFCA4948         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL42                 0xFFCA4950         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL43                 0xFFCA4958         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL44                 0xFFCA4960         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL45                 0xFFCA4968         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL46                 0xFFCA4970         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL47                 0xFFCA4978         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL48                 0xFFCA4980         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL49                 0xFFCA4988         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL50                 0xFFCA4990         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL51                 0xFFCA4998         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL52                 0xFFCA49A0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL53                 0xFFCA49A8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL54                 0xFFCA49B0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL55                 0xFFCA49B8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL56                 0xFFCA49C0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL57                 0xFFCA49C8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL58                 0xFFCA49D0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL59                 0xFFCA49D8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL60                 0xFFCA49E0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL61                 0xFFCA49E8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL62                 0xFFCA49F0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL63                 0xFFCA49F8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL64                 0xFFCA4A00         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL65                 0xFFCA4A08         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL66                 0xFFCA4A10         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL67                 0xFFCA4A18         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL68                 0xFFCA4A20         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL69                 0xFFCA4A28         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL70                 0xFFCA4A30         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL71                 0xFFCA4A38         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL72                 0xFFCA4A40         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL73                 0xFFCA4A48         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL74                 0xFFCA4A50         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL75                 0xFFCA4A58         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL76                 0xFFCA4A60         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL77                 0xFFCA4A68         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL78                 0xFFCA4A70         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL79                 0xFFCA4A78         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL80                 0xFFCA4A80         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL81                 0xFFCA4A88         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL82                 0xFFCA4A90         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL83                 0xFFCA4A98         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL84                 0xFFCA4AA0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL85                 0xFFCA4AA8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL86                 0xFFCA4AB0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL87                 0xFFCA4AB8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL88                 0xFFCA4AC0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL89                 0xFFCA4AC8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL90                 0xFFCA4AD0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL91                 0xFFCA4AD8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL92                 0xFFCA4AE0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL93                 0xFFCA4AE8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL94                 0xFFCA4AF0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL95                 0xFFCA4AF8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL96                 0xFFCA4B00         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL97                 0xFFCA4B08         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL98                 0xFFCA4B10         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL99                 0xFFCA4B18         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL100                0xFFCA4B20         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL101                0xFFCA4B28         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL102                0xFFCA4B30         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL103                0xFFCA4B38         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL104                0xFFCA4B40         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL105                0xFFCA4B48         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL106                0xFFCA4B50         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL107                0xFFCA4B58         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL108                0xFFCA4B60         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL109                0xFFCA4B68         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL110                0xFFCA4B70         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL111                0xFFCA4B78         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL112                0xFFCA4B80         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL113                0xFFCA4B88         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL114                0xFFCA4B90         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL115                0xFFCA4B98         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL116                0xFFCA4BA0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL117                0xFFCA4BA8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL118                0xFFCA4BB0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL119                0xFFCA4BB8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL120                0xFFCA4BC0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL121                0xFFCA4BC8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL122                0xFFCA4BD0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL123                0xFFCA4BD8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL124                0xFFCA4BE0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL125                0xFFCA4BE8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL126                0xFFCA4BF0         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL127                0xFFCA4BF8         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL128                0xFFCA4C00         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL129                0xFFCA4C08         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL130                0xFFCA4C10         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL131                0xFFCA4C18         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL132                0xFFCA4C20         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL133                0xFFCA4C28         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL134                0xFFCA4C30         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL135                0xFFCA4C38         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL136                0xFFCA4C40         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL137                0xFFCA4C48         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL138                0xFFCA4C50         /* SEC IRQ Source Control Register n */
-#define SEC_SCTL139                0xFFCA4C58         /* SEC IRQ Source Control Register n */
-#define SEC_SSTAT0                 0xFFCA4804         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT1                 0xFFCA480C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT2                 0xFFCA4814         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT3                 0xFFCA481C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT4                 0xFFCA4824         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT5                 0xFFCA482C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT6                 0xFFCA4834         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT7                 0xFFCA483C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT8                 0xFFCA4844         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT9                 0xFFCA484C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT10                0xFFCA4854         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT11                0xFFCA485C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT12                0xFFCA4864         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT13                0xFFCA486C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT14                0xFFCA4874         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT15                0xFFCA487C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT16                0xFFCA4884         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT17                0xFFCA488C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT18                0xFFCA4894         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT19                0xFFCA489C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT20                0xFFCA48A4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT21                0xFFCA48AC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT22                0xFFCA48B4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT23                0xFFCA48BC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT24                0xFFCA48C4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT25                0xFFCA48CC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT26                0xFFCA48D4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT27                0xFFCA48DC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT28                0xFFCA48E4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT29                0xFFCA48EC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT30                0xFFCA48F4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT31                0xFFCA48FC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT32                0xFFCA4904         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT33                0xFFCA490C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT34                0xFFCA4914         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT35                0xFFCA491C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT36                0xFFCA4924         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT37                0xFFCA492C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT38                0xFFCA4934         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT39                0xFFCA493C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT40                0xFFCA4944         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT41                0xFFCA494C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT42                0xFFCA4954         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT43                0xFFCA495C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT44                0xFFCA4964         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT45                0xFFCA496C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT46                0xFFCA4974         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT47                0xFFCA497C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT48                0xFFCA4984         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT49                0xFFCA498C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT50                0xFFCA4994         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT51                0xFFCA499C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT52                0xFFCA49A4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT53                0xFFCA49AC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT54                0xFFCA49B4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT55                0xFFCA49BC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT56                0xFFCA49C4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT57                0xFFCA49CC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT58                0xFFCA49D4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT59                0xFFCA49DC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT60                0xFFCA49E4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT61                0xFFCA49EC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT62                0xFFCA49F4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT63                0xFFCA49FC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT64                0xFFCA4A04         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT65                0xFFCA4A0C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT66                0xFFCA4A14         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT67                0xFFCA4A1C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT68                0xFFCA4A24         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT69                0xFFCA4A2C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT70                0xFFCA4A34         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT71                0xFFCA4A3C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT72                0xFFCA4A44         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT73                0xFFCA4A4C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT74                0xFFCA4A54         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT75                0xFFCA4A5C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT76                0xFFCA4A64         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT77                0xFFCA4A6C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT78                0xFFCA4A74         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT79                0xFFCA4A7C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT80                0xFFCA4A84         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT81                0xFFCA4A8C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT82                0xFFCA4A94         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT83                0xFFCA4A9C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT84                0xFFCA4AA4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT85                0xFFCA4AAC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT86                0xFFCA4AB4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT87                0xFFCA4ABC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT88                0xFFCA4AC4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT89                0xFFCA4ACC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT90                0xFFCA4AD4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT91                0xFFCA4ADC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT92                0xFFCA4AE4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT93                0xFFCA4AEC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT94                0xFFCA4AF4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT95                0xFFCA4AFC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT96                0xFFCA4B04         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT97                0xFFCA4B0C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT98                0xFFCA4B14         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT99                0xFFCA4B1C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT100               0xFFCA4B24         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT101               0xFFCA4B2C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT102               0xFFCA4B34         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT103               0xFFCA4B3C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT104               0xFFCA4B44         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT105               0xFFCA4B4C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT106               0xFFCA4B54         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT107               0xFFCA4B5C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT108               0xFFCA4B64         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT109               0xFFCA4B6C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT110               0xFFCA4B74         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT111               0xFFCA4B7C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT112               0xFFCA4B84         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT113               0xFFCA4B8C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT114               0xFFCA4B94         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT115               0xFFCA4B9C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT116               0xFFCA4BA4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT117               0xFFCA4BAC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT118               0xFFCA4BB4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT119               0xFFCA4BBC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT120               0xFFCA4BC4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT121               0xFFCA4BCC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT122               0xFFCA4BD4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT123               0xFFCA4BDC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT124               0xFFCA4BE4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT125               0xFFCA4BEC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT126               0xFFCA4BF4         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT127               0xFFCA4BFC         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT128               0xFFCA4C04         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT129               0xFFCA4C0C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT130               0xFFCA4C14         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT131               0xFFCA4C1C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT132               0xFFCA4C24         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT133               0xFFCA4C2C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT134               0xFFCA4C34         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT135               0xFFCA4C3C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT136               0xFFCA4C44         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT137               0xFFCA4C4C         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT138               0xFFCA4C54         /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT139               0xFFCA4C5C         /* SEC IRQ Source Status Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CCTL                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CCTL_LOCK                   0x80000000    /* LOCK: Lock */
-#define SEC_CCTL_NMI_EN                 0x00010000    /* NMIEN: Enable */
-#define SEC_CCTL_WAITIDLE               0x00001000    /* WFI: Wait for Idle */
-#define SEC_CCTL_RESET                  0x00000002    /* RESET: Reset */
-#define SEC_CCTL_EN                     0x00000001    /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSTAT                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSTAT_NMI                   0x00010000    /* NMI Status */
-#define SEC_CSTAT_WAITING               0x00001000    /* WFI: Waiting */
-#define SEC_CSTAT_VALID_SID             0x00000400    /* SIDV: Valid */
-#define SEC_CSTAT_VALID_ACT             0x00000200    /* ACTV: Valid */
-#define SEC_CSTAT_VALID_PND             0x00000100    /* PNDV: Valid */
-#define SEC_CSTAT_ERRC                  0x00000030    /* Error Cause */
-#define SEC_CSTAT_ACKERR                0x00000010    /* ERRC: Acknowledge Error */
-#define SEC_CSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPND                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPND_PRIO                   0x0000FF00    /* Highest Pending IRQ Priority */
-#define SEC_CPND_SID                    0x000000FF    /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CACT                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CACT_PRIO                   0x0000FF00    /* Highest Active IRQ Priority */
-#define SEC_CACT_SID                    0x000000FF    /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPMSK                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPMSK_LOCK                  0x80000000    /* LOCK: Lock */
-#define SEC_CPMSK_PRIO                  0x000000FF    /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CGMSK                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CGMSK_LOCK                  0x80000000    /* LOCK: Lock */
-#define SEC_CGMSK_MASK                  0x00000100    /* UGRP: Mask Ungrouped Sources */
-#define SEC_CGMSK_GRP                   0x0000000F    /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPLVL                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPLVL_LOCK                  0x80000000    /* LOCK: Lock */
-#define SEC_CPLVL_PLVL                  0x00000007    /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSID                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSID_SID                    0x000000FF    /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FCTL                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL_LOCK                   0x80000000    /* LOCK: Lock */
-#define SEC_FCTL_FLTPND_MODE            0x00002000    /* TES: Fault Pending Mode */
-#define SEC_FCTL_COP_MODE               0x00001000    /* CMS: COP Mode */
-#define SEC_FCTL_FLTIN_EN               0x00000080    /* FIEN: Enable */
-#define SEC_FCTL_SYSRST_EN              0x00000040    /* SREN: Enable */
-#define SEC_FCTL_TRGOUT_EN              0x00000020    /* TOEN: Enable */
-#define SEC_FCTL_FLTOUT_EN              0x00000010    /* FOEN: Enable */
-#define SEC_FCTL_RESET                  0x00000002    /* RESET: Reset */
-#define SEC_FCTL_EN                     0x00000001    /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSTAT                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSTAT_NXTFLT                0x00000400    /* NPND: Pending */
-#define SEC_FSTAT_FLTACT                0x00000200    /* ACT: Active Fault */
-#define SEC_FSTAT_FLTPND                0x00000100    /* PND: Pending */
-#define SEC_FSTAT_ERRC                  0x00000030    /* Error Cause */
-#define SEC_FSTAT_ENDERR                0x00000020    /* ERRC: End Error */
-#define SEC_FSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSID                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSID_SRC_EXTFLT             0x00010000    /* FEXT: Fault External */
-#define SEC_FSID_SID                    0x000000FF    /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FEND                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FEND_END_EXTFLT             0x00010000    /* FEXT: Fault External */
-#define SEC_FEND_SID                    0x000000FF    /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GCTL                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL_LOCK                   0x80000000    /* Lock */
-#define SEC_GCTL_RESET                  0x00000002    /* Reset */
-#define SEC_GCTL_EN                     0x00000001    /* Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GSTAT                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GSTAT_LWERR                 0x80000000    /* LWERR: Error Occurred */
-#define SEC_GSTAT_ADRERR                0x40000000    /* ADRERR: Error Occurred */
-#define SEC_GSTAT_SID                   0x00FF0000    /* Source ID for SSI Error */
-#define SEC_GSTAT_SCI                   0x00000F00    /* SCI ID for SCI Error */
-#define SEC_GSTAT_ERRC                  0x00000030    /* Error Cause */
-#define SEC_GSTAT_SCIERR                0x00000010    /* ERRC: SCI Error */
-#define SEC_GSTAT_SSIERR                0x00000020    /* ERRC: SSI Error */
-#define SEC_GSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_RAISE                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_RAISE_SID                   0x000000FF    /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_END                              Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_END_SID                     0x000000FF    /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SCTL                             Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL_LOCK                   0x80000000    /* Lock */
-#define SEC_SCTL_CTG                    0x0F000000    /* Core Target Select */
-#define SEC_SCTL_GRP                    0x000F0000    /* Group Select */
-#define SEC_SCTL_PRIO                   0x0000FF00    /* Priority Level Select */
-#define SEC_SCTL_ERR_EN                 0x00000010    /* ERREN: Enable */
-#define SEC_SCTL_EDGE                   0x00000008    /* ES: Edge Sensitive */
-#define SEC_SCTL_SRC_EN                 0x00000004    /* SEN: Enable */
-#define SEC_SCTL_FAULT_EN               0x00000002    /* FEN: Enable */
-#define SEC_SCTL_INT_EN                 0x00000001    /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SSTAT                            Pos/Masks     Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SSTAT_CHID                  0x00FF0000    /* Channel ID */
-#define SEC_SSTAT_ACTIVE_SRC            0x00000200    /* ACT: Active Source */
-#define SEC_SSTAT_PENDING               0x00000100    /* PND: Pending */
-#define SEC_SSTAT_ERRC                  0x00000030    /* Error Cause */
-#define SEC_SSTAT_ENDERR                0x00000020    /* ERRC: End Error */
-#define SEC_SSTAT_ERR                   0x00000002    /* Error */
-
-
-/* =========================
-        RCU Registers
-   ========================= */
-
-/* =========================
-        RCU0
-   ========================= */
-#define RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
-#define RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
-#define RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
-#define RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
-#define RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
-#define RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
-
-
-/* =========================
-        CGU0
-   ========================= */
-#define CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
-#define CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
-#define CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
-#define CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
-
-
-/* =========================
-        DPM Registers
-   ========================= */
-
-/* =========================
-        DPM0
-   ========================= */
-#define DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
-#define DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
-#define DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
-#define DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
-#define DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
-#define DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
-#define DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
-#define DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore Register */
-#define DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore Register */
-#define DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore Register */
-#define DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore Register */
-#define DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore Register */
-#define DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore Register */
-#define DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore Register */
-#define DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore Register */
-#define DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore Register */
-#define DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore Register */
-#define DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore Register */
-#define DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore Register */
-#define DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore Register */
-#define DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore Register */
-#define DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore Register */
-#define DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore Register */
-
-
-/* =========================
-        DBG Registers
-   ========================= */
-
-/* USB register */
-#define USB_FADDR                  0xFFCC1000         /* USB Device Address in Peripheral Mode */
-#define USB_POWER                  0xFFCC1001         /* USB Power and Device Control */
-#define USB_INTRTX                 0xFFCC1002         /* USB Transmit Interrupt */
-#define USB_INTRRX                 0xFFCC1004         /* USB Receive Interrupts */
-#define USB_INTRTXE                0xFFCC1006         /* USB Transmit Interrupt Enable */
-#define USB_INTRRXE                0xFFCC1008         /* USB Receive Interrupt Enable */
-#define USB_INTRUSB                    0xFFCC100A         /* USB USB Interrupts */
-#define USB_INTRUSBE                    0xFFCC100B         /* USB USB Interrupt Enable */
-#define USB_FRAME                  0xFFCC100C         /* USB Frame Number */
-#define USB_INDEX                  0xFFCC100E         /* USB Index */
-#define USB_TESTMODE               0xFFCC100F         /* USB Testmodes */
-#define USB_EPI_TXMAXP0            0xFFCC1010         /* USB Transmit Maximum Packet Length */
-#define USB_EP_NI0_TXMAXP          0xFFCC1010
-#define USB_EP0I_CSR0_H            0xFFCC1012         /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_H           0xFFCC1012         /* USB Transmit Configuration and Status */
-#define USB_EP0I_CSR0_P            0xFFCC1012         /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_P           0xFFCC1012         /* USB Transmit Configuration and Status */
-#define USB_EPI_RXMAXP0            0xFFCC1014         /* USB Receive Maximum Packet Length */
-#define USB_EPI_RXCSR0_H           0xFFCC1016         /* USB Receive Configuration and Status Register */
-#define USB_EPI_RXCSR0_P           0xFFCC1016         /* USB Receive Configuration and Status Register */
-#define USB_EP0I_CNT0              0xFFCC1018         /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EPI_RXCNT0             0xFFCC1018         /* USB Number of Byte Received */
-#define USB_EP0I_TYPE0             0xFFCC101A         /* USB Speed for Endpoint 0 */
-#define USB_EPI_TXTYPE0            0xFFCC101A         /* USB Transmit Type */
-#define USB_EP0I_NAKLIMIT0         0xFFCC101B         /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EPI_TXINTERVAL0        0xFFCC101B         /* USB Transmit Polling Interval */
-#define USB_EPI_RXTYPE0            0xFFCC101C         /* USB Receive Type */
-#define USB_EPI_RXINTERVAL0        0xFFCC101D         /* USB Receive Polling Interval */
-#define USB_EP0I_CFGDATA0          0xFFCC101F         /* USB Configuration Information */
-#define USB_FIFOB0                 0xFFCC1020         /* USB FIFO Data */
-#define USB_FIFOB1                 0xFFCC1024         /* USB FIFO Data */
-#define USB_FIFOB2                 0xFFCC1028         /* USB FIFO Data */
-#define USB_FIFOB3                 0xFFCC102C         /* USB FIFO Data */
-#define USB_FIFOB4                 0xFFCC1030         /* USB FIFO Data */
-#define USB_FIFOB5                 0xFFCC1034         /* USB FIFO Data */
-#define USB_FIFOB6                 0xFFCC1038         /* USB FIFO Data */
-#define USB_FIFOB7                 0xFFCC103C         /* USB FIFO Data */
-#define USB_FIFOB8                 0xFFCC1040         /* USB FIFO Data */
-#define USB_FIFOB9                 0xFFCC1044         /* USB FIFO Data */
-#define USB_FIFOB10                0xFFCC1048         /* USB FIFO Data */
-#define USB_FIFOB11                0xFFCC104C         /* USB FIFO Data */
-#define USB_FIFOH0                 0xFFCC1020         /* USB FIFO Data */
-#define USB_FIFOH1                 0xFFCC1024         /* USB FIFO Data */
-#define USB_FIFOH2                 0xFFCC1028         /* USB FIFO Data */
-#define USB_FIFOH3                 0xFFCC102C         /* USB FIFO Data */
-#define USB_FIFOH4                 0xFFCC1030         /* USB FIFO Data */
-#define USB_FIFOH5                 0xFFCC1034         /* USB FIFO Data */
-#define USB_FIFOH6                 0xFFCC1038         /* USB FIFO Data */
-#define USB_FIFOH7                 0xFFCC103C         /* USB FIFO Data */
-#define USB_FIFOH8                 0xFFCC1040         /* USB FIFO Data */
-#define USB_FIFOH9                 0xFFCC1044         /* USB FIFO Data */
-#define USB_FIFOH10                0xFFCC1048         /* USB FIFO Data */
-#define USB_FIFOH11                0xFFCC104C         /* USB FIFO Data */
-#define USB_FIFO0                  0xFFCC1020         /* USB FIFO Data */
-#define USB_EP0_FIFO               0xFFCC1020
-#define USB_FIFO1                  0xFFCC1024         /* USB FIFO Data */
-#define USB_FIFO2                  0xFFCC1028         /* USB FIFO Data */
-#define USB_FIFO3                  0xFFCC102C         /* USB FIFO Data */
-#define USB_FIFO4                  0xFFCC1030         /* USB FIFO Data */
-#define USB_FIFO5                  0xFFCC1034         /* USB FIFO Data */
-#define USB_FIFO6                  0xFFCC1038         /* USB FIFO Data */
-#define USB_FIFO7                  0xFFCC103C         /* USB FIFO Data */
-#define USB_FIFO8                  0xFFCC1040         /* USB FIFO Data */
-#define USB_FIFO9                  0xFFCC1044         /* USB FIFO Data */
-#define USB_FIFO10                 0xFFCC1048         /* USB FIFO Data */
-#define USB_FIFO11                 0xFFCC104C         /* USB FIFO Data */
-#define USB_OTG_DEV_CTL                0xFFCC1060         /* USB Device Control */
-#define USB_TXFIFOSZ               0xFFCC1062         /* USB Transmit FIFO Size */
-#define USB_RXFIFOSZ               0xFFCC1063         /* USB Receive FIFO Size */
-#define USB_TXFIFOADDR             0xFFCC1064         /* USB Transmit FIFO Address */
-#define USB_RXFIFOADDR             0xFFCC1066         /* USB Receive FIFO Address */
-#define USB_VENDSTAT               0xFFCC1068         /* USB Vendor Status */
-#define USB_HWVERS                 0xFFCC106C         /* USB Hardware Version */
-#define USB_EPINFO                 0xFFCC1078         /* USB Endpoint Info */
-#define USB_RAMINFO                0xFFCC1079         /* USB Ram Information */
-#define USB_LINKINFO               0xFFCC107A         /* USB Programmable Delay Values */
-#define USB_VPLEN                  0xFFCC107B         /* USB VBus Pulse Duration */
-#define USB_HS_EOF1                0xFFCC107C         /* USB High Speed End of Frame Remaining */
-#define USB_FS_EOF1                0xFFCC107D         /* USB Full Speed End of Frame Remaining */
-#define USB_LS_EOF1                0xFFCC107E         /* USB Low Speed End of Frame Remaining */
-#define USB_SOFT_RST               0xFFCC107F         /* USB Software Reset */
-#define USB_TXFUNCADDR0            0xFFCC1080         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR1            0xFFCC1088         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR2            0xFFCC1090         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR3            0xFFCC1098         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR4            0xFFCC10A0         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR5            0xFFCC10A8         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR6            0xFFCC10B0         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR7            0xFFCC10B8         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR8            0xFFCC10C0         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR9            0xFFCC10C8         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR10           0xFFCC10D0         /* USB Transmit Function Address */
-#define USB_TXFUNCADDR11           0xFFCC10D8         /* USB Transmit Function Address */
-#define USB_TXHUBADDR0             0xFFCC1082         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR1             0xFFCC108A         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR2             0xFFCC1092         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR3             0xFFCC109A         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR4             0xFFCC10A2         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR5             0xFFCC10AA         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR6             0xFFCC10B2         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR7             0xFFCC10BA         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR8             0xFFCC10C2         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR9             0xFFCC10CA         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR10            0xFFCC10D2         /* USB Transmit Hub Address */
-#define USB_TXHUBADDR11            0xFFCC10DA         /* USB Transmit Hub Address */
-#define USB_TXHUBPORT0             0xFFCC1083         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT1             0xFFCC108B         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT2             0xFFCC1093         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT3             0xFFCC109B         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT4             0xFFCC10A3         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT5             0xFFCC10AB         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT6             0xFFCC10B3         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT7             0xFFCC10BB         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT8             0xFFCC10C3         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT9             0xFFCC10CB         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT10            0xFFCC10D3         /* USB Transmit Hub Port */
-#define USB_TXHUBPORT11            0xFFCC10DB         /* USB Transmit Hub Port */
-#define USB_RXFUNCADDR0            0xFFCC1084         /* USB Receive Function Address */
-#define USB_RXFUNCADDR1            0xFFCC108C         /* USB Receive Function Address */
-#define USB_RXFUNCADDR2            0xFFCC1094         /* USB Receive Function Address */
-#define USB_RXFUNCADDR3            0xFFCC109C         /* USB Receive Function Address */
-#define USB_RXFUNCADDR4            0xFFCC10A4         /* USB Receive Function Address */
-#define USB_RXFUNCADDR5            0xFFCC10AC         /* USB Receive Function Address */
-#define USB_RXFUNCADDR6            0xFFCC10B4         /* USB Receive Function Address */
-#define USB_RXFUNCADDR7            0xFFCC10BC         /* USB Receive Function Address */
-#define USB_RXFUNCADDR8            0xFFCC10C4         /* USB Receive Function Address */
-#define USB_RXFUNCADDR9            0xFFCC10CC         /* USB Receive Function Address */
-#define USB_RXFUNCADDR10           0xFFCC10D4         /* USB Receive Function Address */
-#define USB_RXFUNCADDR11           0xFFCC10DC         /* USB Receive Function Address */
-#define USB_RXHUBADDR0             0xFFCC1086         /* USB Receive Hub Address */
-#define USB_RXHUBADDR1             0xFFCC108E         /* USB Receive Hub Address */
-#define USB_RXHUBADDR2             0xFFCC1096         /* USB Receive Hub Address */
-#define USB_RXHUBADDR3             0xFFCC109E         /* USB Receive Hub Address */
-#define USB_RXHUBADDR4             0xFFCC10A6         /* USB Receive Hub Address */
-#define USB_RXHUBADDR5             0xFFCC10AE         /* USB Receive Hub Address */
-#define USB_RXHUBADDR6             0xFFCC10B6         /* USB Receive Hub Address */
-#define USB_RXHUBADDR7             0xFFCC10BE         /* USB Receive Hub Address */
-#define USB_RXHUBADDR8             0xFFCC10C6         /* USB Receive Hub Address */
-#define USB_RXHUBADDR9             0xFFCC10CE         /* USB Receive Hub Address */
-#define USB_RXHUBADDR10            0xFFCC10D6         /* USB Receive Hub Address */
-#define USB_RXHUBADDR11            0xFFCC10DE         /* USB Receive Hub Address */
-#define USB_RXHUBPORT0             0xFFCC1087         /* USB Receive Hub Port */
-#define USB_RXHUBPORT1             0xFFCC108F         /* USB Receive Hub Port */
-#define USB_RXHUBPORT2             0xFFCC1097         /* USB Receive Hub Port */
-#define USB_RXHUBPORT3             0xFFCC109F         /* USB Receive Hub Port */
-#define USB_RXHUBPORT4             0xFFCC10A7         /* USB Receive Hub Port */
-#define USB_RXHUBPORT5             0xFFCC10AF         /* USB Receive Hub Port */
-#define USB_RXHUBPORT6             0xFFCC10B7         /* USB Receive Hub Port */
-#define USB_RXHUBPORT7             0xFFCC10BF         /* USB Receive Hub Port */
-#define USB_RXHUBPORT8             0xFFCC10C7         /* USB Receive Hub Port */
-#define USB_RXHUBPORT9             0xFFCC10CF         /* USB Receive Hub Port */
-#define USB_RXHUBPORT10            0xFFCC10D7         /* USB Receive Hub Port */
-#define USB_RXHUBPORT11            0xFFCC10DF         /* USB Receive Hub Port */
-#define USB_EP0_CSR0_H             0xFFCC1102         /* USB Config and Status EP0 */
-#define USB_EP0_CSR0_P             0xFFCC1102         /* USB Config and Status EP0 */
-#define USB_EP0_CNT0               0xFFCC1108         /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EP0_TYPE0              0xFFCC110A         /* USB Speed for Endpoint 0 */
-#define USB_EP0_NAKLIMIT0          0xFFCC110B         /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EP0_CFGDATA0           0xFFCC110F         /* USB Configuration Information */
-#define USB_EP_TXMAXP0             0xFFCC1110         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP1             0xFFCC1120         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP2             0xFFCC1130         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP3             0xFFCC1140         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP4             0xFFCC1150         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP5             0xFFCC1160         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP6             0xFFCC1170         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP7             0xFFCC1180         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP8             0xFFCC1190         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP9             0xFFCC11A0         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP10            0xFFCC11B0         /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXCSR0_H            0xFFCC1112         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_H            0xFFCC1122         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_H            0xFFCC1132         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_H            0xFFCC1142         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_H            0xFFCC1152         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_H            0xFFCC1162         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_H            0xFFCC1172         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_H            0xFFCC1182         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_H            0xFFCC1192         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_H            0xFFCC11A2         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_H           0xFFCC11B2         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR0_P            0xFFCC1112         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_P            0xFFCC1122         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_P            0xFFCC1132         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_P            0xFFCC1142         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_P            0xFFCC1152         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_P            0xFFCC1162         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_P            0xFFCC1172         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_P            0xFFCC1182         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_P            0xFFCC1192         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_P            0xFFCC11A2         /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_P           0xFFCC11B2         /* USB Transmit Configuration and Status */
-#define USB_EP_RXMAXP0             0xFFCC1114         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP1             0xFFCC1124         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP2             0xFFCC1134         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP3             0xFFCC1144         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP4             0xFFCC1154         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP5             0xFFCC1164         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP6             0xFFCC1174         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP7             0xFFCC1184         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP8             0xFFCC1194         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP9             0xFFCC11A4         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP10            0xFFCC11B4         /* USB Receive Maximum Packet Length */
-#define USB_EP_RXCSR0_H            0xFFCC1116         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_H            0xFFCC1126         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_H            0xFFCC1136         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_H            0xFFCC1146         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_H            0xFFCC1156         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_H            0xFFCC1166         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_H            0xFFCC1176         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_H            0xFFCC1186         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_H            0xFFCC1196         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_H            0xFFCC11A6         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_H           0xFFCC11B6         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR0_P            0xFFCC1116         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_P            0xFFCC1126         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_P            0xFFCC1136         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_P            0xFFCC1146         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_P            0xFFCC1156         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_P            0xFFCC1166         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_P            0xFFCC1176         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_P            0xFFCC1186         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_P            0xFFCC1196         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_P            0xFFCC11A6         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_P           0xFFCC11B6         /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCNT0              0xFFCC1118         /* USB Number of Byte Received */
-#define USB_EP_RXCNT1              0xFFCC1128         /* USB Number of Byte Received */
-#define USB_EP_RXCNT2              0xFFCC1138         /* USB Number of Byte Received */
-#define USB_EP_RXCNT3              0xFFCC1148         /* USB Number of Byte Received */
-#define USB_EP_RXCNT4              0xFFCC1158         /* USB Number of Byte Received */
-#define USB_EP_RXCNT5              0xFFCC1168         /* USB Number of Byte Received */
-#define USB_EP_RXCNT6              0xFFCC1178         /* USB Number of Byte Received */
-#define USB_EP_RXCNT7              0xFFCC1188         /* USB Number of Byte Received */
-#define USB_EP_RXCNT8              0xFFCC1198         /* USB Number of Byte Received */
-#define USB_EP_RXCNT9              0xFFCC11A8         /* USB Number of Byte Received */
-#define USB_EP_RXCNT10             0xFFCC11B8         /* USB Number of Byte Received */
-#define USB_EP_TXTYPE0             0xFFCC111A         /* USB Transmit Type */
-#define USB_EP_TXTYPE1             0xFFCC112A         /* USB Transmit Type */
-#define USB_EP_TXTYPE2             0xFFCC113A         /* USB Transmit Type */
-#define USB_EP_TXTYPE3             0xFFCC114A         /* USB Transmit Type */
-#define USB_EP_TXTYPE4             0xFFCC115A         /* USB Transmit Type */
-#define USB_EP_TXTYPE5             0xFFCC116A         /* USB Transmit Type */
-#define USB_EP_TXTYPE6             0xFFCC117A         /* USB Transmit Type */
-#define USB_EP_TXTYPE7             0xFFCC118A         /* USB Transmit Type */
-#define USB_EP_TXTYPE8             0xFFCC119A         /* USB Transmit Type */
-#define USB_EP_TXTYPE9             0xFFCC11AA         /* USB Transmit Type */
-#define USB_EP_TXTYPE10            0xFFCC11BA         /* USB Transmit Type */
-#define USB_EP_TXINTERVAL0         0xFFCC111B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL1         0xFFCC112B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL2         0xFFCC113B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL3         0xFFCC114B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL4         0xFFCC115B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL5         0xFFCC116B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL6         0xFFCC117B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL7         0xFFCC118B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL8         0xFFCC119B         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL9         0xFFCC11AB         /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL10        0xFFCC11BB         /* USB Transmit Polling Interval */
-#define USB_EP_RXTYPE0             0xFFCC111C         /* USB Receive Type */
-#define USB_EP_RXTYPE1             0xFFCC112C         /* USB Receive Type */
-#define USB_EP_RXTYPE2             0xFFCC113C         /* USB Receive Type */
-#define USB_EP_RXTYPE3             0xFFCC114C         /* USB Receive Type */
-#define USB_EP_RXTYPE4             0xFFCC115C         /* USB Receive Type */
-#define USB_EP_RXTYPE5             0xFFCC116C         /* USB Receive Type */
-#define USB_EP_RXTYPE6             0xFFCC117C         /* USB Receive Type */
-#define USB_EP_RXTYPE7             0xFFCC118C         /* USB Receive Type */
-#define USB_EP_RXTYPE8             0xFFCC119C         /* USB Receive Type */
-#define USB_EP_RXTYPE9             0xFFCC11AC         /* USB Receive Type */
-#define USB_EP_RXTYPE10            0xFFCC11BC         /* USB Receive Type */
-#define USB_EP_RXINTERVAL0         0xFFCC111D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL1         0xFFCC112D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL2         0xFFCC113D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL3         0xFFCC114D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL4         0xFFCC115D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL5         0xFFCC116D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL6         0xFFCC117D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL7         0xFFCC118D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL8         0xFFCC119D         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL9         0xFFCC11AD         /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL10        0xFFCC11BD         /* USB Receive Polling Interval */
-#define USB_DMA_IRQ                0xFFCC1200         /* USB Interrupt Register */
-#define USB_DMA_CTL0               0xFFCC1204         /* USB DMA Control */
-#define USB_DMA_CTL1               0xFFCC1214         /* USB DMA Control */
-#define USB_DMA_CTL2               0xFFCC1224         /* USB DMA Control */
-#define USB_DMA_CTL3               0xFFCC1234         /* USB DMA Control */
-#define USB_DMA_CTL4               0xFFCC1244         /* USB DMA Control */
-#define USB_DMA_CTL5               0xFFCC1254         /* USB DMA Control */
-#define USB_DMA_CTL6               0xFFCC1264         /* USB DMA Control */
-#define USB_DMA_CTL7               0xFFCC1274         /* USB DMA Control */
-#define USB_DMA_ADDR0              0xFFCC1208         /* USB DMA Address */
-#define USB_DMA_ADDR1              0xFFCC1218         /* USB DMA Address */
-#define USB_DMA_ADDR2              0xFFCC1228         /* USB DMA Address */
-#define USB_DMA_ADDR3              0xFFCC1238         /* USB DMA Address */
-#define USB_DMA_ADDR4              0xFFCC1248         /* USB DMA Address */
-#define USB_DMA_ADDR5              0xFFCC1258         /* USB DMA Address */
-#define USB_DMA_ADDR6              0xFFCC1268         /* USB DMA Address */
-#define USB_DMA_ADDR7              0xFFCC1278         /* USB DMA Address */
-#define USB_DMA_CNT0               0xFFCC120C         /* USB DMA Count */
-#define USB_DMA_CNT1               0xFFCC121C         /* USB DMA Count */
-#define USB_DMA_CNT2               0xFFCC122C         /* USB DMA Count */
-#define USB_DMA_CNT3               0xFFCC123C         /* USB DMA Count */
-#define USB_DMA_CNT4               0xFFCC124C         /* USB DMA Count */
-#define USB_DMA_CNT5               0xFFCC125C         /* USB DMA Count */
-#define USB_DMA_CNT6               0xFFCC126C         /* USB DMA Count */
-#define USB_DMA_CNT7               0xFFCC127C         /* USB DMA Count */
-#define USB_RQPKTCNT0              0xFFCC1300         /* USB Request Packet Count */
-#define USB_RQPKTCNT1              0xFFCC1304         /* USB Request Packet Count */
-#define USB_RQPKTCNT2              0xFFCC1308         /* USB Request Packet Count */
-#define USB_RQPKTCNT3              0xFFCC130C         /* USB Request Packet Count */
-#define USB_RQPKTCNT4              0xFFCC1310         /* USB Request Packet Count */
-#define USB_RQPKTCNT5              0xFFCC1314         /* USB Request Packet Count */
-#define USB_RQPKTCNT6              0xFFCC1318         /* USB Request Packet Count */
-#define USB_RQPKTCNT7              0xFFCC131C         /* USB Request Packet Count */
-#define USB_RQPKTCNT8              0xFFCC1320         /* USB Request Packet Count */
-#define USB_RQPKTCNT9              0xFFCC1324         /* USB Request Packet Count */
-#define USB_RQPKTCNT10             0xFFCC1328         /* USB Request Packet Count */
-#define USB_CT_UCH                 0xFFCC1344         /* USB Chirp Timeout */
-#define USB_CT_HHSRTN              0xFFCC1346         /* USB High Speed Resume Return to Normal */
-#define USB_CT_HSBT                0xFFCC1348         /* USB High Speed Timeout */
-#define USB_LPM_ATTR               0xFFCC1360         /* USB LPM Attribute */
-#define USB_LPM_CTL                0xFFCC1362         /* USB LPM Control */
-#define USB_LPM_IEN                0xFFCC1363         /* USB LPM Interrupt Enable */
-#define USB_LPM_IRQ                0xFFCC1364         /* USB LPM Interrupt */
-#define USB_LPM_FADDR              0xFFCC1365         /* USB LPM Function Address */
-#define USB_VBUS_CTL               0xFFCC1380         /* USB VBus Control */
-#define USB_BAT_CHG                0xFFCC1381         /* USB Battery Charging */
-#define USB_PHY_CTL                0xFFCC1394         /* USB PHY Control */
-#define USB_TESTCTL                0xFFCC1397         /* USB Test Control */
-#define USB_PLL_OSC                0xFFCC1398         /* USB PLL and Oscillator Control */
-
-
-
-/* =========================
-        CHIPID
-   ========================= */
-
-#define                           CHIPID  0xffc00014
-/* CHIPID Masks */
-#define                   CHIPID_VERSION  0xF0000000
-#define                    CHIPID_FAMILY  0x0FFFF000
-#define               CHIPID_MANUFACTURE  0x00000FFE
-
-
-#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
deleted file mode 100644
index 872d141ca119..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/dma.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_TX                   0
-#define CH_SPORT0_RX                   1
-#define CH_SPORT1_TX                   2
-#define CH_SPORT1_RX                   3
-#define CH_SPORT2_TX                   4
-#define CH_SPORT2_RX                   5
-#define CH_SPI0_TX                     6
-#define CH_SPI0_RX                     7
-#define CH_SPI1_TX                     8
-#define CH_SPI1_RX                     9
-#define CH_RSI                        10
-#define CH_SDU                        11
-#define CH_LP0                        13
-#define CH_LP1                        14
-#define CH_LP2                        15
-#define CH_LP3                        16
-#define CH_UART0_TX                   17
-#define CH_UART0_RX                   18
-#define CH_UART1_TX                   19
-#define CH_UART1_RX                   20
-#define CH_MEM_STREAM0_SRC_CRC0      21
-#define CH_MEM_STREAM0_SRC           CH_MEM_STREAM0_SRC_CRC0
-#define CH_MEM_STREAM0_DEST_CRC0     22
-#define CH_MEM_STREAM0_DEST          CH_MEM_STREAM0_DEST_CRC0
-#define CH_MEM_STREAM1_SRC_CRC1      23
-#define CH_MEM_STREAM1_SRC           CH_MEM_STREAM1_SRC_CRC1
-#define CH_MEM_STREAM1_DEST_CRC1     24
-#define CH_MEM_STREAM1_DEST          CH_MEM_STREAM1_DEST_CRC1
-#define CH_MEM_STREAM2_SRC           25
-#define CH_MEM_STREAM2_DEST          26
-#define CH_MEM_STREAM3_SRC           27
-#define CH_MEM_STREAM3_DEST          28
-#define CH_EPPI0_CH0                  29
-#define CH_EPPI0_CH1                  30
-#define CH_EPPI1_CH0                  31
-#define CH_EPPI1_CH1                  32
-#define CH_EPPI2_CH0                  33
-#define CH_EPPI2_CH1                  34
-#define CH_PIXC_CH0                   35
-#define CH_PIXC_CH1                   36
-#define CH_PIXC_CH2                   37
-#define CH_PVP_CPDOB                  38
-#define CH_PVP_CPDOC                  39
-#define CH_PVP_CPSTAT                 40
-#define CH_PVP_CPCI                   41
-#define CH_PVP_MPDO                   42
-#define CH_PVP_MPDI                   43
-#define CH_PVP_MPSTAT                 44
-#define CH_PVP_MPCI                   45
-#define CH_PVP_CPDOA                  46
-
-#define MAX_DMA_CHANNELS 47
-#define MAX_DMA_SUSPEND_CHANNELS 0
-#define DMA_MMR_SIZE_32
-
-#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
-#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
-#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
-#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
-#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
-#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
-#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
-#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
-#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
-#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
-#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
-#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
-#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
-#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
-
-#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
-#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
-#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
-#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
-#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
-#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
-
-#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
-#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
-#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
-#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
-#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
-#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
-#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
-#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
-#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
-#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
-#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
-#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
-#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
-#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
deleted file mode 100644
index 07182513e794..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0	0
-#define GPIO_PA1	1
-#define GPIO_PA2	2
-#define GPIO_PA3	3
-#define GPIO_PA4	4
-#define GPIO_PA5	5
-#define GPIO_PA6	6
-#define GPIO_PA7	7
-#define GPIO_PA8	8
-#define GPIO_PA9	9
-#define GPIO_PA10	10
-#define GPIO_PA11	11
-#define GPIO_PA12	12
-#define GPIO_PA13	13
-#define GPIO_PA14	14
-#define GPIO_PA15	15
-#define GPIO_PB0	16
-#define GPIO_PB1	17
-#define GPIO_PB2	18
-#define GPIO_PB3	19
-#define GPIO_PB4	20
-#define GPIO_PB5	21
-#define GPIO_PB6	22
-#define GPIO_PB7	23
-#define GPIO_PB8	24
-#define GPIO_PB9	25
-#define GPIO_PB10	26
-#define GPIO_PB11	27
-#define GPIO_PB12	28
-#define GPIO_PB13	29
-#define GPIO_PB14	30
-#define GPIO_PB15	31
-#define GPIO_PC0	32
-#define GPIO_PC1	33
-#define GPIO_PC2	34
-#define GPIO_PC3	35
-#define GPIO_PC4	36
-#define GPIO_PC5	37
-#define GPIO_PC6	38
-#define GPIO_PC7	39
-#define GPIO_PC8	40
-#define GPIO_PC9	41
-#define GPIO_PC10	42
-#define GPIO_PC11	43
-#define GPIO_PC12	44
-#define GPIO_PC13	45
-#define GPIO_PC14	46
-#define GPIO_PC15	47
-#define GPIO_PD0	48
-#define GPIO_PD1	49
-#define GPIO_PD2	50
-#define GPIO_PD3	51
-#define GPIO_PD4	52
-#define GPIO_PD5	53
-#define GPIO_PD6	54
-#define GPIO_PD7	55
-#define GPIO_PD8	56
-#define GPIO_PD9	57
-#define GPIO_PD10	58
-#define GPIO_PD11	59
-#define GPIO_PD12	60
-#define GPIO_PD13	61
-#define GPIO_PD14	62
-#define GPIO_PD15	63
-#define GPIO_PE0	64
-#define GPIO_PE1	65
-#define GPIO_PE2	66
-#define GPIO_PE3	67
-#define GPIO_PE4	68
-#define GPIO_PE5	69
-#define GPIO_PE6	70
-#define GPIO_PE7	71
-#define GPIO_PE8	72
-#define GPIO_PE9	73
-#define GPIO_PE10	74
-#define GPIO_PE11	75
-#define GPIO_PE12	76
-#define GPIO_PE13	77
-#define GPIO_PE14	78
-#define GPIO_PE15	79
-#define GPIO_PF0	80
-#define GPIO_PF1	81
-#define GPIO_PF2	82
-#define GPIO_PF3	83
-#define GPIO_PF4	84
-#define GPIO_PF5	85
-#define GPIO_PF6	86
-#define GPIO_PF7	87
-#define GPIO_PF8	88
-#define GPIO_PF9	89
-#define GPIO_PF10	90
-#define GPIO_PF11	91
-#define GPIO_PF12	92
-#define GPIO_PF13	93
-#define GPIO_PF14	94
-#define GPIO_PF15	95
-#define GPIO_PG0	96
-#define GPIO_PG1	97
-#define GPIO_PG2	98
-#define GPIO_PG3	99
-#define GPIO_PG4	100
-#define GPIO_PG5	101
-#define GPIO_PG6	102
-#define GPIO_PG7	103
-#define GPIO_PG8	104
-#define GPIO_PG9	105
-#define GPIO_PG10	106
-#define GPIO_PG11	107
-#define GPIO_PG12	108
-#define GPIO_PG13	109
-#define GPIO_PG14	110
-#define GPIO_PG15	111
-
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS        6
-#define NR_PINTS                112
-
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
-	unsigned long port_fer;
-	unsigned long port_fer_set;
-	unsigned long port_fer_clear;
-	unsigned long data;
-	unsigned long data_set;
-	unsigned long data_clear;
-	unsigned long dir;
-	unsigned long dir_set;
-	unsigned long dir_clear;
-	unsigned long inen;
-	unsigned long inen_set;
-	unsigned long inen_clear;
-	unsigned long port_mux;
-	unsigned long toggle;
-	unsigned long polar;
-	unsigned long polar_set;
-	unsigned long polar_clear;
-	unsigned long lock;
-	unsigned long spare;
-	unsigned long revid;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
deleted file mode 100644
index d1cb6a86f80a..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF60x_IRQ_H_
-#define _BF60x_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS		(5 * 32)
-
-#define IRQ_SEC_ERR		BFIN_IRQ(0)	/* SEC Error */
-#define IRQ_CGU_EVT		BFIN_IRQ(1)	/* CGU Event */
-#define IRQ_WATCH0		BFIN_IRQ(2)	/* Watchdog0 Interrupt */
-#define IRQ_WATCH1		BFIN_IRQ(3)	/* Watchdog1 Interrupt */
-#define IRQ_L2CTL0_ECC_ERR	BFIN_IRQ(4)	/* L2 ECC Error */
-#define IRQ_L2CTL0_ECC_WARN	BFIN_IRQ(5)	/* L2 ECC Waring */
-#define IRQ_C0_DBL_FAULT	BFIN_IRQ(6)	/* Core 0 Double Fault */
-#define IRQ_C1_DBL_FAULT	BFIN_IRQ(7)	/* Core 1 Double Fault */
-#define IRQ_C0_HW_ERR		BFIN_IRQ(8)	/* Core 0 Hardware Error */
-#define IRQ_C1_HW_ERR		BFIN_IRQ(9)	/* Core 1 Hardware Error */
-#define IRQ_C0_NMI_L1_PARITY_ERR	BFIN_IRQ(10)	/* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define IRQ_C1_NMI_L1_PARITY_ERR	BFIN_IRQ(11)	/* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define CORE_IRQS		(IRQ_C1_NMI_L1_PARITY_ERR + 1)
-
-#define IRQ_TIMER0		BFIN_IRQ(12)	/* Timer 0 Interrupt */
-#define IRQ_TIMER1		BFIN_IRQ(13)	/* Timer 1 Interrupt */
-#define IRQ_TIMER2		BFIN_IRQ(14)	/* Timer 2 Interrupt */
-#define IRQ_TIMER3		BFIN_IRQ(15)	/* Timer 3 Interrupt */
-#define IRQ_TIMER4		BFIN_IRQ(16)	/* Timer 4 Interrupt */
-#define IRQ_TIMER5		BFIN_IRQ(17)	/* Timer 5 Interrupt */
-#define IRQ_TIMER6		BFIN_IRQ(18)	/* Timer 6 Interrupt */
-#define IRQ_TIMER7		BFIN_IRQ(19)	/* Timer 7 Interrupt */
-#define IRQ_TIMER_STAT		BFIN_IRQ(20)	/* Timer Block Status */
-#define IRQ_PINT0		BFIN_IRQ(21)	/* PINT0 Interrupt */
-#define IRQ_PINT1		BFIN_IRQ(22)	/* PINT1 Interrupt */
-#define IRQ_PINT2		BFIN_IRQ(23)	/* PINT2 Interrupt */
-#define IRQ_PINT3		BFIN_IRQ(24)	/* PINT3 Interrupt */
-#define IRQ_PINT4		BFIN_IRQ(25)	/* PINT4 Interrupt */
-#define IRQ_PINT5		BFIN_IRQ(26)	/* PINT5 Interrupt */
-#define IRQ_CNT			BFIN_IRQ(27)	/* CNT Interrupt */
-#define IRQ_PWM0_TRIP		BFIN_IRQ(28)	/* PWM0 Trip Interrupt */
-#define IRQ_PWM0_SYNC		BFIN_IRQ(29)	/* PWM0 Sync Interrupt */
-#define IRQ_PWM1_TRIP		BFIN_IRQ(30)	/* PWM1 Trip Interrupt */
-#define IRQ_PWM1_SYNC		BFIN_IRQ(31)	/* PWM1 Sync Interrupt */
-#define IRQ_TWI0		BFIN_IRQ(32)	/* TWI0 Interrupt */
-#define IRQ_TWI1		BFIN_IRQ(33)	/* TWI1 Interrupt */
-#define IRQ_SOFT0		BFIN_IRQ(34)	/* Software-Driven Interrupt 0 */
-#define IRQ_SOFT1		BFIN_IRQ(35)	/* Software-Driven Interrupt 1 */
-#define IRQ_SOFT2		BFIN_IRQ(36)	/* Software-Driven Interrupt 2 */
-#define IRQ_SOFT3		BFIN_IRQ(37)	/* Software-Driven Interrupt 3 */
-#define IRQ_ACM_EVT_MISS	BFIN_IRQ(38)	/* ACM Event Miss */
-#define IRQ_ACM_EVT_COMPLETE 	BFIN_IRQ(39)	/* ACM Event Complete */
-#define IRQ_CAN0_RX		BFIN_IRQ(40)	/* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX		BFIN_IRQ(41)	/* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_STAT		BFIN_IRQ(42)	/* CAN0 Status */
-#define IRQ_SPORT0_TX		BFIN_IRQ(43)	/* SPORT0 TX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX_STAT	BFIN_IRQ(44)	/* SPORT0 TX Status Interrupt */
-#define IRQ_SPORT0_RX		BFIN_IRQ(45)	/* SPORT0 RX Interrupt (DMA1) */
-#define IRQ_SPORT0_RX_STAT	BFIN_IRQ(46)	/* SPORT0 RX Status Interrupt */
-#define IRQ_SPORT1_TX		BFIN_IRQ(47)	/* SPORT1 TX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX_STAT	BFIN_IRQ(48)	/* SPORT1 TX Status Interrupt */
-#define IRQ_SPORT1_RX		BFIN_IRQ(49)	/* SPORT1 RX Interrupt (DMA3) */
-#define IRQ_SPORT1_RX_STAT	BFIN_IRQ(50)	/* SPORT1 RX Status Interrupt */
-#define IRQ_SPORT2_TX		BFIN_IRQ(51)	/* SPORT2 TX Interrupt (DMA4) */
-#define IRQ_SPORT2_TX_STAT	BFIN_IRQ(52)	/* SPORT2 TX Status Interrupt */
-#define IRQ_SPORT2_RX		BFIN_IRQ(53)	/* SPORT2 RX Interrupt (DMA5) */
-#define IRQ_SPORT2_RX_STAT	BFIN_IRQ(54)	/* SPORT2 RX Status Interrupt */
-#define IRQ_SPI0_TX		BFIN_IRQ(55)	/* SPI0 TX Interrupt (DMA6) */
-#define IRQ_SPI0_RX		BFIN_IRQ(56)	/* SPI0 RX Interrupt (DMA7) */
-#define IRQ_SPI0_STAT		BFIN_IRQ(57)	/* SPI0 Status Interrupt */
-#define IRQ_SPI1_TX		BFIN_IRQ(58)	/* SPI1 TX Interrupt (DMA8) */
-#define IRQ_SPI1_RX		BFIN_IRQ(59)	/* SPI1 RX Interrupt (DMA9) */
-#define IRQ_SPI1_STAT		BFIN_IRQ(60)	/* SPI1 Status Interrupt */
-#define IRQ_RSI			BFIN_IRQ(61)	/* RSI (DMA10) Interrupt */
-#define IRQ_RSI_INT0		BFIN_IRQ(62)	/* RSI Interrupt0 */
-#define IRQ_RSI_INT1		BFIN_IRQ(63)	/* RSI Interrupt1 */
-#define IRQ_SDU			BFIN_IRQ(64)	/* DMA11 Data (SDU) */
-/*       -- RESERVED --             65		   DMA12 Data (Reserved) */
-/*       -- RESERVED --             66		   Reserved */
-/*       -- RESERVED --             67		   Reserved */
-#define IRQ_EMAC0_STAT		BFIN_IRQ(68)	/* EMAC0 Status */
-/*       -- RESERVED --             69		   EMAC0 Power (Reserved) */
-#define IRQ_EMAC1_STAT		BFIN_IRQ(70)	/* EMAC1 Status */
-/*       -- RESERVED --             71		   EMAC1 Power (Reserved) */
-#define IRQ_LP0			BFIN_IRQ(72)	/* DMA13 Data (Link Port 0) */
-#define IRQ_LP0_STAT		BFIN_IRQ(73)	/* Link Port 0 Status */
-#define IRQ_LP1			BFIN_IRQ(74)	/* DMA14 Data (Link Port 1) */
-#define IRQ_LP1_STAT		BFIN_IRQ(75)	/* Link Port 1 Status */
-#define IRQ_LP2			BFIN_IRQ(76)	/* DMA15 Data (Link Port 2) */
-#define IRQ_LP2_STAT		BFIN_IRQ(77)	/* Link Port 2 Status */
-#define IRQ_LP3			BFIN_IRQ(78)	/* DMA16 Data(Link Port 3) */
-#define IRQ_LP3_STAT		BFIN_IRQ(79)	/* Link Port 3 Status */
-#define IRQ_UART0_TX		BFIN_IRQ(80)	/* UART0 TX Interrupt (DMA17) */
-#define IRQ_UART0_RX		BFIN_IRQ(81)	/* UART0 RX Interrupt (DMA18) */
-#define IRQ_UART0_STAT		BFIN_IRQ(82)	/* UART0 Status(Error) Interrupt */
-#define IRQ_UART1_TX		BFIN_IRQ(83)	/* UART1 TX Interrupt (DMA19) */
-#define IRQ_UART1_RX		BFIN_IRQ(84)	/* UART1 RX Interrupt (DMA20) */
-#define IRQ_UART1_STAT		BFIN_IRQ(85)	/* UART1 Status(Error) Interrupt */
-#define IRQ_MDMA0_SRC_CRC0	BFIN_IRQ(86)	/* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
-#define IRQ_MDMA0_DEST_CRC0	BFIN_IRQ(87)	/* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
-#define IRQ_MDMAS0		IRQ_MDMA0_DEST_CRC0
-#define IRQ_CRC0_DCNTEXP	BFIN_IRQ(88)	/* CRC0 DATACOUNT Expiration */
-#define IRQ_CRC0_ERR		BFIN_IRQ(89)	/* CRC0 Error */
-#define IRQ_MDMA1_SRC_CRC1	BFIN_IRQ(90)	/* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
-#define IRQ_MDMA1_DEST_CRC1	BFIN_IRQ(91)	/* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
-#define IRQ_MDMAS1		IRQ_MDMA1_DEST_CRC1
-#define IRQ_CRC1_DCNTEXP	BFIN_IRQ(92)	/* CRC1 DATACOUNT Expiration */
-#define IRQ_CRC1_ERR		BFIN_IRQ(93)	/* CRC1 Error */
-#define IRQ_MDMA2_SRC		BFIN_IRQ(94)	/* DMA25 Data (MDMA Stream 2 Source Channel) */
-#define IRQ_MDMA2_DEST		BFIN_IRQ(95)	/* DMA26 Data (MDMA Stream 2 Destination Channel) */
-#define IRQ_MDMAS2		IRQ_MDMA2_DEST
-#define IRQ_MDMA3_SRC		BFIN_IRQ(96)	/* DMA27 Data (MDMA Stream 3 Source Channel) */
-#define IRQ_MDMA3_DEST 		BFIN_IRQ(97)	/* DMA28 Data (MDMA Stream 3 Destination Channel) */
-#define IRQ_MDMAS3		IRQ_MDMA3_DEST
-#define IRQ_EPPI0_CH0 		BFIN_IRQ(98)	/* DMA29 Data (EPPI0 Channel 0) */
-#define IRQ_EPPI0_CH1 		BFIN_IRQ(99)	/* DMA30 Data (EPPI0 Channel 1) */
-#define IRQ_EPPI0_STAT		BFIN_IRQ(100)	/* EPPI0 Status */
-#define IRQ_EPPI2_CH0		BFIN_IRQ(101)	/* DMA31 Data (EPPI2 Channel 0) */
-#define IRQ_EPPI2_CH1		BFIN_IRQ(102)	/* DMA32 Data (EPPI2 Channel 1) */
-#define IRQ_EPPI2_STAT		BFIN_IRQ(103)	/* EPPI2 Status */
-#define IRQ_EPPI1_CH0		BFIN_IRQ(104)	/* DMA33 Data (EPPI1 Channel 0) */
-#define IRQ_EPPI1_CH1		BFIN_IRQ(105)	/* DMA34 Data (EPPI1 Channel 1) */
-#define IRQ_EPPI1_STAT		BFIN_IRQ(106)	/* EPPI1 Status */
-#define IRQ_PIXC_CH0		BFIN_IRQ(107)	/* DMA35 Data (PIXC Channel 0) */
-#define IRQ_PIXC_CH1		BFIN_IRQ(108)	/* DMA36 Data (PIXC Channel 1) */
-#define IRQ_PIXC_CH2		BFIN_IRQ(109)	/* DMA37 Data (PIXC Channel 2) */
-#define IRQ_PIXC_STAT		BFIN_IRQ(110)	/* PIXC Status */
-#define IRQ_PVP_CPDOB		BFIN_IRQ(111)	/* DMA38 Data (PVP0 Camera Pipe Data Out B) */
-#define IRQ_PVP_CPDOC		BFIN_IRQ(112)	/* DMA39 Data (PVP0 Camera Pipe Data Out C) */
-#define IRQ_PVP_CPSTAT		BFIN_IRQ(113)	/* DMA40 Data (PVP0 Camera Pipe Status Out) */
-#define IRQ_PVP_CPCI		BFIN_IRQ(114)	/* DMA41 Data (PVP0 Camera Pipe Control In) */
-#define IRQ_PVP_STAT0		BFIN_IRQ(115)	/* PVP0 Status 0 */
-#define IRQ_PVP_MPDO		BFIN_IRQ(116)	/* DMA42 Data (PVP0 Memory Pipe Data Out) */
-#define IRQ_PVP_MPDI		BFIN_IRQ(117)	/* DMA43 Data (PVP0 Memory Pipe Data In) */
-#define IRQ_PVP_MPSTAT		BFIN_IRQ(118)	/* DMA44 Data (PVP0 Memory Pipe Status Out) */
-#define IRQ_PVP_MPCI		BFIN_IRQ(119)	/* DMA45 Data (PVP0 Memory Pipe Control In) */
-#define IRQ_PVP_CPDOA		BFIN_IRQ(120)	/* DMA46 Data (PVP0 Camera Pipe Data Out A) */
-#define IRQ_PVP_STAT1		BFIN_IRQ(121)	/* PVP0 Status 1 */
-#define IRQ_USB_STAT		BFIN_IRQ(122)	/* USB Status Interrupt */
-#define IRQ_USB_DMA		BFIN_IRQ(123)	/* USB DMA Interrupt */
-#define IRQ_TRU_INT0		BFIN_IRQ(124)	/* TRU0 Interrupt 0 */
-#define IRQ_TRU_INT1		BFIN_IRQ(125)	/* TRU0 Interrupt 1 */
-#define IRQ_TRU_INT2		BFIN_IRQ(126)	/* TRU0 Interrupt 2 */
-#define IRQ_TRU_INT3		BFIN_IRQ(127)	/* TRU0 Interrupt 3 */
-#define IRQ_DMAC0_ERROR		BFIN_IRQ(128)	/* DMAC0 Status Interrupt */
-#define IRQ_CGU0_ERROR		BFIN_IRQ(129)	/* CGU0 Error */
-/*       -- RESERVED --             130		   Reserved */
-#define IRQ_DPM			BFIN_IRQ(131)	/* DPM0 Event */
-/*       -- RESERVED --             132		   Reserved */
-#define IRQ_SWU0		BFIN_IRQ(133)	/* SWU0 */
-#define IRQ_SWU1		BFIN_IRQ(134)	/* SWU1 */
-#define IRQ_SWU2		BFIN_IRQ(135)	/* SWU2 */
-#define IRQ_SWU3		BFIN_IRQ(136)	/* SWU3 */
-#define IRQ_SWU4		BFIN_IRQ(137)	/* SWU4 */
-#define IRQ_SWU5		BFIN_IRQ(138)	/* SWU5 */
-#define IRQ_SWU6		BFIN_IRQ(139)	/* SWU6 */
-
-#define SYS_IRQS		IRQ_SWU6
-
-#define BFIN_PA_IRQ(x)		((x) + SYS_IRQS + 1)
-#define IRQ_PA0			BFIN_PA_IRQ(0)
-#define IRQ_PA1			BFIN_PA_IRQ(1)
-#define IRQ_PA2			BFIN_PA_IRQ(2)
-#define IRQ_PA3			BFIN_PA_IRQ(3)
-#define IRQ_PA4			BFIN_PA_IRQ(4)
-#define IRQ_PA5			BFIN_PA_IRQ(5)
-#define IRQ_PA6			BFIN_PA_IRQ(6)
-#define IRQ_PA7			BFIN_PA_IRQ(7)
-#define IRQ_PA8			BFIN_PA_IRQ(8)
-#define IRQ_PA9			BFIN_PA_IRQ(9)
-#define IRQ_PA10		BFIN_PA_IRQ(10)
-#define IRQ_PA11		BFIN_PA_IRQ(11)
-#define IRQ_PA12		BFIN_PA_IRQ(12)
-#define IRQ_PA13		BFIN_PA_IRQ(13)
-#define IRQ_PA14		BFIN_PA_IRQ(14)
-#define IRQ_PA15		BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x)		((x) + IRQ_PA15 + 1)
-#define IRQ_PB0			BFIN_PB_IRQ(0)
-#define IRQ_PB1			BFIN_PB_IRQ(1)
-#define IRQ_PB2			BFIN_PB_IRQ(2)
-#define IRQ_PB3			BFIN_PB_IRQ(3)
-#define IRQ_PB4			BFIN_PB_IRQ(4)
-#define IRQ_PB5			BFIN_PB_IRQ(5)
-#define IRQ_PB6			BFIN_PB_IRQ(6)
-#define IRQ_PB7			BFIN_PB_IRQ(7)
-#define IRQ_PB8			BFIN_PB_IRQ(8)
-#define IRQ_PB9			BFIN_PB_IRQ(9)
-#define IRQ_PB10		BFIN_PB_IRQ(10)
-#define IRQ_PB11		BFIN_PB_IRQ(11)
-#define IRQ_PB12		BFIN_PB_IRQ(12)
-#define IRQ_PB13		BFIN_PB_IRQ(13)
-#define IRQ_PB14		BFIN_PB_IRQ(14)
-#define IRQ_PB15		BFIN_PB_IRQ(15)		/* N/A */
-
-#define BFIN_PC_IRQ(x)		((x) + IRQ_PB15 + 1)
-#define IRQ_PC0			BFIN_PC_IRQ(0)
-#define IRQ_PC1			BFIN_PC_IRQ(1)
-#define IRQ_PC2			BFIN_PC_IRQ(2)
-#define IRQ_PC3			BFIN_PC_IRQ(3)
-#define IRQ_PC4			BFIN_PC_IRQ(4)
-#define IRQ_PC5			BFIN_PC_IRQ(5)
-#define IRQ_PC6			BFIN_PC_IRQ(6)
-#define IRQ_PC7			BFIN_PC_IRQ(7)
-#define IRQ_PC8			BFIN_PC_IRQ(8)
-#define IRQ_PC9			BFIN_PC_IRQ(9)
-#define IRQ_PC10		BFIN_PC_IRQ(10)
-#define IRQ_PC11		BFIN_PC_IRQ(11)
-#define IRQ_PC12		BFIN_PC_IRQ(12)
-#define IRQ_PC13		BFIN_PC_IRQ(13)
-#define IRQ_PC14		BFIN_PC_IRQ(14)		/* N/A */
-#define IRQ_PC15		BFIN_PC_IRQ(15)		/* N/A */
-
-#define BFIN_PD_IRQ(x)		((x) + IRQ_PC15 + 1)
-#define IRQ_PD0			BFIN_PD_IRQ(0)
-#define IRQ_PD1			BFIN_PD_IRQ(1)
-#define IRQ_PD2			BFIN_PD_IRQ(2)
-#define IRQ_PD3			BFIN_PD_IRQ(3)
-#define IRQ_PD4			BFIN_PD_IRQ(4)
-#define IRQ_PD5			BFIN_PD_IRQ(5)
-#define IRQ_PD6			BFIN_PD_IRQ(6)
-#define IRQ_PD7			BFIN_PD_IRQ(7)
-#define IRQ_PD8			BFIN_PD_IRQ(8)
-#define IRQ_PD9			BFIN_PD_IRQ(9)
-#define IRQ_PD10		BFIN_PD_IRQ(10)
-#define IRQ_PD11		BFIN_PD_IRQ(11)
-#define IRQ_PD12		BFIN_PD_IRQ(12)
-#define IRQ_PD13		BFIN_PD_IRQ(13)
-#define IRQ_PD14		BFIN_PD_IRQ(14)
-#define IRQ_PD15		BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x)		((x) + IRQ_PD15 + 1)
-#define IRQ_PE0			BFIN_PE_IRQ(0)
-#define IRQ_PE1			BFIN_PE_IRQ(1)
-#define IRQ_PE2			BFIN_PE_IRQ(2)
-#define IRQ_PE3			BFIN_PE_IRQ(3)
-#define IRQ_PE4			BFIN_PE_IRQ(4)
-#define IRQ_PE5			BFIN_PE_IRQ(5)
-#define IRQ_PE6			BFIN_PE_IRQ(6)
-#define IRQ_PE7			BFIN_PE_IRQ(7)
-#define IRQ_PE8			BFIN_PE_IRQ(8)
-#define IRQ_PE9			BFIN_PE_IRQ(9)
-#define IRQ_PE10		BFIN_PE_IRQ(10)
-#define IRQ_PE11		BFIN_PE_IRQ(11)
-#define IRQ_PE12		BFIN_PE_IRQ(12)
-#define IRQ_PE13		BFIN_PE_IRQ(13)
-#define IRQ_PE14		BFIN_PE_IRQ(14)
-#define IRQ_PE15		BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x)		((x) + IRQ_PE15 + 1)
-#define IRQ_PF0			BFIN_PF_IRQ(0)
-#define IRQ_PF1			BFIN_PF_IRQ(1)
-#define IRQ_PF2			BFIN_PF_IRQ(2)
-#define IRQ_PF3			BFIN_PF_IRQ(3)
-#define IRQ_PF4			BFIN_PF_IRQ(4)
-#define IRQ_PF5			BFIN_PF_IRQ(5)
-#define IRQ_PF6			BFIN_PF_IRQ(6)
-#define IRQ_PF7			BFIN_PF_IRQ(7)
-#define IRQ_PF8			BFIN_PF_IRQ(8)
-#define IRQ_PF9			BFIN_PF_IRQ(9)
-#define IRQ_PF10		BFIN_PF_IRQ(10)
-#define IRQ_PF11		BFIN_PF_IRQ(11)
-#define IRQ_PF12		BFIN_PF_IRQ(12)
-#define IRQ_PF13		BFIN_PF_IRQ(13)
-#define IRQ_PF14		BFIN_PF_IRQ(14)
-#define IRQ_PF15		BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x)		((x) + IRQ_PF15 + 1)
-#define IRQ_PG0			BFIN_PG_IRQ(0)
-#define IRQ_PG1			BFIN_PG_IRQ(1)
-#define IRQ_PG2			BFIN_PG_IRQ(2)
-#define IRQ_PG3			BFIN_PG_IRQ(3)
-#define IRQ_PG4			BFIN_PG_IRQ(4)
-#define IRQ_PG5			BFIN_PG_IRQ(5)
-#define IRQ_PG6			BFIN_PG_IRQ(6)
-#define IRQ_PG7			BFIN_PG_IRQ(7)
-#define IRQ_PG8			BFIN_PG_IRQ(8)
-#define IRQ_PG9			BFIN_PG_IRQ(9)
-#define IRQ_PG10		BFIN_PG_IRQ(10)
-#define IRQ_PG11		BFIN_PG_IRQ(11)
-#define IRQ_PG12		BFIN_PG_IRQ(12)
-#define IRQ_PG13		BFIN_PG_IRQ(13)
-#define IRQ_PG14		BFIN_PG_IRQ(14)
-#define IRQ_PG15		BFIN_PG_IRQ(15)
-
-#define GPIO_IRQ_BASE		IRQ_PA0
-
-#define NR_MACH_IRQS		(IRQ_PG15 + 1)
-
-#define SEC_SCTL_PRIO_OFFSET	8
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-extern u8 sec_int_priority[];
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
-	u32 mask_set;
-	u32 mask_clear;
-	u32 request;
-	u32 assign;
-	u32 edge_set;
-	u32 edge_clear;
-	u32 invert_set;
-	u32 invert_clear;
-	u32 pinstate;
-	u32 latch;
-	u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
deleted file mode 100644
index 20b65bfc5311..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/mem_map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BF60x memory map
- *
- * Copyright 2011 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE	0xBC000000	 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE	0x04000000	/* 64M */
-#define ASYNC_BANK2_BASE	0xB8000000	 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE	0x04000000	/* 64M */
-#define ASYNC_BANK1_BASE	0xB4000000	 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE	0x04000000	/* 64M */
-#define ASYNC_BANK0_BASE	0xB0000000	 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE	0x04000000	/* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START		0xC8000000
-#define BOOT_ROM_LENGTH		0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF60x processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE	(16*1024)
-#define L1_CODE_LENGTH      0x10000
-#else
-#define BFIN_ICACHESIZE	(0*1024)
-#define L1_CODE_LENGTH      0x14000
-#endif
-
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-
-#define COREA_L1_SCRATCH_START  0xFFB00000
-#define COREB_L1_SCRATCH_START  0xFF700000
-
-#define COREB_L1_CODE_START       0xFF600000
-#define COREB_L1_DATA_A_START     0xFF400000
-#define COREB_L1_DATA_B_START     0xFF500000
-
-#define COREB_L1_CODE_LENGTH     0x14000
-#define COREB_L1_DATA_A_LENGTH   0x8000
-#define COREB_L1_DATA_B_LENGTH   0x8000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE	(16*1024)
-#define BFIN_DSUPBANKS	1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE	(32*1024)
-#define BFIN_DSUPBANKS	2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE	(0*1024)
-#define BFIN_DSUPBANKS	0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START            0xC8080000
-#define L2_LENGTH           0x40000
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
deleted file mode 100644
index 1857a4a0f262..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
deleted file mode 100644
index a1efd936dd30..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __MACH_BF609_PM_H__
-#define __MACH_BF609_PM_H__
-
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-
-extern int bfin609_pm_enter(suspend_state_t state);
-extern int bf609_pm_prepare(void);
-extern void bf609_pm_finish(void);
-
-void bf609_hibernate(void);
-void bfin_sec_raise_irq(unsigned int sid);
-void coreb_enable(void);
-
-int bf609_nor_flash_init(struct platform_device *pdev);
-void bf609_nor_flash_exit(struct platform_device *pdev);
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
deleted file mode 100644
index c48bb71a55ce..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_MII0_PTPPPS	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_CRS, \
-	P_MII0_PTPPPS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, 0}
-
-#define P_MII1_MDC	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_MII1_PTPPPS	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-
-#define P_RMII1 {\
-	P_MII1_ETxD0, \
-	P_MII1_ETxD1, \
-	P_MII1_ETxEN, \
-	P_MII1_ERxD0, \
-	P_MII1_ERxD1, \
-	P_MII1_ERxER, \
-	P_MII1_TxCLK, \
-	P_MII1_PHYINT, \
-	P_MII1_CRS, \
-	P_MII1_PTPPPS, \
-	P_MII1_MDC, \
-	P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0	(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2	(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3	(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4	(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6	(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7	(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8	(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10	(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11	(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12	(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14	(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15	(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1	(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2	(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* CORE IDLE  */
-#define P_IDLEA		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_IDLEB		(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_SLEEP		(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-/* UART Port Mux */
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3		(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4		(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5		(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6		(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7		(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8		(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9		(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10		(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11		(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12		(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13		(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14		(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15		(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16		(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17		(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18		(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19		(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20		(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21		(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22		(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23		(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24		(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25		(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK         (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1		(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-/* CAN */
-#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-/* SPORT */
-#define P_SPORT0_ACLK	(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
-#define P_SPORT0_AFS	(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
-#define P_SPORT0_AD0	(P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
-#define P_SPORT0_AD1	(P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
-#define P_SPORT0_ATDV	(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
-#define P_SPORT0_BCLK	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
-#define P_SPORT0_BFS	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
-#define P_SPORT0_BD0	(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
-#define P_SPORT0_BD1	(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
-#define P_SPORT0_BTDV	(P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
-
-#define P_SPORT1_ACLK	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
-#define P_SPORT1_AFS	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
-#define P_SPORT1_AD0	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPORT1_AD1	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_SPORT1_ATDV	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_SPORT1_BCLK	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
-#define P_SPORT1_BFS	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
-#define P_SPORT1_BD0	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
-#define P_SPORT1_BD1	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
-#define P_SPORT1_BTDV	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-
-#define P_SPORT2_ACLK	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT2_AFS	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPORT2_AD0	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT2_AD1	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT2_ATDV	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
-#define P_SPORT2_BCLK	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT2_BFS	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT2_BD0	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPORT2_BD1	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT2_BTDV	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-
-/* LINK PORT */
-#define P_LP0_CLK	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
-#define P_LP0_ACK       (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
-#define P_LP0_D0        (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
-#define P_LP0_D1        (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
-#define P_LP0_D2        (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
-#define P_LP0_D3        (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
-#define P_LP0_D4        (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
-#define P_LP0_D5        (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
-#define P_LP0_D6        (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
-#define P_LP0_D7        (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
-
-#define P_LP1_CLK	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
-#define P_LP1_ACK       (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
-#define P_LP1_D0        (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
-#define P_LP1_D1        (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
-#define P_LP1_D2        (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
-#define P_LP1_D3        (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
-#define P_LP1_D4        (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
-#define P_LP1_D5        (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
-#define P_LP1_D6        (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
-#define P_LP1_D7        (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
-
-#define P_LP2_CLK	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
-#define P_LP2_ACK       (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
-#define P_LP2_D0        (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_LP2_D1        (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_LP2_D2        (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_LP2_D3        (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_LP2_D4        (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_LP2_D5        (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_LP2_D6        (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_LP2_D7        (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_LP3_CLK	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
-#define P_LP3_ACK       (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
-#define P_LP3_D0        (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_LP3_D1        (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_LP3_D2        (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_LP3_D3        (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_LP3_D4        (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_LP3_D5        (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_LP3_D6        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_LP3_D7        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-/* TWI */
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-#define P_TWI1_SCL	(P_DONTCARE)
-#define P_TWI1_SDA	(P_DONTCARE)
-
-/* Rotary Encoder */
-#define P_CNT_CZM	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
-#define P_CNT_CUD	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
-#define P_CNT_CDG	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
-
-#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
deleted file mode 100644
index f68abb9aa79e..000000000000
--- a/arch/blackfin/mach-bf609/ints-priority.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-u8 sec_int_priority[] = {
-	255,	/* IRQ_SEC_ERR */
-	255,	/* IRQ_CGU_EVT */
-	254,	/* IRQ_WATCH0 */
-	254,	/* IRQ_WATCH1 */
-	253,	/* IRQ_L2CTL0_ECC_ERR */
-	253,	/* IRQ_L2CTL0_ECC_WARN */
-	253,	/* IRQ_C0_DBL_FAULT */
-	253,	/* IRQ_C1_DBL_FAULT */
-	252,	/* IRQ_C0_HW_ERR */
-	252,	/* IRQ_C1_HW_ERR */
-	255,	/* IRQ_C0_NMI_L1_PARITY_ERR */
-	255,	/* IRQ_C1_NMI_L1_PARITY_ERR */
-
-	50,	/* IRQ_TIMER0 */
-	50,	/* IRQ_TIMER1 */
-	50,	/* IRQ_TIMER2 */
-	50,	/* IRQ_TIMER3 */
-	50,	/* IRQ_TIMER4 */
-	50,	/* IRQ_TIMER5 */
-	50,	/* IRQ_TIMER6 */
-	50,	/* IRQ_TIMER7 */
-	50,	/* IRQ_TIMER_STAT */
-	0,	/* IRQ_PINT0 */
-	0,	/* IRQ_PINT1 */
-	0,	/* IRQ_PINT2 */
-	0,	/* IRQ_PINT3 */
-	0,	/* IRQ_PINT4 */
-	0,	/* IRQ_PINT5 */
-	0,	/* IRQ_CNT */
-	50,	/* RQ_PWM0_TRIP */
-	50,	/* IRQ_PWM0_SYNC */
-	50,	/* IRQ_PWM1_TRIP */
-	50,	/* IRQ_PWM1_SYNC */
-	0,	/* IRQ_TWI0 */
-	0,	/* IRQ_TWI1 */
-	10,	/* IRQ_SOFT0 */
-	10,	/* IRQ_SOFT1 */
-	10,	/* IRQ_SOFT2 */
-	10,	/* IRQ_SOFT3 */
-	0,	/* IRQ_ACM_EVT_MISS */
-	0,	/* IRQ_ACM_EVT_COMPLETE */
-	0,	/* IRQ_CAN0_RX */
-	0,	/* IRQ_CAN0_TX */
-	0,	/* IRQ_CAN0_STAT */
-	100,	/* IRQ_SPORT0_TX */
-	100,	/* IRQ_SPORT0_TX_STAT */
-	100,	/* IRQ_SPORT0_RX */
-	100,	/* IRQ_SPORT0_RX_STAT */
-	100,	/* IRQ_SPORT1_TX */
-	100,	/* IRQ_SPORT1_TX_STAT */
-	100,	/* IRQ_SPORT1_RX */
-	100,	/* IRQ_SPORT1_RX_STAT */
-	100,	/* IRQ_SPORT2_TX */
-	100,	/* IRQ_SPORT2_TX_STAT */
-	100,	/* IRQ_SPORT2_RX */
-	100,	/* IRQ_SPORT2_RX_STAT */
-	0,	/* IRQ_SPI0_TX */
-	0,	/* IRQ_SPI0_RX */
-	0,	/* IRQ_SPI0_STAT */
-	0,	/* IRQ_SPI1_TX */
-	0,	/* IRQ_SPI1_RX */
-	0,	/* IRQ_SPI1_STAT */
-	0,	/* IRQ_RSI */
-	0,	/* IRQ_RSI_INT0 */
-	0,	/* IRQ_RSI_INT1 */
-	0,	/* DMA11 Data (SDU) */
-	0,	/* DMA12 Data (Reserved) */
-	0,	/* Reserved */
-	0,	/* Reserved */
-	30,	/* IRQ_EMAC0_STAT */
-	0,	/* EMAC0 Power (Reserved) */
-	30,	/* IRQ_EMAC1_STAT */
-	0,	/* EMAC1 Power (Reserved) */
-	0,	/* IRQ_LP0 */
-	0,	/* IRQ_LP0_STAT */
-	0,	/* IRQ_LP1 */
-	0,	/* IRQ_LP1_STAT */
-	0,	/* IRQ_LP2 */
-	0,	/* IRQ_LP2_STAT */
-	0,	/* IRQ_LP3 */
-	0,	/* IRQ_LP3_STAT */
-	0,	/* IRQ_UART0_TX */
-	0,	/* IRQ_UART0_RX */
-	0,	/* IRQ_UART0_STAT */
-	0,	/* IRQ_UART1_TX */
-	0,	/* IRQ_UART1_RX */
-	0,	/* IRQ_UART1_STAT */
-	0,	/* IRQ_MDMA0_SRC_CRC0 */
-	0,	/* IRQ_MDMA0_DEST_CRC0 */
-	0,	/* IRQ_CRC0_DCNTEXP */
-	0,	/* IRQ_CRC0_ERR */
-	0,	/* IRQ_MDMA1_SRC_CRC1 */
-	0,	/* IRQ_MDMA1_DEST_CRC1 */
-	0,	/* IRQ_CRC1_DCNTEXP */
-	0,	/* IRQ_CRC1_ERR */
-	0,	/* IRQ_MDMA2_SRC */
-	0,	/* IRQ_MDMA2_DEST */
-	0,	/* IRQ_MDMA3_SRC */
-	0,	/* IRQ_MDMA3_DEST */
-	120,	/* IRQ_EPPI0_CH0 */
-	120,	/* IRQ_EPPI0_CH1 */
-	120,	/* IRQ_EPPI0_STAT */
-	120,	/* IRQ_EPPI2_CH0 */
-	120,	/* IRQ_EPPI2_CH1 */
-	120,	/* IRQ_EPPI2_STAT */
-	120,	/* IRQ_EPPI1_CH0 */
-	120,	/* IRQ_EPPI1_CH1 */
-	120,	/* IRQ_EPPI1_STAT */
-	120,	/* IRQ_PIXC_CH0 */
-	120,	/* IRQ_PIXC_CH1 */
-	120,	/* IRQ_PIXC_CH2 */
-	120,	/* IRQ_PIXC_STAT */
-	120,	/* IRQ_PVP_CPDOB */
-	120,	/* IRQ_PVP_CPDOC */
-	120,	/* IRQ_PVP_CPSTAT */
-	120,	/* IRQ_PVP_CPCI */
-	120,	/* IRQ_PVP_STAT0 */
-	120,	/* IRQ_PVP_MPDO */
-	120,	/* IRQ_PVP_MPDI */
-	120,	/* IRQ_PVP_MPSTAT */
-	120,	/* IRQ_PVP_MPCI */
-	120,	/* IRQ_PVP_CPDOA */
-	120,	/* IRQ_PVP_STAT1 */
-	0,	/* IRQ_USB_STAT */
-	0,	/* IRQ_USB_DMA */
-	0,	/* IRQ_TRU_INT0 */
-	0,	/* IRQ_TRU_INT1 */
-	0,	/* IRQ_TRU_INT2	*/
-	0,	/* IRQ_TRU_INT3 */
-	0,	/* IRQ_DMAC0_ERROR */
-	0,	/* IRQ_CGU0_ERROR */
-	0,	/* Reserved */
-	0,	/* IRQ_DPM */
-	0,	/* Reserved */
-	0,	/* IRQ_SWU0 */
-	0,	/* IRQ_SWU1 */
-	0,	/* IRQ_SWU2 */
-	0,	/* IRQ_SWU3 */
-	0,	/* IRQ_SWU4 */
-	0,	/* IRQ_SWU4 */
-	0,	/* IRQ_SWU6 */
-};
-
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
deleted file mode 100644
index b1bfcf434d16..000000000000
--- a/arch/blackfin/mach-bf609/pm.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <mach/pm.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-
-/***********************************************************/
-/*                                                         */
-/* Wakeup Actions for DPM_RESTORE                          */
-/*                                                         */
-/***********************************************************/
-#define BITP_ROM_WUA_CHKHDR             24
-#define BITP_ROM_WUA_DDRLOCK            7
-#define BITP_ROM_WUA_DDRDLLEN           6
-#define BITP_ROM_WUA_DDR                5
-#define BITP_ROM_WUA_CGU                4
-#define BITP_ROM_WUA_MEMBOOT            2
-#define BITP_ROM_WUA_EN                 1
-
-#define BITM_ROM_WUA_CHKHDR             (0xFF000000)
-#define ENUM_ROM_WUA_CHKHDR_AD                  0xAD000000
-
-#define BITM_ROM_WUA_DDRLOCK            (0x00000080)
-#define BITM_ROM_WUA_DDRDLLEN           (0x00000040)
-#define BITM_ROM_WUA_DDR                (0x00000020)
-#define BITM_ROM_WUA_CGU                (0x00000010)
-#define BITM_ROM_WUA_MEMBOOT            (0x00000002)
-#define BITM_ROM_WUA_EN                 (0x00000001)
-
-/***********************************************************/
-/*                                                         */
-/* Syscontrol                                              */
-/*                                                         */
-/***********************************************************/
-#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN  28    /* unlocks CGU_CTL register */
-#define BITP_ROM_SYSCTRL_WUA_OVERRIDE   24
-#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN   20    /* Saves the DDR DLL and PADS registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DDR        19    /* Saves the DDR registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_CGU        18    /* Saves the CGU registers into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DPMWRITE   17    /* Saves the Syscontrol structure structure contents into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_EN         16    /* reads current PLL and DDR configuration into structure */
-#define BITP_ROM_SYSCTRL_DDR_WRITE      13    /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
-#define BITP_ROM_SYSCTRL_DDR_READ       12    /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
-#define BITP_ROM_SYSCTRL_CGU_AUTODIS    11    /* Disables auto handling of UPDT and ALGN fields */
-#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL  7    /* access CGU_CLKOUTSEL register */
-#define BITP_ROM_SYSCTRL_CGU_DIV        6    /* access CGU_DIV register */
-#define BITP_ROM_SYSCTRL_CGU_STAT       5    /* access CGU_STAT register */
-#define BITP_ROM_SYSCTRL_CGU_CTL        4    /* access CGU_CTL register */
-#define BITP_ROM_SYSCTRL_CGU_RTNSTAT    2    /* Update structure STAT field upon error */
-#define BITP_ROM_SYSCTRL_WRITE          1    /* write registers */
-#define BITP_ROM_SYSCTRL_READ           0    /* read registers */
-
-#define BITM_ROM_SYSCTRL_CGU_READ       (0x00000001)    /* Read CGU registers */
-#define BITM_ROM_SYSCTRL_CGU_WRITE      (0x00000002)    /* Write registers */
-#define BITM_ROM_SYSCTRL_CGU_RTNSTAT    (0x00000004)    /* Update structure STAT field upon error or after a write operation */
-#define BITM_ROM_SYSCTRL_CGU_CTL        (0x00000010)    /* Access CGU_CTL register */
-#define BITM_ROM_SYSCTRL_CGU_STAT       (0x00000020)    /* Access CGU_STAT register */
-#define BITM_ROM_SYSCTRL_CGU_DIV        (0x00000040)    /* Access CGU_DIV register */
-#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL  (0x00000080)    /* Access CGU_CLKOUTSEL register */
-#define BITM_ROM_SYSCTRL_CGU_AUTODIS    (0x00000800)    /* Disables auto handling of UPDT and ALGN fields */
-#define BITM_ROM_SYSCTRL_DDR_READ       (0x00001000)    /* Reads the contents of the DDR registers and stores them into the structure */
-#define BITM_ROM_SYSCTRL_DDR_WRITE      (0x00002000)    /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
-#define BITM_ROM_SYSCTRL_WUA_EN         (0x00010000)    /* Wakeup entry or exit opertation enable */
-#define BITM_ROM_SYSCTRL_WUA_DPMWRITE   (0x00020000)    /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
-#define BITM_ROM_SYSCTRL_WUA_CGU        (0x00040000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDR        (0x00080000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN   (0x00100000)    /* Enables saving/restoring of the DDR DLLCTL register */
-#define BITM_ROM_SYSCTRL_WUA_OVERRIDE   (0x01000000)
-#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN  (0x10000000)    /* Unlocks the CGU_CTL register */
-
-
-/* Structures for the syscontrol() function */
-struct STRUCT_ROM_SYSCTRL {
-	uint32_t ulCGU_CTL;
-	uint32_t ulCGU_STAT;
-	uint32_t ulCGU_DIV;
-	uint32_t ulCGU_CLKOUTSEL;
-	uint32_t ulWUA_Flags;
-	uint32_t ulWUA_BootAddr;
-	uint32_t ulWUA_User;
-	uint32_t ulDDR_CTL;
-	uint32_t ulDDR_CFG;
-	uint32_t ulDDR_TR0;
-	uint32_t ulDDR_TR1;
-	uint32_t ulDDR_TR2;
-	uint32_t ulDDR_MR;
-	uint32_t ulDDR_EMR1;
-	uint32_t ulDDR_EMR2;
-	uint32_t ulDDR_PADCTL;
-	uint32_t ulDDR_DLLCTL;
-	uint32_t ulReserved;
-};
-
-struct bfin_pm_data {
-	uint32_t magic;
-	uint32_t resume_addr;
-	uint32_t sp;
-};
-
-struct bfin_pm_data bf609_pm_data;
-
-struct STRUCT_ROM_SYSCTRL configvalues;
-uint32_t dactionflags;
-
-#define FUNC_ROM_SYSCONTROL 0xC8000080
-__attribute__((l1_data))
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
-
-__attribute__((l1_text))
-void bfin_cpu_suspend(void)
-{
-	__asm__ __volatile__( \
-			".align 8;" \
-			"idle;" \
-			: : \
-			);
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr(void)
-{
-	dmc_enter_self_refresh();
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
-{
-	dmc_exit_self_refresh();
-
-	/* After wake up from deep sleep and exit DDR from self refress mode,
-	 * should wait till CGU PLL is locked.
-	 */
-	while (bfin_read32(CGU0_STAT) & CLKSALGN)
-		continue;
-}
-
-__attribute__((l1_text))
-void bf609_resume_ccbuf(void)
-{
-	bfin_write32(DPM0_CCBF_EN, 3);
-	bfin_write32(DPM0_CTL, 2);
-
-	while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
-}
-
-__attribute__((l1_text))
-void bfin_hibernate_syscontrol(void)
-{
-	configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
-		| BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
-
-	dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
-		| BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
-		| BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
-
-	bfrom_SysControl(dactionflags, &configvalues, NULL);
-
-	bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
-}
-
-asmlinkage void enter_deepsleep(void);
-
-__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
-{
-	bfin_write32(DPM0_WAKE_EN, mask);
-	bfin_write32(DPM0_WAKE_POL, pol_mask);
-	SSYNC();
-	enter_deepsleep();
-}
-
-void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
-{
-	bfin_write32(DPM0_WAKE_EN, mask);
-	bfin_write32(DPM0_WAKE_POL, pol_mask);
-	bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
-	bfin_write32(DPM0_HIB_DIS, 0xFFFF);
-
-	bf609_hibernate();
-}
-
-void bf609_cpu_pm_enter(suspend_state_t state)
-{
-	int error;
-	unsigned long wakeup = 0;
-	unsigned long wakeup_pol = 0;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PA15
-	wakeup |= PA15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
-	wakeup_pol |= PA15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PB15
-	wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PB15_POL
-	wakeup_pol |= PB15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PC15
-	wakeup |= PC15WE;
-# if CONFIG_PM_BFIN_WAKE_PC15_POL
-	wakeup_pol |= PC15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PD06
-	wakeup |= PD06WE;
-# if CONFIG_PM_BFIN_WAKE_PD06_POL
-	wakeup_pol |= PD06WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
-	wakeup |= PE12WE;
-# if CONFIG_PM_BFIN_WAKE_PE12_POL
-	wakeup_pol |= PE12WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG04
-	wakeup |= PG04WE;
-# if CONFIG_PM_BFIN_WAKE_PG04_POL
-	wakeup_pol |= PG04WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG13
-	wakeup |= PG13WE;
-# if CONFIG_PM_BFIN_WAKE_PG13_POL
-	wakeup_pol |= PG13WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_USB
-	wakeup |= USBWE;
-# if CONFIG_PM_BFIN_WAKE_USB_POL
-	wakeup_pol |= USBWE;
-# endif
-#endif
-
-	error = irq_set_irq_wake(255, 1);
-	if(error < 0)
-		printk(KERN_DEBUG "Unable to get irq wake\n");
-	error = irq_set_irq_wake(231, 1);
-	if (error < 0)
-		printk(KERN_DEBUG "Unable to get irq wake\n");
-
-	if (state == PM_SUSPEND_STANDBY)
-		bfin_deepsleep(wakeup, wakeup_pol);
-	else {
-		bfin_hibernate(wakeup, wakeup_pol);
-	}
-
-}
-
-int bf609_cpu_pm_prepare(void)
-{
-	return 0;
-}
-
-void bf609_cpu_pm_finish(void)
-{
-
-}
-
-static struct bfin_cpu_pm_fns bf609_cpu_pm = {
-	.enter          = bf609_cpu_pm_enter,
-	.prepare        = bf609_cpu_pm_prepare,
-	.finish         = bf609_cpu_pm_finish,
-};
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static int smc_pm_syscore_suspend(void)
-{
-	bf609_nor_flash_exit(NULL);
-	return 0;
-}
-
-static void smc_pm_syscore_resume(void)
-{
-	bf609_nor_flash_init(NULL);
-}
-
-static struct syscore_ops smc_pm_syscore_ops = {
-	.suspend        = smc_pm_syscore_suspend,
-	.resume         = smc_pm_syscore_resume,
-};
-#endif
-
-static irqreturn_t test_isr(int irq, void *dev_id)
-{
-	printk(KERN_DEBUG "gpio irq %d\n", irq);
-	if (irq == 231)
-		bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1));
-	return IRQ_HANDLED;
-}
-
-static irqreturn_t dpm0_isr(int irq, void *dev_id)
-{
-	bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
-	bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
-	return IRQ_HANDLED;
-}
-
-static int __init bf609_init_pm(void)
-{
-	int irq;
-	int error;
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-	register_syscore_ops(&smc_pm_syscore_ops);
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
-	irq = gpio_to_irq(GPIO_PE12);
-	if (irq < 0) {
-		error = irq;
-		printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
-				GPIO_PE12, error);
-	}
-
-	error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
-				| IRQF_FORCE_RESUME, "gpiope12", NULL);
-	if(error < 0)
-		printk(KERN_DEBUG "Unable to get irq\n");
-#endif
-
-	error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
-				IRQF_FORCE_RESUME, "cgu0 event", NULL);
-	if(error < 0)
-		printk(KERN_DEBUG "Unable to get irq\n");
-
-	error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
-				IRQF_FORCE_RESUME, "dpm0 event", NULL);
-	if (error < 0)
-		printk(KERN_DEBUG "Unable to get irq\n");
-
-	bfin_cpu_pm = &bf609_cpu_pm;
-	return 0;
-}
-
-late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c
deleted file mode 100644
index ac1f07c33594..000000000000
--- a/arch/blackfin/mach-bf609/scb.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/scb.h>
-
-struct scb_mi_prio scb_data[] = {
-#ifdef CONFIG_SCB0_MI0
-	{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
-		CONFIG_SCB0_MI0_SLOT0,
-		CONFIG_SCB0_MI0_SLOT1,
-		CONFIG_SCB0_MI0_SLOT2,
-		CONFIG_SCB0_MI0_SLOT3,
-		CONFIG_SCB0_MI0_SLOT4,
-		CONFIG_SCB0_MI0_SLOT5,
-		CONFIG_SCB0_MI0_SLOT6,
-		CONFIG_SCB0_MI0_SLOT7,
-		CONFIG_SCB0_MI0_SLOT8,
-		CONFIG_SCB0_MI0_SLOT9,
-		CONFIG_SCB0_MI0_SLOT10,
-		CONFIG_SCB0_MI0_SLOT11,
-		CONFIG_SCB0_MI0_SLOT12,
-		CONFIG_SCB0_MI0_SLOT13,
-		CONFIG_SCB0_MI0_SLOT14,
-		CONFIG_SCB0_MI0_SLOT15,
-		CONFIG_SCB0_MI0_SLOT16,
-		CONFIG_SCB0_MI0_SLOT17,
-		CONFIG_SCB0_MI0_SLOT18,
-		CONFIG_SCB0_MI0_SLOT19,
-		CONFIG_SCB0_MI0_SLOT20,
-		CONFIG_SCB0_MI0_SLOT21,
-		CONFIG_SCB0_MI0_SLOT22,
-		CONFIG_SCB0_MI0_SLOT23,
-		CONFIG_SCB0_MI0_SLOT24,
-		CONFIG_SCB0_MI0_SLOT25,
-		CONFIG_SCB0_MI0_SLOT26,
-		CONFIG_SCB0_MI0_SLOT27,
-		CONFIG_SCB0_MI0_SLOT28,
-		CONFIG_SCB0_MI0_SLOT29,
-		CONFIG_SCB0_MI0_SLOT30,
-		CONFIG_SCB0_MI0_SLOT31
-		},
-	},
-#endif
-#ifdef CONFIG_SCB0_MI1
-	{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
-		CONFIG_SCB0_MI1_SLOT0,
-		CONFIG_SCB0_MI1_SLOT1,
-		CONFIG_SCB0_MI1_SLOT2,
-		CONFIG_SCB0_MI1_SLOT3,
-		CONFIG_SCB0_MI1_SLOT4,
-		CONFIG_SCB0_MI1_SLOT5,
-		CONFIG_SCB0_MI1_SLOT6,
-		CONFIG_SCB0_MI1_SLOT7,
-		CONFIG_SCB0_MI1_SLOT8,
-		CONFIG_SCB0_MI1_SLOT9,
-		CONFIG_SCB0_MI1_SLOT10,
-		CONFIG_SCB0_MI1_SLOT11,
-		CONFIG_SCB0_MI1_SLOT12,
-		CONFIG_SCB0_MI1_SLOT13,
-		CONFIG_SCB0_MI1_SLOT14,
-		CONFIG_SCB0_MI1_SLOT15,
-		CONFIG_SCB0_MI1_SLOT16,
-		CONFIG_SCB0_MI1_SLOT17,
-		CONFIG_SCB0_MI1_SLOT18,
-		CONFIG_SCB0_MI1_SLOT19,
-		CONFIG_SCB0_MI1_SLOT20,
-		CONFIG_SCB0_MI1_SLOT21,
-		CONFIG_SCB0_MI1_SLOT22,
-		CONFIG_SCB0_MI1_SLOT23,
-		CONFIG_SCB0_MI1_SLOT24,
-		CONFIG_SCB0_MI1_SLOT25,
-		CONFIG_SCB0_MI1_SLOT26,
-		CONFIG_SCB0_MI1_SLOT27,
-		CONFIG_SCB0_MI1_SLOT28,
-		CONFIG_SCB0_MI1_SLOT29,
-		CONFIG_SCB0_MI1_SLOT30,
-		CONFIG_SCB0_MI1_SLOT31
-		},
-	},
-#endif
-#ifdef CONFIG_SCB0_MI2
-	{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
-		CONFIG_SCB0_MI2_SLOT0,
-		CONFIG_SCB0_MI2_SLOT1,
-		CONFIG_SCB0_MI2_SLOT2,
-		CONFIG_SCB0_MI2_SLOT3,
-		CONFIG_SCB0_MI2_SLOT4,
-		CONFIG_SCB0_MI2_SLOT5,
-		CONFIG_SCB0_MI2_SLOT6,
-		CONFIG_SCB0_MI2_SLOT7,
-		CONFIG_SCB0_MI2_SLOT8,
-		CONFIG_SCB0_MI2_SLOT9,
-		CONFIG_SCB0_MI2_SLOT10,
-		CONFIG_SCB0_MI2_SLOT11,
-		CONFIG_SCB0_MI2_SLOT12,
-		CONFIG_SCB0_MI2_SLOT13,
-		CONFIG_SCB0_MI2_SLOT14,
-		CONFIG_SCB0_MI2_SLOT15,
-		CONFIG_SCB0_MI2_SLOT16,
-		CONFIG_SCB0_MI2_SLOT17,
-		CONFIG_SCB0_MI2_SLOT18,
-		CONFIG_SCB0_MI2_SLOT19,
-		CONFIG_SCB0_MI2_SLOT20,
-		CONFIG_SCB0_MI2_SLOT21,
-		CONFIG_SCB0_MI2_SLOT22,
-		CONFIG_SCB0_MI2_SLOT23,
-		CONFIG_SCB0_MI2_SLOT24,
-		CONFIG_SCB0_MI2_SLOT25,
-		CONFIG_SCB0_MI2_SLOT26,
-		CONFIG_SCB0_MI2_SLOT27,
-		CONFIG_SCB0_MI2_SLOT28,
-		CONFIG_SCB0_MI2_SLOT29,
-		CONFIG_SCB0_MI2_SLOT30,
-		CONFIG_SCB0_MI2_SLOT31
-		},
-	},
-#endif
-#ifdef CONFIG_SCB0_MI3
-	{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
-		CONFIG_SCB0_MI3_SLOT0,
-		CONFIG_SCB0_MI3_SLOT1,
-		CONFIG_SCB0_MI3_SLOT2,
-		CONFIG_SCB0_MI3_SLOT3,
-		CONFIG_SCB0_MI3_SLOT4,
-		CONFIG_SCB0_MI3_SLOT5,
-		CONFIG_SCB0_MI3_SLOT6,
-		CONFIG_SCB0_MI3_SLOT7,
-		CONFIG_SCB0_MI3_SLOT8,
-		CONFIG_SCB0_MI3_SLOT9,
-		CONFIG_SCB0_MI3_SLOT10,
-		CONFIG_SCB0_MI3_SLOT11,
-		CONFIG_SCB0_MI3_SLOT12,
-		CONFIG_SCB0_MI3_SLOT13,
-		CONFIG_SCB0_MI3_SLOT14,
-		CONFIG_SCB0_MI3_SLOT15,
-		CONFIG_SCB0_MI3_SLOT16,
-		CONFIG_SCB0_MI3_SLOT17,
-		CONFIG_SCB0_MI3_SLOT18,
-		CONFIG_SCB0_MI3_SLOT19,
-		CONFIG_SCB0_MI3_SLOT20,
-		CONFIG_SCB0_MI3_SLOT21,
-		CONFIG_SCB0_MI3_SLOT22,
-		CONFIG_SCB0_MI3_SLOT23,
-		CONFIG_SCB0_MI3_SLOT24,
-		CONFIG_SCB0_MI3_SLOT25,
-		CONFIG_SCB0_MI3_SLOT26,
-		CONFIG_SCB0_MI3_SLOT27,
-		CONFIG_SCB0_MI3_SLOT28,
-		CONFIG_SCB0_MI3_SLOT29,
-		CONFIG_SCB0_MI3_SLOT30,
-		CONFIG_SCB0_MI3_SLOT31
-		},
-	},
-#endif
-#ifdef CONFIG_SCB0_MI4
-	{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
-		CONFIG_SCB0_MI4_SLOT0,
-		CONFIG_SCB0_MI4_SLOT1,
-		CONFIG_SCB0_MI4_SLOT2,
-		CONFIG_SCB0_MI4_SLOT3,
-		CONFIG_SCB0_MI4_SLOT4,
-		CONFIG_SCB0_MI4_SLOT5,
-		CONFIG_SCB0_MI4_SLOT6,
-		CONFIG_SCB0_MI4_SLOT7,
-		CONFIG_SCB0_MI4_SLOT8,
-		CONFIG_SCB0_MI4_SLOT9,
-		CONFIG_SCB0_MI4_SLOT10,
-		CONFIG_SCB0_MI4_SLOT11,
-		CONFIG_SCB0_MI4_SLOT12,
-		CONFIG_SCB0_MI4_SLOT13,
-		CONFIG_SCB0_MI4_SLOT14,
-		CONFIG_SCB0_MI4_SLOT15,
-		CONFIG_SCB0_MI4_SLOT16,
-		CONFIG_SCB0_MI4_SLOT17,
-		CONFIG_SCB0_MI4_SLOT18,
-		CONFIG_SCB0_MI4_SLOT19,
-		CONFIG_SCB0_MI4_SLOT20,
-		CONFIG_SCB0_MI4_SLOT21,
-		CONFIG_SCB0_MI4_SLOT22,
-		CONFIG_SCB0_MI4_SLOT23,
-		CONFIG_SCB0_MI4_SLOT24,
-		CONFIG_SCB0_MI4_SLOT25,
-		CONFIG_SCB0_MI4_SLOT26,
-		CONFIG_SCB0_MI4_SLOT27,
-		CONFIG_SCB0_MI4_SLOT28,
-		CONFIG_SCB0_MI4_SLOT29,
-		CONFIG_SCB0_MI4_SLOT30,
-		CONFIG_SCB0_MI4_SLOT31
-		},
-	},
-#endif
-#ifdef CONFIG_SCB0_MI5
-	{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
-		CONFIG_SCB0_MI5_SLOT0,
-		CONFIG_SCB0_MI5_SLOT1,
-		CONFIG_SCB0_MI5_SLOT2,
-		CONFIG_SCB0_MI5_SLOT3,
-		CONFIG_SCB0_MI5_SLOT4,
-		CONFIG_SCB0_MI5_SLOT5,
-		CONFIG_SCB0_MI5_SLOT6,
-		CONFIG_SCB0_MI5_SLOT7,
-		CONFIG_SCB0_MI5_SLOT8,
-		CONFIG_SCB0_MI5_SLOT9,
-		CONFIG_SCB0_MI5_SLOT10,
-		CONFIG_SCB0_MI5_SLOT11,
-		CONFIG_SCB0_MI5_SLOT12,
-		CONFIG_SCB0_MI5_SLOT13,
-		CONFIG_SCB0_MI5_SLOT14,
-		CONFIG_SCB0_MI5_SLOT15
-		},
-	},
-#endif
-#ifdef CONFIG_SCB1_MI0
-	{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
-		CONFIG_SCB1_MI0_SLOT0,
-		CONFIG_SCB1_MI0_SLOT1,
-		CONFIG_SCB1_MI0_SLOT2,
-		CONFIG_SCB1_MI0_SLOT3,
-		CONFIG_SCB1_MI0_SLOT4,
-		CONFIG_SCB1_MI0_SLOT5,
-		CONFIG_SCB1_MI0_SLOT6,
-		CONFIG_SCB1_MI0_SLOT7,
-		CONFIG_SCB1_MI0_SLOT8,
-		CONFIG_SCB1_MI0_SLOT9,
-		CONFIG_SCB1_MI0_SLOT10,
-		CONFIG_SCB1_MI0_SLOT11,
-		CONFIG_SCB1_MI0_SLOT12,
-		CONFIG_SCB1_MI0_SLOT13,
-		CONFIG_SCB1_MI0_SLOT14,
-		CONFIG_SCB1_MI0_SLOT15,
-		CONFIG_SCB1_MI0_SLOT16,
-		CONFIG_SCB1_MI0_SLOT17,
-		CONFIG_SCB1_MI0_SLOT18,
-		CONFIG_SCB1_MI0_SLOT19
-		},
-	},
-#endif
-#ifdef CONFIG_SCB2_MI0
-	{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
-		CONFIG_SCB2_MI0_SLOT0,
-		CONFIG_SCB2_MI0_SLOT1,
-		CONFIG_SCB2_MI0_SLOT2,
-		CONFIG_SCB2_MI0_SLOT3,
-		CONFIG_SCB2_MI0_SLOT4,
-		CONFIG_SCB2_MI0_SLOT5,
-		CONFIG_SCB2_MI0_SLOT6,
-		CONFIG_SCB2_MI0_SLOT7,
-		CONFIG_SCB2_MI0_SLOT8,
-		CONFIG_SCB2_MI0_SLOT9
-		},
-	},
-#endif
-#ifdef CONFIG_SCB3_MI0
-	{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
-		CONFIG_SCB3_MI0_SLOT0,
-		CONFIG_SCB3_MI0_SLOT1,
-		CONFIG_SCB3_MI0_SLOT2,
-		CONFIG_SCB3_MI0_SLOT3,
-		CONFIG_SCB3_MI0_SLOT4,
-		CONFIG_SCB3_MI0_SLOT5,
-		CONFIG_SCB3_MI0_SLOT6,
-		CONFIG_SCB3_MI0_SLOT7,
-		CONFIG_SCB3_MI0_SLOT8,
-		CONFIG_SCB3_MI0_SLOT9,
-		CONFIG_SCB3_MI0_SLOT10,
-		CONFIG_SCB3_MI0_SLOT11,
-		CONFIG_SCB3_MI0_SLOT12,
-		CONFIG_SCB3_MI0_SLOT13,
-		CONFIG_SCB3_MI0_SLOT14,
-		CONFIG_SCB3_MI0_SLOT15
-		},
-	},
-#endif
-#ifdef CONFIG_SCB4_MI0
-	{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
-		CONFIG_SCB4_MI0_SLOT0,
-		CONFIG_SCB4_MI0_SLOT1,
-		CONFIG_SCB4_MI0_SLOT2,
-		CONFIG_SCB4_MI0_SLOT3,
-		CONFIG_SCB4_MI0_SLOT4,
-		CONFIG_SCB4_MI0_SLOT5,
-		CONFIG_SCB4_MI0_SLOT6,
-		CONFIG_SCB4_MI0_SLOT7,
-		CONFIG_SCB4_MI0_SLOT8,
-		CONFIG_SCB4_MI0_SLOT9,
-		CONFIG_SCB4_MI0_SLOT10,
-		CONFIG_SCB4_MI0_SLOT11,
-		CONFIG_SCB4_MI0_SLOT12,
-		CONFIG_SCB4_MI0_SLOT13,
-		CONFIG_SCB4_MI0_SLOT14,
-		CONFIG_SCB4_MI0_SLOT15
-		},
-	},
-#endif
-#ifdef CONFIG_SCB5_MI0
-	{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
-		CONFIG_SCB5_MI0_SLOT0,
-		CONFIG_SCB5_MI0_SLOT1,
-		CONFIG_SCB5_MI0_SLOT2,
-		CONFIG_SCB5_MI0_SLOT3,
-		CONFIG_SCB5_MI0_SLOT4,
-		CONFIG_SCB5_MI0_SLOT5,
-		CONFIG_SCB5_MI0_SLOT6,
-		CONFIG_SCB5_MI0_SLOT7
-		},
-	},
-#endif
-#ifdef CONFIG_SCB6_MI0
-	{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
-		CONFIG_SCB6_MI0_SLOT0,
-		CONFIG_SCB6_MI0_SLOT1,
-		CONFIG_SCB6_MI0_SLOT2,
-		CONFIG_SCB6_MI0_SLOT3
-		},
-	},
-#endif
-#ifdef CONFIG_SCB7_MI0
-	{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
-		CONFIG_SCB7_MI0_SLOT0,
-		CONFIG_SCB7_MI0_SLOT1,
-		CONFIG_SCB7_MI0_SLOT2,
-		CONFIG_SCB7_MI0_SLOT3,
-		CONFIG_SCB7_MI0_SLOT4,
-		CONFIG_SCB7_MI0_SLOT5
-		},
-	},
-#endif
-#ifdef CONFIG_SCB8_MI0
-	{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
-		CONFIG_SCB8_MI0_SLOT0,
-		CONFIG_SCB8_MI0_SLOT1,
-		CONFIG_SCB8_MI0_SLOT2,
-		CONFIG_SCB8_MI0_SLOT3,
-		CONFIG_SCB8_MI0_SLOT4,
-		CONFIG_SCB8_MI0_SLOT5,
-		CONFIG_SCB8_MI0_SLOT6,
-		CONFIG_SCB8_MI0_SLOT7
-		},
-	},
-#endif
-#ifdef CONFIG_SCB9_MI0
-	{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
-		CONFIG_SCB9_MI0_SLOT0,
-		CONFIG_SCB9_MI0_SLOT1,
-		CONFIG_SCB9_MI0_SLOT2,
-		CONFIG_SCB9_MI0_SLOT3,
-		CONFIG_SCB9_MI0_SLOT4,
-		CONFIG_SCB9_MI0_SLOT5,
-		CONFIG_SCB9_MI0_SLOT6,
-		CONFIG_SCB9_MI0_SLOT7,
-		CONFIG_SCB9_MI0_SLOT8,
-		CONFIG_SCB9_MI0_SLOT9
-		},
-	},
-#endif
-	{ 0, }
-};