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| author | Takashi Iwai <tiwai@suse.de> | 2009-12-14 20:01:56 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2009-12-14 20:01:56 +0300 |
| commit | b89371621e5bedc84498ced2c5c33976bd1b2f64 (patch) | |
| tree | b309919239586e25617a17785b827577b1abb6b5 /arch/blackfin/mach-bf548/include/mach/defBF547.h | |
| parent | 63978ab3e3e963db28093b53bb4598f2702e1ad7 (diff) | |
| parent | 74c2b45b714e49b427584b4bd8f44f1a24d82d9c (diff) | |
| download | linux-b89371621e5bedc84498ced2c5c33976bd1b2f64.tar.xz | |
Merge branch 'next/isa' into topic/misc
Diffstat (limited to 'arch/blackfin/mach-bf548/include/mach/defBF547.h')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF547.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h index 5a9dbabe0a68..c4dcf302d9f5 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -470,7 +470,7 @@ #define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ #define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ #define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ #define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ #define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ @@ -480,7 +480,7 @@ #define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ #define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ #define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ #define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ #define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ |