diff options
| author | Graf Yang <graf.yang@analog.com> | 2008-11-18 12:48:22 +0300 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-11-18 12:48:22 +0300 |
| commit | b8a989893cbdeb6c97a7b5af5f38fb0e480235f9 (patch) | |
| tree | 658cf6df93dac687f0d6b94111d0f53b3dd0177c /arch/blackfin/include/asm/cplb-mpu.h | |
| parent | 6b3087c64a92a36ae20d33479b4df6d7afc910d4 (diff) | |
| download | linux-b8a989893cbdeb6c97a7b5af5f38fb0e480235f9.tar.xz | |
Blackfin arch: SMP supporting patchset: Blackfin CPLB related code
Blackfin dual core BF561 processor can support SMP like features.
https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like
In this patch, we provide SMP extend to Blackfin CPLB related code
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include/asm/cplb-mpu.h')
| -rw-r--r-- | arch/blackfin/include/asm/cplb-mpu.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h index 75c67b99d607..80680ad7a378 100644 --- a/arch/blackfin/include/asm/cplb-mpu.h +++ b/arch/blackfin/include/asm/cplb-mpu.h @@ -28,6 +28,7 @@ */ #ifndef __ASM_BFIN_CPLB_MPU_H #define __ASM_BFIN_CPLB_MPU_H +#include <linux/threads.h> struct cplb_entry { unsigned long data, addr; @@ -39,22 +40,22 @@ struct mem_region { unsigned long icplb_data; }; -extern struct cplb_entry dcplb_tbl[MAX_CPLBS]; -extern struct cplb_entry icplb_tbl[MAX_CPLBS]; +extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; +extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; extern int first_switched_icplb; extern int first_mask_dcplb; extern int first_switched_dcplb; -extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; -extern int nr_cplb_flush; +extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[]; +extern int nr_dcplb_prot[], nr_cplb_flush[]; extern int page_mask_order; extern int page_mask_nelts; -extern unsigned long *current_rwx_mask; +extern unsigned long *current_rwx_mask[NR_CPUS]; -extern void flush_switched_cplbs(void); -extern void set_mask_dcplbs(unsigned long *); +extern void flush_switched_cplbs(unsigned int); +extern void set_mask_dcplbs(unsigned long *, unsigned int); extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); |