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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-02-03 23:05:13 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-02-09 19:34:48 +0400
commita22db0f38243f68957c89b1b9689a2064507bed6 (patch)
treebf6f6c2b19f247a46c12b943aa8d09d108f49c6b /arch/arm
parent29c140b623ce2c55131c6d1c26a2f3e455723b81 (diff)
downloadlinux-a22db0f38243f68957c89b1b9689a2064507bed6.tar.xz
ARM: sa1111: fix PWM state on suspend
We should not write to the SA1111 registers after setting the SLEEP bit. Moreover, the manual says that the PWM registers should be disabled before we enter sleep. So, move the clearing of these registers earlier in the suspend sequence. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/common/sa1111.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index c7bed309b3aa..f0d9faadcc3f 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -905,6 +905,9 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state)
save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0);
save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1);
+ sa1111_writel(0, sachip->base + SA1111_SKPWM0);
+ sa1111_writel(0, sachip->base + SA1111_SKPWM1);
+
base = sachip->base + SA1111_INTC;
save->intpol0 = sa1111_readl(base + SA1111_INTPOL0);
save->intpol1 = sa1111_readl(base + SA1111_INTPOL1);
@@ -920,8 +923,6 @@ static int sa1111_suspend(struct platform_device *dev, pm_message_t state)
*/
val = sa1111_readl(sachip->base + SA1111_SKCR);
sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
- sa1111_writel(0, sachip->base + SA1111_SKPWM0);
- sa1111_writel(0, sachip->base + SA1111_SKPWM1);
clk_disable(sachip->clk);