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author | Gabriel Fernandez <gabriel.fernandez@st.com> | 2017-03-23 19:35:50 +0300 |
---|---|---|
committer | Alexandre TORGUE <alexandre.torgue@st.com> | 2017-03-23 20:18:22 +0300 |
commit | 01e435d23b18621972097bbfb30a55be258b1ea2 (patch) | |
tree | 32021479df9301978c8a2d5255e0bd2f2cc91a64 /arch/arm | |
parent | c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff) | |
download | linux-01e435d23b18621972097bbfb30a55be258b1ea2.tar.xz |
ARM: dts: stm32: Enable clocks for STM32F746 MCU
This patch enables clocks for STM32F746 MCU.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/stm32f746.dtsi | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index f321ffe87144..e05e131d07fe 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -43,6 +43,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/pinctrl/stm32f746-pinfunc.h> +#include <dt-bindings/clock/stm32fx-clock.h> / { clocks { @@ -51,6 +52,24 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_i2s_ckin: clk-i2s-ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; }; soc { @@ -178,6 +197,11 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; }; + pwrcfg: power-config@40007000 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + pin-controller { #address-cells = <1>; #size-cells = <1>; @@ -291,9 +315,10 @@ rcc: rcc@40023800 { #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; - clocks = <&clk_hse>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; }; }; }; |