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authorAlex Wilson <alex.david.wilson@gmail.com>2015-07-18 05:23:55 +0300
committerMichal Simek <michal.simek@xilinx.com>2015-07-31 11:50:05 +0300
commit6de663fe33b35fc95e751f907aa28e608c38f121 (patch)
tree0f7a95287fda0acd70d22a461b529f6707d37c10 /arch/arm
parent1837649fd350bf25e20d05dbdd4449160ad0219b (diff)
downloadlinux-6de663fe33b35fc95e751f907aa28e608c38f121.tar.xz
ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index d373b3860333..ac0a6a09b652 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -139,6 +139,7 @@
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
+ interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;