diff options
| author | Antoine Tenart <antoine.tenart@free-electrons.com> | 2017-07-19 12:04:26 +0300 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-07-19 14:38:14 +0300 |
| commit | ec0aef9881d18aa781268ec9cba8eba5b202f5b4 (patch) | |
| tree | a82f526fbf30c0dad89a4326e6e18138ede0870e /arch/arm64 | |
| parent | 579c183e4fe01d493f2efef8a335a9607376f754 (diff) | |
| download | linux-ec0aef9881d18aa781268ec9cba8eba5b202f5b4.tar.xz | |
arm64: dts: marvell: mark the cp110 crypto engine as dma coherent
The crypto engines found on the cp110 master and slave are dma coherent.
This patch adds the relevant property to their dt nodes.
Cc: stable@vger.kernel.org # v4.12+
Fixes: 973020fd9498 ("arm64: marvell: dts: add crypto engine description for 7k/8k")
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 726528ce54e9..4c68605675a8 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -270,6 +270,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; + dma-coherent; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 471aaf8dc750..923f354b02f0 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -261,6 +261,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; + dma-coherent; /* * The cryptographic engine found on the cp110 * master is enabled by default at the SoC |