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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-02-24 19:29:56 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-03-01 18:43:15 +0300 |
| commit | ef82c9be844f6b249a69d8fa190d4d686121d55c (patch) | |
| tree | 19c69c5404dbed6eae1c19f194a68a38b66670cd /arch/arm64 | |
| parent | 4b557e171ae7b5c5b69f7a5eee553714f7c52435 (diff) | |
| download | linux-ef82c9be844f6b249a69d8fa190d4d686121d55c.tar.xz | |
arm64: dts: n5x: add sdr edac support
The N5X platform has the Synopsys DDR controller the includes an EDAC
controller. Add the entry for the controller in the DTS file instead of
the base Agilex DTSI because the base Agilex does not have the
controller.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 5609d8df6729..50b29fa7ee01 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -24,6 +24,16 @@ /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; + + soc { + sdram_edac: sdr_edac@f87f8000 { + compatible = "snps,ddrc-3.80a"; + reg = <0xf87f8000 0x400>; + interrupts = <0 175 4>; + intel,sysmgr-syscon = <&sysmgr 0xb8>; + status = "okay"; + }; + }; }; &clkmgr { |