diff options
| author | Caesar Wang <wxt@rock-chips.com> | 2016-07-27 17:24:06 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-09-07 09:32:41 +0300 |
| commit | df4fe6f8c7b793adcab7b423a6efd989e195b4b3 (patch) | |
| tree | ea2358bd6e8c8f2f3e9834fa19ef68e737b23001 /arch/arm64 | |
| parent | ed6625cfdbe6bb9bc9561934361abdca43be551a (diff) | |
| download | linux-df4fe6f8c7b793adcab7b423a6efd989e195b4b3.tar.xz | |
arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
commit 78ec79bfd59e126e1cb394302bfa531a420b3ecd upstream.
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 8fe39e1b680e..e0ee2b00d573 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -262,6 +262,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; |