diff options
| author | Will Deacon <will.deacon@arm.com> | 2017-08-10 15:29:06 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-12-11 16:40:29 +0300 |
| commit | 85d13c001497b481b4a8cc5d7db243cc44ac2bd8 (patch) | |
| tree | aa9f9db5f6d9b6856c8cbb32bd0c13cdd6cd3430 /arch/arm64/mm/proc.S | |
| parent | 7655abb953860485940d4de74fb45a8192149bb6 (diff) | |
| download | linux-85d13c001497b481b4a8cc5d7db243cc44ac2bd8.tar.xz | |
arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003
The pre_ttbr0_update_workaround hook is called prior to context-switching
TTBR0 because Falkor erratum E1003 can cause TLB allocation with the wrong
ASID if both the ASID and the base address of the TTBR are updated at
the same time.
With the ASID sitting safely in TTBR1, we no longer update things
atomically, so we can remove the pre_ttbr0_update_workaround macro as
it's no longer required. The erratum infrastructure and documentation
is left around for #E1003, as it will be required by the entry
trampoline code in a future patch.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/mm/proc.S')
| -rw-r--r-- | arch/arm64/mm/proc.S | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index a8a64898a2aa..f2ff0837577c 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -138,7 +138,6 @@ ENDPROC(cpu_do_resume) * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) - pre_ttbr0_update_workaround x0, x2, x3 mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id bfi x2, x1, #48, #16 // set the ASID |