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| author | Will Deacon <will.deacon@arm.com> | 2017-03-10 23:32:22 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 19:16:57 +0300 |
| commit | 155433cb365ee4666bdf7c3c7bc2978b17be36a4 (patch) | |
| tree | 43668ce6b2cfffb1327fe5c1054ddc228a108f1a /arch/arm64/mm/context.c | |
| parent | a8d4636f96ad075dc6d6af182b3de0b5498dc301 (diff) | |
| download | linux-155433cb365ee4666bdf7c3c7bc2978b17be36a4.tar.xz | |
arm64: cache: Remove support for ASID-tagged VIVT I-caches
As a recent change to ARMv8, ASID-tagged VIVT I-caches are removed
retrospectively from the architecture. Consequently, we don't need to
support them in Linux either.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm/context.c')
| -rw-r--r-- | arch/arm64/mm/context.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 68634c630cdd..ab9f5f0fb2c7 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -119,9 +119,6 @@ static void flush_context(unsigned int cpu) /* Queue a TLB invalidate and flush the I-cache if necessary. */ cpumask_setall(&tlb_flush_pending); - - if (icache_is_aivivt()) - __flush_icache_all(); } static bool check_update_reserved_asid(u64 asid, u64 newasid) |