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| author | Will Deacon <will.deacon@arm.com> | 2018-06-11 16:22:09 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-07-05 19:24:36 +0300 |
| commit | 3b8c9f1cdfc506e94e992ae66b68bbe416f89610 (patch) | |
| tree | b57aba6cc3433283aaf8e327e9f2a43d4eb9a2cf /arch/arm64/mm/cache.S | |
| parent | 7373fed2f258e640031387616a2275a6fc0d7231 (diff) | |
| download | linux-3b8c9f1cdfc506e94e992ae66b68bbe416f89610.tar.xz | |
arm64: IPI each CPU after invalidating the I-cache for kernel mappings
When invalidating the instruction cache for a kernel mapping via
flush_icache_range(), it is also necessary to flush the pipeline for
other CPUs so that instructions fetched into the pipeline before the
I-cache invalidation are discarded. For example, if module 'foo' is
unloaded and then module 'bar' is loaded into the same area of memory,
a CPU could end up executing instructions from 'foo' when branching into
'bar' if these instructions were fetched into the pipeline before 'foo'
was unloaded.
Whilst this is highly unlikely to occur in practice, particularly as
any exception acts as a context-synchronizing operation, following the
letter of the architecture requires us to execute an ISB on each CPU
in order for the new instruction stream to be visible.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 30334d81b021..0c22ede52f90 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -35,7 +35,7 @@ * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(flush_icache_range) +ENTRY(__flush_icache_range) /* FALLTHROUGH */ /* @@ -77,7 +77,7 @@ alternative_else_nop_endif 9: mov x0, #-EFAULT b 1b -ENDPROC(flush_icache_range) +ENDPROC(__flush_icache_range) ENDPROC(__flush_cache_user_range) /* |