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authorJames Morse <james.morse@arm.com>2022-11-30 20:16:31 +0300
committerWill Deacon <will@kernel.org>2022-12-01 18:53:16 +0300
commite79c94a2a487515aeb1557b6d3e540ae5f66a67a (patch)
tree2a441f80b92bb961bb7cad7fa66acf72029f5faf /arch/arm64/include
parent039d372305fff8aa7dc22774c80637d57775eee6 (diff)
downloadlinux-e79c94a2a487515aeb1557b6d3e540ae5f66a67a.tar.xz
arm64/sysreg: Convert MVFR0_EL1 to automatic generation
Convert MVFR0_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20221130171637.718182-33-james.morse@arm.com Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r--arch/arm64/include/asm/sysreg.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ccb64dc09a4e..561968f7b66d 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,7 +170,6 @@
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
-#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
@@ -693,15 +692,6 @@
#define ID_DFR0_EL1_CopSDbg_SHIFT 4
#define ID_DFR0_EL1_CopDbg_SHIFT 0
-#define MVFR0_EL1_FPRound_SHIFT 28
-#define MVFR0_EL1_FPShVec_SHIFT 24
-#define MVFR0_EL1_FPSqrt_SHIFT 20
-#define MVFR0_EL1_FPDivide_SHIFT 16
-#define MVFR0_EL1_FPTrap_SHIFT 12
-#define MVFR0_EL1_FPDP_SHIFT 8
-#define MVFR0_EL1_FPSP_SHIFT 4
-#define MVFR0_EL1_SIMDReg_SHIFT 0
-
#define MVFR1_EL1_SIMDFMAC_SHIFT 28
#define MVFR1_EL1_FPHP_SHIFT 24
#define MVFR1_EL1_SIMDHP_SHIFT 20