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| author | Will Deacon <will.deacon@arm.com> | 2018-01-03 14:17:58 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-01-08 21:45:25 +0300 |
| commit | 0f15adbb2861ce6f75ccfc5a92b19eae0ef327d0 (patch) | |
| tree | 918eadd8cc51a5c04e2c9d4e657a4fec8f4b29d4 /arch/arm64/include/asm/sysreg.h | |
| parent | 95e3de3590e3f2358bb13f013911bc1bfa5d3f53 (diff) | |
| download | linux-0f15adbb2861ce6f75ccfc5a92b19eae0ef327d0.tar.xz | |
arm64: Add skeleton to harden the branch predictor against aliasing attacks
Aliasing attacks against CPU branch predictors can allow an attacker to
redirect speculative control flow on some CPUs and potentially divulge
information from one context to another.
This patch adds initial skeleton code behind a new Kconfig option to
enable implementation-specific mitigations against these attacks for
CPUs that are affected.
Co-developed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 262ae18f0e05..54e99af043c6 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -439,6 +439,7 @@ /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 +#define ID_AA64PFR0_CSV2_SHIFT 56 #define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 |