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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-05-21 20:35:19 +0400 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-02-27 21:16:59 +0400 |
| commit | 7363590d2c4691593fd280f94b3deaeb5e83dbbd (patch) | |
| tree | 892b7ac3974015dd23401a1d993cbd930cee2fb9 /arch/arm64/include/asm/cacheflush.h | |
| parent | 3690951fc6d42f3a0903987677d0e592c49dd8db (diff) | |
| download | linux-7363590d2c4691593fd280f94b3deaeb5e83dbbd.tar.xz | |
arm64: Implement coherent DMA API based on swiotlb
This patch adds support for DMA API cache maintenance on SoCs without
hardware device cache coherency.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cacheflush.h')
| -rw-r--r-- | arch/arm64/include/asm/cacheflush.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 889324981aa4..4c60e64a801c 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -85,6 +85,13 @@ static inline void flush_cache_page(struct vm_area_struct *vma, } /* + * Cache maintenance functions used by the DMA API. No to be used directly. + */ +extern void __dma_map_area(const void *, size_t, int); +extern void __dma_unmap_area(const void *, size_t, int); +extern void __dma_flush_range(const void *, const void *); + +/* * Copy user data from/to a page which is mapped into a different * processes address space. Really, we want to allow our "user * space" model to handle this. |