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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-03-17 21:05:13 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-19 13:43:57 +0300 |
| commit | 4a97abd44329bf7b9c57f020224da5f823c9c9ea (patch) | |
| tree | 7c22535e94706459719f71071113c57897de4bad /arch/arm64/crypto/aes-ce.S | |
| parent | b63dbef93f91d56cb4385fdd8d1765201d451136 (diff) | |
| download | linux-4a97abd44329bf7b9c57f020224da5f823c9c9ea.tar.xz | |
arm64/crypto: issue aese/aesmc instructions in pairs
This changes the AES core transform implementations to issue aese/aesmc
(and aesd/aesimc) in pairs. This enables a micro-architectural optimization
in recent Cortex-A5x cores that improves performance by 50-90%.
Measured performance in cycles per byte (Cortex-A57):
CBC enc CBC dec CTR
before 3.64 1.34 1.32
after 1.95 0.85 0.93
Note that this results in a ~5% performance decrease for older cores.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/crypto/aes-ce.S')
| -rw-r--r-- | arch/arm64/crypto/aes-ce.S | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm64/crypto/aes-ce.S b/arch/arm64/crypto/aes-ce.S index 685a18f731eb..78f3cfe92c08 100644 --- a/arch/arm64/crypto/aes-ce.S +++ b/arch/arm64/crypto/aes-ce.S @@ -45,18 +45,14 @@ .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3 aes\de \i0\().16b, \k\().16b - .ifnb \i1 - aes\de \i1\().16b, \k\().16b - .ifnb \i3 - aes\de \i2\().16b, \k\().16b - aes\de \i3\().16b, \k\().16b - .endif - .endif aes\mc \i0\().16b, \i0\().16b .ifnb \i1 + aes\de \i1\().16b, \k\().16b aes\mc \i1\().16b, \i1\().16b .ifnb \i3 + aes\de \i2\().16b, \k\().16b aes\mc \i2\().16b, \i2\().16b + aes\de \i3\().16b, \k\().16b aes\mc \i3\().16b, \i3\().16b .endif .endif |