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author | Jisheng Zhang <jszhang@kernel.org> | 2022-01-23 12:04:17 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-02-09 04:02:47 +0300 |
commit | f81393a5b252df772b934cde81b7e16273afbd43 (patch) | |
tree | 5e0075974304fc0021484ba9a8971cf564178ede /arch/arm64/configs | |
parent | ca0cb9a60f6d86d4b2139c6f393a78f39edcd7cb (diff) | |
download | linux-f81393a5b252df772b934cde81b7e16273afbd43.tar.xz |
riscv: extable: fix err reg writing in dedicated uaccess handler
Mayuresh reported commit 20802d8d477d ("riscv: extable: add a dedicated
uaccess handler") breaks the writev02 test case in LTP. This is due to
the err reg isn't correctly set with the errno(-EFAULT in writev02
case). First of all, the err and zero regs are reg numbers rather than
reg offsets in struct pt_regs; Secondly, regs_set_gpr() should write
the regs when offset isn't zero(zero means epc)
Fix it by correcting regs_set_gpr() logic and passing the correct reg
offset to it.
Reported-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Fixes: 20802d8d477d ("riscv: extable: add a dedicated uaccess handler")
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/arm64/configs')
0 files changed, 0 insertions, 0 deletions