diff options
| author | Yifeng Zhao <yifeng.zhao@rock-chips.com> | 2022-02-08 12:13:26 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2022-02-25 02:25:12 +0300 |
| commit | 3cc8cd2d25954ed5794df2d190b81c7325c584e3 (patch) | |
| tree | 68f4b468f1a7d0df65b44cb0a2f9a4a29b21ec69 /arch/arm64/boot/dts/rockchip/rk3568.dtsi | |
| parent | a0024f55eb5b741b76a0b950f1222ddbab6a9fc9 (diff) | |
| download | linux-3cc8cd2d25954ed5794df2d190b81c7325c584e3.tar.xz | |
arm64: dts: rockchip: add naneng combo phy nodes for rk3568
Add the core dt-node for the rk3568's naneng combo phys.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3568.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { |