diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-03 16:18:16 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 09:51:04 +0300 |
| commit | d165856de103a6d317a9c9a5782eacd5dc90a9dc (patch) | |
| tree | 55672faf7d5d66dfe1262a1c4d36813b19015e44 /arch/arm64/boot/dts/renesas | |
| parent | b3f26910c0daafded536cf5edceab2ab469252cb (diff) | |
| download | linux-d165856de103a6d317a9c9a5782eacd5dc90a9dc.tar.xz | |
arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
The Cortex-A57/A53 cache controllers are integrated controllers, and
thus the device nodes representing them should not have unit-addresses
or reg properties.
Fixes: 6f7bf82cc912441f ("arm64: dts: r8a7795: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index c1e00a3e7c45..14772bc02125 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -109,17 +109,15 @@ enable-method = "psci"; }; - L2_CA57: cache-controller@0 { + L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7795_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; - L2_CA53: cache-controller@100 { + L2_CA53: cache-controller-1 { compatible = "cache"; - reg = <0x100>; power-domains = <&sysc R8A7795_PD_CA53_SCU>; cache-unified; cache-level = <2>; |