diff options
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2021-09-01 14:13:04 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-20 13:07:06 +0300 |
| commit | eb6750431e66bf139283ef7e56c1f41dc30f15fc (patch) | |
| tree | 33e26ce8324967f1f7495a8fd6311b31d9dcec9d /arch/arm64/boot/dts/renesas | |
| parent | bdd8b0053f4ff0df889bd849f0789580e9faea3a (diff) | |
| download | linux-eb6750431e66bf139283ef7e56c1f41dc30f15fc.tar.xz | |
arm64: dts: renesas: r8a779a0: Add IPMMU nodes
Add IPMMU nodes for r8a779a0. Note that this patch sets the power
domain of IPMMU-VC0 is Always-On tentatively because the SoC doesn't
have A3VC power domain.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210901111305.570206-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 4428e65dc7e1..2ac1ec465601 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1104,6 +1104,103 @@ status = "disabled"; }; + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 19>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: iommu@eed80000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeed80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A779A0_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@eedc0000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeedc0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@eee80000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeee80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@eeec0000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeeec0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_3dg: iommu@eee00000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeee00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: iommu@eef00000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeef00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip1: iommu@eef40000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeef40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 11>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779a0"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; |