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authorYT Shen <yt.shen@mediatek.com>2018-12-03 14:35:59 +0300
committerMatthias Brugger <matthias.bgg@gmail.com>2019-01-09 20:16:07 +0300
commitd85b9774c8bda4589db7e82d9e347522b82ef57d (patch)
treef57e7a11f509e8f7992bb8a643260312bf8bc4ae /arch/arm64/boot/dts/mediatek/mt2712e.dtsi
parent9d66740cecbdfb7dca65af4ba6ae5f70df8d9c07 (diff)
downloadlinux-d85b9774c8bda4589db7e82d9e347522b82ef57d.tar.xz
arm64: dts: add pwm nodes for MT2712
Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt2712e.dtsi')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4843376fd827..e9856fef3e72 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,34 @@
status = "disabled";
};
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt2712-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM>,
+ <&pericfg CLK_PERI_PWM0>,
+ <&pericfg CLK_PERI_PWM1>,
+ <&pericfg CLK_PERI_PWM2>,
+ <&pericfg CLK_PERI_PWM3>,
+ <&pericfg CLK_PERI_PWM4>,
+ <&pericfg CLK_PERI_PWM5>,
+ <&pericfg CLK_PERI_PWM6>,
+ <&pericfg CLK_PERI_PWM7>;
+ clock-names = "top",
+ "main",
+ "pwm1",
+ "pwm2",
+ "pwm3",
+ "pwm4",
+ "pwm5",
+ "pwm6",
+ "pwm7",
+ "pwm8";
+ status = "disabled";
+ };
+
i2c0: i2c@11007000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11007000 0 0x90>,