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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 17:27:35 +0300 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 10:36:41 +0300 |
| commit | 6b8970bd8d7a17a648e31f3996d9b21336b4a2cf (patch) | |
| tree | 037afdb9ed341d3af1b233a46db585e8ab0b038b /arch/arm64/boot/dts/marvell/cn9130.dtsi | |
| parent | 96bb4b31aa660e39fca2bb464b9a9f399bd5b71c (diff) | |
| download | linux-6b8970bd8d7a17a648e31f3996d9b21336b4a2cf.tar.xz | |
arm64: dts: marvell: Add support for Marvell CN9130 SoC support
A CN9130 SoC has one AP807 and one internal CP115.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/cn9130.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi new file mode 100644 index 000000000000..a2b7e5ec979d --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9130 SoC. + */ + +#include "armada-ap807-quad.dtsi" + +/ { + model = "Marvell Armada CN9130 SoC"; + compatible = "marvell,cn9130", "marvell,armada-ap807-quad", + "marvell,armada-ap807"; +}; + +/* + * Instantiate the internal CP115 + */ + +#define CP11X_NAME cp0 +#define CP11X_BASE f2000000 +#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ + 0xe0000000 + ((iface - 1) * 0x1000000)) +#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) +#define CP11X_PCIE0_BASE f2600000 +#define CP11X_PCIE1_BASE f2620000 +#define CP11X_PCIE2_BASE f2640000 + +#include "armada-cp115.dtsi" + +#undef CP11X_NAME +#undef CP11X_BASE +#undef CP11X_PCIEx_MEM_BASE +#undef CP11X_PCIEx_MEM_SIZE +#undef CP11X_PCIE0_BASE +#undef CP11X_PCIE1_BASE +#undef CP11X_PCIE2_BASE |