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| author | Yixun Lan <yixun.lan@amlogic.com> | 2018-03-28 06:01:29 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-05-10 01:14:50 +0300 |
| commit | 5e395e146667ef5484e7186d5a9218ce52b548d7 (patch) | |
| tree | a75ccaf9f0bcd07b025c15b559b1080b35420a4f /arch/arm64/boot/dts/amlogic | |
| parent | 0df8fbb9df8b73aafde80e1b1519a244ea703cf8 (diff) | |
| download | linux-5e395e146667ef5484e7186d5a9218ce52b548d7.tar.xz | |
ARM64: dts: meson-axg: add an 32K alt aoclk
The ao_clk81 in AO domain have two clock source,
one from a 32K alt crystal we name it as ao_alt_clk,
another is the clk81 signal from EE domain.
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 854d5b25effd..a3a0fd51871b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -108,6 +108,13 @@ #clock-cells = <0>; }; + ao_alt_xtal: ao_alt_xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <32000000>; + clock-output-names = "ao_alt_xtal"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; |