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authorStefan Agner <stefan@agner.ch>2020-12-07 20:58:00 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-12-30 13:53:41 +0300
commit46b7f2249854532d5783e24bb2a6d143d323558d (patch)
tree3926f07e976fd5732d1f8edd7223d32162405d5e /arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
parenta83bf1290710b82c420f9a33808d8d69f90f0eb3 (diff)
downloadlinux-46b7f2249854532d5783e24bb2a6d143d323558d.tar.xz
arm64: dts: meson: fix PHY deassert timing requirements
[ Upstream commit c183c406c4321002fe85b345b51bc1a3a04b6d33 ] According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue seen on ODROID-C2 where the Ethernet link doesn't come up when using ip link set down/up: [ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down [ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36) [ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma [ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts')
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index ea45ae0c71b7..8edbfe040805 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -64,7 +64,7 @@
/* External PHY reset is shared with internal PHY Led signal */
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;