diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-07-29 16:26:17 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-08-09 21:06:13 +0300 |
| commit | 1499218c80c99ae73c937c370142c8f6048002d5 (patch) | |
| tree | 847cfb24305e9241880142e4fa9578578170e0e8 /arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | |
| parent | dc7f2cb218b5ef65ab3d455a0e62d27e44075203 (diff) | |
| download | linux-1499218c80c99ae73c937c370142c8f6048002d5.tar.xz | |
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi file and
express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi.
This separation will help for DVFS and future Amlogic SM1 Family support.
The sd_emmc_a quirk is added in the g12a/g12b since since it's already
known the sd_emmc_a controller is fixed in the next SM1 SoC family.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-g12b.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 9e88e513b22d..d5edbc1a1991 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -4,12 +4,15 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ -#include "meson-g12a.dtsi" +#include "meson-g12-common.dtsi" / { compatible = "amlogic,g12b"; cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + cpu-map { cluster0 { core0 { @@ -40,8 +43,21 @@ }; }; - /delete-node/ cpu@2; - /delete-node/ cpu@3; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; cpu100: cpu@100 { device_type = "cpu"; @@ -74,9 +90,17 @@ enable-method = "psci"; next-level-cache = <&l2>; }; + + l2: l2-cache0 { + compatible = "cache"; + }; }; }; &clkc { compatible = "amlogic,g12b-clkc"; }; + +&sd_emmc_a { + amlogic,dram-access-quirk; +}; |