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author | Neil Armstrong <narmstrong@baylibre.com> | 2019-07-29 16:26:20 +0300 |
---|---|---|
committer | Kevin Hilman <khilman@baylibre.com> | 2019-08-09 21:07:03 +0300 |
commit | e9bc0765cc1274b7221360f462a3a993b41cac92 (patch) | |
tree | 4aefeb8b4bd7b44ba196ec2cd8de0094171922f3 /arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | |
parent | b190056fa9eecc016b6a6e41f89a04da14b78bf7 (diff) | |
download | linux-e9bc0765cc1274b7221360f462a3a993b41cac92.tar.xz |
arm64: dts: meson-g12a: enable DVFS on G12A boards
Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board
by setting the clock, OPP and supply for each CPU cores.
The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM
output clocked at 800KHz with an inverse duty-cycle.
DVFS has been tested by running the arm64 cpuburn at [1] and cycling
between all the possible cpufreq translations and checking the final
frequency using the clock-measurer, script at [2].
[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts')
-rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 12aa7eaeaf68..c9fa23a56562 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -129,6 +129,25 @@ enable-active-high; }; + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + vddio_ao1v8: regulator-vddio_ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; @@ -297,6 +316,34 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + &cvbs_vdac_port { cvbs_vdac_out: endpoint { remote-endpoint = <&cvbs_connector_in>; @@ -345,6 +392,14 @@ pinctrl-names = "default"; }; +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>; |