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authorPaul Kocialkowski <paul.kocialkowski@bootlin.com>2018-12-05 12:24:37 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-12-05 14:03:02 +0300
commit24a1be4e7e80fc7a19290be4715191b77fe80b41 (patch)
tree27b8c7959d6da3543a73b4c00bbb25d667807d72 /arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
parent973efbc6a061488f280ac1792200e48eb0b1ff5e (diff)
downloadlinux-24a1be4e7e80fc7a19290be4715191b77fe80b41.tar.xz
ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes
The EMAC driver requires a syscon node to access the EMAC clock configuration register (that is part of the system-control register range and controlled). For this purpose, a dummy syscon node was introduced to let the driver access the register freely. Recently, the EMAC driver was tuned to get access to the register when the SRAM driver is registered (as used on the A64). As a result, it is no longer necessary to have a dummy syscon node for that purpose. Now that we have a proper system-control node for both the H3 and H5, we can get rid of that dummy syscon node and have the EMAC driver use the node corresponding to the proper SRAM driver (by switching the syscon label over to each dtsi). This way, we no longer have two separate nodes for the same register space. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi')
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index f184d8f55c8a..107607baaa42 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -94,7 +94,7 @@
};
soc {
- system-control@1c00000 {
+ syscon: system-control@1c00000 {
compatible = "allwinner,sun50i-h5-system-control";
reg = <0x01c00000 0x1000>;
#address-cells = <1>;