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authorCatalin Marinas <catalin.marinas@arm.com>2011-11-28 17:53:28 +0400
committerCatalin Marinas <catalin.marinas@arm.com>2012-04-17 18:29:32 +0400
commit7fec1b57b8a925d83c194f995f83d9f8442fd48e (patch)
tree320c333459779e1388f5aae50ae50edb4482e82c /arch/arm/mm/proc-v7-2level.S
parent3c5f7e7b4a0346de670b08f595bd15e7eec91f97 (diff)
downloadlinux-7fec1b57b8a925d83c194f995f83d9f8442fd48e.tar.xz
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
Since the ASIDs must be unique to an mm across all the CPUs in a system, the __new_context() function needs to broadcast a context reset event to all the CPUs during ASID allocation if a roll-over occurred. Such IPIs cannot be issued with interrupts disabled and ARM had to define __ARCH_WANT_INTERRUPTS_ON_CTXSW. This patch changes the check_context() function to check_and_switch_context() called from switch_mm(). In case of ASID-capable CPUs (ARMv6 onwards), if a new ASID is needed and the interrupts are disabled, it defers the __new_context() and cpu_switch_mm() calls to the post-lock switch hook where the interrupts are enabled. Setting the reserved TTBR0 was also moved to check_and_switch_context() from cpu_v7_switch_mm(). Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com> Tested-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/mm/proc-v7-2level.S')
-rw-r--r--arch/arm/mm/proc-v7-2level.S3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 72270482a922..42ac069c8012 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -46,9 +46,6 @@ ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_ARM_ERRATA_430973
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif
- mrc p15, 0, r2, c2, c0, 1 @ load TTB 1
- mcr p15, 0, r2, c2, c0, 0 @ into TTB 0
- isb
#ifdef CONFIG_ARM_ERRATA_754322
dsb
#endif