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author | Jaroslav Kysela <perex@perex.cz> | 2010-01-08 11:26:34 +0300 |
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committer | Jaroslav Kysela <perex@perex.cz> | 2010-01-08 11:26:34 +0300 |
commit | 1cb4f624ea38361b6397966470f0a1bed5532483 (patch) | |
tree | 418b05ddc854b09d64f7d5ee0c78875e42b5f151 /arch/arm/mm/cache-v4wb.S | |
parent | 444c1953d496d272208902ff7010dc70d1f887f0 (diff) | |
parent | 2c1f1895ef2aa8f0e5497893eff71304aef332e1 (diff) | |
download | linux-1cb4f624ea38361b6397966470f0a1bed5532483.tar.xz |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into fixes
Diffstat (limited to 'arch/arm/mm/cache-v4wb.S')
-rw-r--r-- | arch/arm/mm/cache-v4wb.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 2ebc1b3bf856..3dbedf1ec0e7 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -114,15 +114,16 @@ ENTRY(v4wb_flush_user_cache_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(v4wb_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(v4wb_flush_kern_dcache_area) + add r1, r0, r1 /* fall through */ /* @@ -224,7 +225,7 @@ ENTRY(v4wb_cache_fns) .long v4wb_flush_user_cache_range .long v4wb_coherent_kern_range .long v4wb_coherent_user_range - .long v4wb_flush_kern_dcache_page + .long v4wb_flush_kern_dcache_area .long v4wb_dma_inv_range .long v4wb_dma_clean_range .long v4wb_dma_flush_range |