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authorTakashi Iwai <tiwai@suse.de>2009-12-14 20:01:56 +0300
committerTakashi Iwai <tiwai@suse.de>2009-12-14 20:01:56 +0300
commitb89371621e5bedc84498ced2c5c33976bd1b2f64 (patch)
treeb309919239586e25617a17785b827577b1abb6b5 /arch/arm/mm/Kconfig
parent63978ab3e3e963db28093b53bb4598f2702e1ad7 (diff)
parent74c2b45b714e49b427584b4bd8f44f1a24d82d9c (diff)
downloadlinux-b89371621e5bedc84498ced2c5c33976bd1b2f64.tar.xz
Merge branch 'next/isa' into topic/misc
Diffstat (limited to 'arch/arm/mm/Kconfig')
-rw-r--r--arch/arm/mm/Kconfig13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9264d814cd7a..dd4698c67cc3 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID
# ARMv6
config CPU_V6
- bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+ bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
select CPU_32v6
select CPU_ABRT_EV6
select CPU_PABRT_V6
@@ -764,6 +764,15 @@ config CACHE_L2X0
help
This option enables the L2x0 PrimeCell.
+config CACHE_TAUROS2
+ bool "Enable the Tauros2 L2 cache controller"
+ depends on ARCH_DOVE
+ default y
+ select OUTER_CACHE
+ help
+ This option enables the Tauros2 L2 cache controller (as
+ found on PJ1/PJ4).
+
config CACHE_XSC3L2
bool "Enable the L2 cache on XScale3"
depends on CPU_XSC3
@@ -774,5 +783,5 @@ config CACHE_XSC3L2
config ARM_L1_CACHE_SHIFT
int
- default 6 if ARCH_OMAP3
+ default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
default 5