diff options
| author | Pawel Moll <pawel.moll@arm.com> | 2012-06-12 19:14:03 +0400 |
|---|---|---|
| committer | Pawel Moll <pawel.moll@arm.com> | 2012-07-12 19:16:56 +0400 |
| commit | d927daf5c81c9b6bf2d6a83dc4c8c60268930ee5 (patch) | |
| tree | e0a45cf8833d54d2b811b1b5a9635b3b8c844084 /arch/arm/mach-vexpress/ct-ca9x4.c | |
| parent | ef5911966d2312478a74e93d993cd623a869ab10 (diff) | |
| download | linux-d927daf5c81c9b6bf2d6a83dc4c8c60268930ee5.tar.xz | |
ARM: vexpress: Check master site in daughterboard's sysctl operations
With recent enough motherboard firmware, core tile can be fitted
in either of the two daughterboard sites. The non-DT tile code for
V2P-CA9 did not check that when configuring DVI output nor setting
CLCD pixel clock.
Fixed now, providing "get master site" API in motherboard's code.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/arm/mach-vexpress/ct-ca9x4.c')
| -rw-r--r-- | arch/arm/mach-vexpress/ct-ca9x4.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index c65cc3b462a5..ab15a5515312 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void) static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) { - v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); - v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); + u32 site = v2m_get_master_site(); + + /* + * Old firmware was using the "site" component of the command + * to control the DVI muxer (while it should be always 0 ie. MB). + * Newer firmware uses the data register. Keep both for compatibility. + */ + v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site); + v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2); } static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) @@ -112,7 +119,9 @@ static long ct_round(struct clk *clk, unsigned long rate) static int ct_set(struct clk *clk, unsigned long rate) { - return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate); + u32 site = v2m_get_master_site(); + + return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(site) | 1, rate); } static const struct clk_ops osc1_clk_ops = { |