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| author | Maxime Coquelin <maxime.coquelin@stericsson.com> | 2013-01-23 14:27:58 +0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-03-18 16:49:58 +0400 |
| commit | 0f2fa40e464c955e928979331625b5485c292bf0 (patch) | |
| tree | 670ea27813cf5b9fb5570d0ae6591253bdd51a2e /arch/arm/mach-ux500 | |
| parent | cca438b57e660c9a4a3216a69405b45ff00274e6 (diff) | |
| download | linux-0f2fa40e464c955e928979331625b5485c292bf0.tar.xz | |
ARM: mach-ux500: enable 128KB way L2 cache on DB8540
DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.
Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
cpus in the x540 family.
Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500')
| -rw-r--r-- | arch/arm/mach-ux500/cache-l2x0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609da76ce..f815efe54c73 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void) /* Unlock before init */ ux500_l2x0_unlock(); - /* DB9540's L2 has 128KB way size */ - if (cpu_is_u9540()) + /* DBx540's L2 has 128KB way size */ + if (cpu_is_ux540_family()) /* 128KB way size */ aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); else |