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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-19 16:44:41 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-30 03:48:51 +0400 |
| commit | 36bccb11a4ac7cc9d190c3062945f1c911a62801 (patch) | |
| tree | 499ae758e459a3334a96ab82084c9fd15f5208ea /arch/arm/mach-spear | |
| parent | 4374d64933b1d0f0ebbad064289ef44b869d77c1 (diff) | |
| download | linux-36bccb11a4ac7cc9d190c3062945f1c911a62801.tar.xz | |
ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear')
| -rw-r--r-- | arch/arm/mach-spear/spear13xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 92860fa01668..dcb300443b66 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -46,7 +46,7 @@ void __init spear13xx_l2x0_init(void) */ writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); - l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); + l2x0_init(VA_L2CC_BASE, 0x30a60001, 0xfe00ffff); } /* |