diff options
| author | Dinh Nguyen <dinguyen@altera.com> | 2013-04-11 19:55:26 +0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-04-15 07:18:13 +0400 |
| commit | 56c5c13f7080f9299a92b3fb6a1bf22689d607cc (patch) | |
| tree | 2d2c1570166abefb89e0c6a85810308790e4e4a8 /arch/arm/mach-socfpga | |
| parent | 042000b00344dbf25db2919c97cbd09be99ecf93 (diff) | |
| download | linux-56c5c13f7080f9299a92b3fb6a1bf22689d607cc.tar.xz | |
ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/socfpga.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 2cae16c1f265..46a051359f02 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -15,6 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -29,6 +30,7 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; +void __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { @@ -77,6 +79,9 @@ void __init socfpga_sysmgr_init(void) np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); rst_manager_base_addr = of_iomap(np, 0); + + np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); + clk_mgr_base_addr = of_iomap(np, 0); } static void __init socfpga_init_irq(void) @@ -102,6 +107,7 @@ static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_clk_init(NULL); socfpga_init_clocks(); } |