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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-06-03 05:14:02 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@linaro.org> | 2015-06-11 01:35:35 +0300 |
| commit | 45be0cdb5323d6f2b4005a4d9263a72eac2040cd (patch) | |
| tree | bc331c9bbffe4ea63a77452a12aeb57116fa992a /arch/arm/mach-socfpga/core.h | |
| parent | 5f763ef80d4dff7f2aa519a31472b03499e2c2e1 (diff) | |
| download | linux-45be0cdb5323d6f2b4005a4d9263a72eac2040cd.tar.xz | |
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:
- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/mach-socfpga/core.h')
| -rw-r--r-- | arch/arm/mach-socfpga/core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 38e5cbf37f45..27e7c65093c0 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -25,6 +25,8 @@ #define SOCFPGA_RSTMGR_MODPERRST 0x14 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c +#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 + /* System Manager bits */ #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ |