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authorOlof Johansson <olof@lixom.net>2013-08-14 12:09:40 +0400
committerOlof Johansson <olof@lixom.net>2013-08-14 22:09:47 +0400
commitf2d6e550a23e6ea5aca70817ada87b78f2b8c6c1 (patch)
tree3b01d8edc1c2da5e20cb1a57dddf30504b5c3b7c /arch/arm/mach-shmobile
parentfc5d46222fe60ce56da47bcb85beed3f8864a5fe (diff)
parentd687f4d1993fa046171dbb1ca1970a3172ce11b9 (diff)
downloadlinux-f2d6e550a23e6ea5aca70817ada87b78f2b8c6c1.tar.xz
Merge tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman: Second Round of Renesas ARM based SoC updates for v3.12 * Increased clock coverage for r8a7740 and r8a7790 SoCs * tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms ARM: shmobile: r8a7790: clocks for Ether support ARM: shmobile: r8a7740: Fix TPU clock name ARM: shmobile: Insert align directives before 4 bytes data ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y ARM: shmobile: Update romImage to relocate appended DTB Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c3
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S4
-rw-r--r--arch/arm/mach-shmobile/headsmp.S6
-rw-r--r--arch/arm/mach-shmobile/include/mach/zboot.h2
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S2
6 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index de10fd78bf2b..c826bca4024e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
- CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]),
+ CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
+ CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 50d96f9cf981..fc36d3db0b4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -51,6 +51,7 @@
#define SMSTPCR3 0xe615013c
#define SMSTPCR5 0xe6150144
#define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
#define SDCKCR 0xE6150074
#define SD2CKCR 0xE6150078
@@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = {
/* MSTP */
enum {
+ MSTP813,
MSTP721, MSTP720,
MSTP717, MSTP716,
MSTP522,
@@ -190,6 +192,7 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
@@ -258,6 +261,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+ CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bfd920083a3b..f45dde701d7b 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu)
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
ldr r2, [r0, #8] @ SCU Power Status Register
mov r3, #3
- bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode)
+ lsl r3, r3, r1
+ bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back
b shmobile_invalidate_start
ENDPROC(shmobile_boot_scu)
.text
+ .align 2
.globl shmobile_scu_base
shmobile_scu_base:
.space 4
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index a9d212498987..2667db806c39 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,12 +24,16 @@ ENDPROC(shmobile_invalidate_start)
* This will be mapped at address 0 by SBAR register.
* We need _long_ jump to the physical address.
*/
+ .arm
.align 12
ENTRY(shmobile_boot_vector)
ldr r0, 2f
- ldr pc, 1f
+ ldr r1, 1f
+ bx r1
+
ENDPROC(shmobile_boot_vector)
+ .align 2
.globl shmobile_boot_fn
shmobile_boot_fn:
1: .space 4
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index f2d8744c1f14..c3c4669a2d72 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -1,7 +1,6 @@
#ifndef ZBOOT_H
#define ZBOOT_H
-#include <asm/mach-types.h>
#include <mach/zboot_macros.h>
/**************************************************
@@ -11,7 +10,6 @@
**************************************************/
#ifdef CONFIG_MACH_MACKEREL
-#define MACH_TYPE MACH_TYPE_MACKEREL
#define MEMORY_START 0x40000000
#include "mach/head-mackerel.txt"
#else
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 53f4840e4949..9782862899e8 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -41,6 +41,7 @@
sh7372_resume_core_standby_sysc:
ldr pc, 1f
+ .align 2
.globl sh7372_cpu_resume
sh7372_cpu_resume:
1: .space 4
@@ -96,6 +97,7 @@ sh7372_do_idle_sysc:
1:
b 1b
+ .align 2
kernel_flush:
.word v7_flush_dcache_all
#endif