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authorMagnus Damm <damm@opensource.se>2011-09-26 01:20:49 +0400
committerRafael J. Wysocki <rjw@sisk.pl>2011-09-26 01:20:49 +0400
commitcf33835c5fc528cacd4f98bc38f246022dad340d (patch)
tree4142c54bfcc9e95468d8d3e872583d306d6484e7 /arch/arm/mach-shmobile/sleep-sh7372.S
parent06b841666a5a47918d31472dd77837906f999a9a (diff)
downloadlinux-cf33835c5fc528cacd4f98bc38f246022dad340d.tar.xz
ARM: mach-shmobile: sh7372 A3SM support
This patch adds sh7372 A3SM power domain support. The sh7372 A3SM hardware power domain contains the ARM Cortex-A8 CPU Core including L2 cache. This sleep mode can be seen as a one step deeper sleep mode from the already existing Core Standby mode. To wake up from A3SM sleep only a few wakeup sources are supported - so the regular INTC controller will not be able to help us unfortunately. The code in this patch will enter A3SM sleep via the regular Suspend-to-RAM interface in the case of only wakeups supported by A3SM are enabled. If unsupported wakeups are enabled then Core Standby will be used instead. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/arm/mach-shmobile/sleep-sh7372.S')
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S55
1 files changed, 53 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index dedf6126789c..d365842ded47 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -36,7 +36,58 @@
.align 12
.text
- .global sh7372_resume_core_standby
-sh7372_resume_core_standby:
+ .global sh7372_resume_core_standby_a3sm
+sh7372_resume_core_standby_a3sm:
ldr pc, 1f
1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+
+ .global sh7372_do_idle_a3sm
+sh7372_do_idle_a3sm:
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /* disable L2 cache in the aux control register */
+ mrc p15, 0, r10, c1, c0, 1
+ bic r10, r10, #2
+ mcr p15, 0, r10, c1, c0, 1
+
+ /*
+ * Invalidate data cache again.
+ */
+ ldr r1, kernel_flush
+ blx r1
+ /*
+ * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+ * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+ * This sequence switches back to ARM. Note that .align may insert a
+ * nop: bx pc needs to be word-aligned in order to work.
+ */
+ THUMB( .thumb )
+ THUMB( .align )
+ THUMB( bx pc )
+ THUMB( nop )
+ .arm
+
+ /* Data memory barrier and Data sync barrier */
+ dsb
+ dmb
+
+#define SPDCR 0xe6180008
+#define A3SM (1 << 12)
+
+ /* A3SM power down */
+ ldr r0, =SPDCR
+ ldr r1, =A3SM
+ str r1, [r0]
+1:
+ b 1b
+
+kernel_flush:
+ .word v7_flush_dcache_all