diff options
| author | David Woodhouse <David.Woodhouse@intel.com> | 2012-10-09 18:03:21 +0400 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-10-09 18:04:25 +0400 |
| commit | ffe315012510165ce82e4dd4767f0a5dba9edbf7 (patch) | |
| tree | f601cd980af9d0ced5ca9aedecef4fa0d2ca0e15 /arch/arm/mach-shmobile/clock-sh7367.c | |
| parent | e2d3a35ee427aaba99b6c68a56609ce276c51270 (diff) | |
| parent | 4a8e43feeac7996b8de2d5b2823e316917493df4 (diff) | |
| download | linux-ffe315012510165ce82e4dd4767f0a5dba9edbf7.tar.xz | |
Merge tag 'disintegrate-mtd-20121009' of git://git.infradead.org/users/dhowells/linux-headers
UAPI Disintegration 2012-10-09
Conflicts:
MAINTAINERS
arch/arm/configs/bcmring_defconfig
arch/arm/mach-imx/clk-imx51-imx53.c
drivers/mtd/nand/Kconfig
drivers/mtd/nand/bcm_umi_nand.c
drivers/mtd/nand/nand_bcm_umi.h
drivers/mtd/nand/orion_nand.c
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh7367.c')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7367.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 162b791b8984..ef0a95e592c4 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -24,28 +24,28 @@ #include <mach/common.h> /* SH7367 registers */ -#define RTFRQCR 0xe6150000 -#define SYFRQCR 0xe6150004 -#define CMFRQCR 0xe61500E0 -#define VCLKCR1 0xe6150008 -#define VCLKCR2 0xe615000C -#define VCLKCR3 0xe615001C -#define SCLKACR 0xe6150010 -#define SCLKBCR 0xe6150014 -#define SUBUSBCKCR 0xe6158080 -#define SPUCKCR 0xe6150084 -#define MSUCKCR 0xe6150088 -#define MVI3CKCR 0xe6150090 -#define VOUCKCR 0xe6150094 -#define MFCK1CR 0xe6150098 -#define MFCK2CR 0xe615009C -#define PLLC1CR 0xe6150028 -#define PLLC2CR 0xe615002C -#define RTMSTPCR0 0xe6158030 -#define RTMSTPCR2 0xe6158038 -#define SYMSTPCR0 0xe6158040 -#define SYMSTPCR2 0xe6158048 -#define CMMSTPCR0 0xe615804c +#define RTFRQCR IOMEM(0xe6150000) +#define SYFRQCR IOMEM(0xe6150004) +#define CMFRQCR IOMEM(0xe61500E0) +#define VCLKCR1 IOMEM(0xe6150008) +#define VCLKCR2 IOMEM(0xe615000C) +#define VCLKCR3 IOMEM(0xe615001C) +#define SCLKACR IOMEM(0xe6150010) +#define SCLKBCR IOMEM(0xe6150014) +#define SUBUSBCKCR IOMEM(0xe6158080) +#define SPUCKCR IOMEM(0xe6150084) +#define MSUCKCR IOMEM(0xe6150088) +#define MVI3CKCR IOMEM(0xe6150090) +#define VOUCKCR IOMEM(0xe6150094) +#define MFCK1CR IOMEM(0xe6150098) +#define MFCK2CR IOMEM(0xe615009C) +#define PLLC1CR IOMEM(0xe6150028) +#define PLLC2CR IOMEM(0xe615002C) +#define RTMSTPCR0 IOMEM(0xe6158030) +#define RTMSTPCR2 IOMEM(0xe6158038) +#define SYMSTPCR0 IOMEM(0xe6158040) +#define SYMSTPCR2 IOMEM(0xe6158048) +#define CMMSTPCR0 IOMEM(0xe615804c) /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { |