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| author | Rob Herring <rob.herring@calxeda.com> | 2011-06-29 06:16:13 +0400 |
|---|---|---|
| committer | Rob Herring <rob.herring@calxeda.com> | 2011-07-12 20:19:29 +0400 |
| commit | c9d95fbe59e426eed7f16e7cac812e46ac4772d0 (patch) | |
| tree | 7e7c01255fb18932ee4f0c68b1501ab35db7c012 /arch/arm/mach-sa1100 | |
| parent | dc8d966bccde0b8b6c9e8c6e663c747030c17435 (diff) | |
| download | linux-c9d95fbe59e426eed7f16e7cac812e46ac4772d0.tar.xz | |
ARM: convert PCI defines to variables
Convert PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM to variables to allow
multi-platform builds. This also removes the requirement for a platform to
have a mach/hardware.h.
The default values for i/o and mem are 0x1000 and 0x01000000, respectively.
Per Arnd Bergmann, other values are likely to be incorrect, but this commit
does not try to address that issue.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-sa1100')
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/hardware.h | 7 | ||||
| -rw-r--r-- | arch/arm/mach-sa1100/pci-nanoengine.c | 3 |
2 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h index 5946af276dc7..99f5856d8de4 100644 --- a/arch/arm/mach-sa1100/include/mach/hardware.h +++ b/arch/arm/mach-sa1100/include/mach/hardware.h @@ -76,11 +76,4 @@ static inline unsigned long get_clock_tick_rate(void) #include "SA-1101.h" #endif -#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI) -#define PCIBIOS_MIN_IO 0 -#define PCIBIOS_MIN_MEM 0 -#define HAVE_ARCH_PCI_SET_DMA_MASK 1 -#endif - - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c index fba7a913f12b..5fc074fe3eee 100644 --- a/arch/arm/mach-sa1100/pci-nanoengine.c +++ b/arch/arm/mach-sa1100/pci-nanoengine.c @@ -252,6 +252,9 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) { int ret = 0; + pcibios_min_io = 0; + pcibios_min_mem = 0; + if (nr == 0) { sys->mem_offset = NANO_PCI_MEM_RW_PHYS; sys->io_offset = 0x400; |