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authorSeungwhan Youn <sw.youn@samsung.com>2010-10-14 05:39:08 +0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 11:05:56 +0400
commitd4b34c6c849d67b7afaa90d55dc7fab981c72950 (patch)
treec6b5c6bfe622832865a98fecec1159cb350bc18a /arch/arm/mach-s5pc100
parent900fa0196c564895bfa2eb412d2a83421d3f3444 (diff)
downloadlinux-d4b34c6c849d67b7afaa90d55dc7fab981c72950.tar.xz
ARM: S5P: Reduce duplicated EPLL control codes
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r--arch/arm/mach-s5pc100/clock.c22
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 306ae743ad72..42c2636ca3ac 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = {
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
};
-static int s5pc100_epll_enable(struct clk *clk, int enable)
-{
- unsigned int ctrlbit = clk->ctrlbit;
- unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
- if (enable)
- __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
- else
- __raw_writel(epll_con, S5P_EPLL_CON);
-
- return 0;
-}
-
-static unsigned long s5pc100_epll_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
static u32 epll_div[][4] = {
{ 32750000, 131, 3, 4 },
{ 32768000, 131, 3, 4 },
@@ -347,7 +329,7 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
}
static struct clk_ops s5pc100_epll_ops = {
- .get_rate = s5pc100_epll_get_rate,
+ .get_rate = s5p_epll_get_rate,
.set_rate = s5pc100_epll_set_rate,
};
@@ -1261,7 +1243,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
unsigned int ptr;
/* Set S5PC100 functions for clk_fout_epll */
- clk_fout_epll.enable = s5pc100_epll_enable;
+ clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5pc100_epll_ops;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);