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authorDaniel Vetter <daniel.vetter@ffwll.ch>2015-09-22 12:02:18 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-09-24 18:18:41 +0300
commit646db260b843d2f758559a5483174354c304acf8 (patch)
tree73cf06896311567e8fcb75730d4461fd689a3d3f /arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h
parenta645654b817feba05e5156345325d19fc85ebc9f (diff)
parent1f93e4a96c9109378204c147b3eec0d0e8100fde (diff)
downloadlinux-646db260b843d2f758559a5483174354c304acf8.tar.xz
Merge tag 'v4.3-rc2' into topic/drm-misc
Backmerge Linux 4.3-rc2 because of conflicts in the dp helper code between bugfixes and new code. Just adjacent lines really. On top of that there's a silent conflict in the new fsl-dcu driver merged into 4.3 and commit 844f9111f6f54f88eb2f0fac121b82ce77193866 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Wed Sep 2 10:42:40 2015 +0200 drm/atomic: Make prepare_fb/cleanup_fb only take state, v3. which Thierry Reding spotted and provided a fixup for. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h')
-rw-r--r--arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h b/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..eae3c311e590
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB2.0 Highspeed/OtG device PHY registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Note, this is a separate header file as some of the clock framework
+ * needs to touch this if the clk_48m is used as the USB OHCI or other
+ * peripheral source.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
+#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
+
+/* S3C64XX_PA_USB_HSPHY */
+
+#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
+
+#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
+#define S3C_PHYPWR_NORMAL_MASK (0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE (1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3)
+#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
+
+#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
+#define S3C_PHYCLK_MODE_USB11 (1 << 6)
+#define S3C_PHYCLK_EXT_OSC (1 << 5)
+#define S3C_PHYCLK_CLK_FORCE (1 << 4)
+#define S3C_PHYCLK_ID_PULL (1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT (0)
+#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
+
+#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
+#define S3C_RSTCON_PHYCLK (1 << 2)
+#define S3C_RSTCON_HCLK (1 << 1)
+#define S3C_RSTCON_PHY (1 << 0)
+
+#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
+
+#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */