ARM: s3c: move into a common directory

s3c24xx and s3c64xx have a lot in common, but are split across three
separate directories, which makes the interaction of the header files
more complicated than necessary.

Move all three directories into a new mach-s3c, with a minimal
set of changes to each file.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[krzk: Rebase, add s3c24xx and s3c64xx suffix to several files, add SPDX
       headers to new files, remove plat-samsung from MAINTAINERS]
Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
https://lore.kernel.org/r/20200806182059.2431-39-krzk@kernel.org

8 files changed, 0 insertions, 766 deletions

diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
deleted file mode 100644
index 40ca8de21096..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400 - DMA support
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H __FILE__
-
-#define S3C64XX_DMA_CHAN(name)		((unsigned long)(name))
-
-/* DMA0/SDMA0 */
-#define DMACH_UART0		"uart0_tx"
-#define DMACH_UART0_SRC2	"uart0_rx"
-#define DMACH_UART1		"uart1_tx"
-#define DMACH_UART1_SRC2	"uart1_rx"
-#define DMACH_UART2		"uart2_tx"
-#define DMACH_UART2_SRC2	"uart2_rx"
-#define DMACH_UART3		"uart3_tx"
-#define DMACH_UART3_SRC2	"uart3_rx"
-#define DMACH_PCM0_TX		"pcm0_tx"
-#define DMACH_PCM0_RX		"pcm0_rx"
-#define DMACH_I2S0_OUT		"i2s0_tx"
-#define DMACH_I2S0_IN		"i2s0_rx"
-#define DMACH_SPI0_TX		S3C64XX_DMA_CHAN("spi0_tx")
-#define DMACH_SPI0_RX		S3C64XX_DMA_CHAN("spi0_rx")
-#define DMACH_HSI_I2SV40_TX	"i2s2_tx"
-#define DMACH_HSI_I2SV40_RX	"i2s2_rx"
-
-/* DMA1/SDMA1 */
-#define DMACH_PCM1_TX		"pcm1_tx"
-#define DMACH_PCM1_RX		"pcm1_rx"
-#define DMACH_I2S1_OUT		"i2s1_tx"
-#define DMACH_I2S1_IN		"i2s1_rx"
-#define DMACH_SPI1_TX		S3C64XX_DMA_CHAN("spi1_tx")
-#define DMACH_SPI1_RX		S3C64XX_DMA_CHAN("spi1_rx")
-#define DMACH_AC97_PCMOUT	"ac97_out"
-#define DMACH_AC97_PCMIN	"ac97_in"
-#define DMACH_AC97_MICIN	"ac97_mic"
-#define DMACH_PWM		"pwm"
-#define DMACH_IRDA		"irda"
-#define DMACH_EXTERNAL		"external"
-#define DMACH_SECURITY_RX	"sec_rx"
-#define DMACH_SECURITY_TX	"sec_tx"
-
-enum dma_ch {
-	DMACH_MAX = 32
-};
-
-#include <linux/amba/pl08x.h>
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h
deleted file mode 100644
index 8ed144a0d474..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C6400 - GPIO lib support
- */
-
-#ifndef GPIO_SAMSUNG_S3C64XX_H
-#define GPIO_SAMSUNG_S3C64XX_H
-
-#ifdef CONFIG_GPIO_SAMSUNG
-
-/* GPIO bank sizes */
-#define S3C64XX_GPIO_A_NR	(8)
-#define S3C64XX_GPIO_B_NR	(7)
-#define S3C64XX_GPIO_C_NR	(8)
-#define S3C64XX_GPIO_D_NR	(5)
-#define S3C64XX_GPIO_E_NR	(5)
-#define S3C64XX_GPIO_F_NR	(16)
-#define S3C64XX_GPIO_G_NR	(7)
-#define S3C64XX_GPIO_H_NR	(10)
-#define S3C64XX_GPIO_I_NR	(16)
-#define S3C64XX_GPIO_J_NR	(12)
-#define S3C64XX_GPIO_K_NR	(16)
-#define S3C64XX_GPIO_L_NR	(15)
-#define S3C64XX_GPIO_M_NR	(6)
-#define S3C64XX_GPIO_N_NR	(16)
-#define S3C64XX_GPIO_O_NR	(16)
-#define S3C64XX_GPIO_P_NR	(15)
-#define S3C64XX_GPIO_Q_NR	(9)
-
-/* GPIO bank numbes */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-
-#define S3C64XX_GPIO_NEXT(__gpio) \
-	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s3c_gpio_number {
-	S3C64XX_GPIO_A_START = 0,
-	S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
-	S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
-	S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
-	S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
-	S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
-	S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
-	S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
-	S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
-	S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
-	S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
-	S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
-	S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
-	S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
-	S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
-	S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
-	S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
-};
-
-/* S3C64XX GPIO number definitions. */
-
-#define S3C64XX_GPA(_nr)	(S3C64XX_GPIO_A_START + (_nr))
-#define S3C64XX_GPB(_nr)	(S3C64XX_GPIO_B_START + (_nr))
-#define S3C64XX_GPC(_nr)	(S3C64XX_GPIO_C_START + (_nr))
-#define S3C64XX_GPD(_nr)	(S3C64XX_GPIO_D_START + (_nr))
-#define S3C64XX_GPE(_nr)	(S3C64XX_GPIO_E_START + (_nr))
-#define S3C64XX_GPF(_nr)	(S3C64XX_GPIO_F_START + (_nr))
-#define S3C64XX_GPG(_nr)	(S3C64XX_GPIO_G_START + (_nr))
-#define S3C64XX_GPH(_nr)	(S3C64XX_GPIO_H_START + (_nr))
-#define S3C64XX_GPI(_nr)	(S3C64XX_GPIO_I_START + (_nr))
-#define S3C64XX_GPJ(_nr)	(S3C64XX_GPIO_J_START + (_nr))
-#define S3C64XX_GPK(_nr)	(S3C64XX_GPIO_K_START + (_nr))
-#define S3C64XX_GPL(_nr)	(S3C64XX_GPIO_L_START + (_nr))
-#define S3C64XX_GPM(_nr)	(S3C64XX_GPIO_M_START + (_nr))
-#define S3C64XX_GPN(_nr)	(S3C64XX_GPIO_N_START + (_nr))
-#define S3C64XX_GPO(_nr)	(S3C64XX_GPIO_O_START + (_nr))
-#define S3C64XX_GPP(_nr)	(S3C64XX_GPIO_P_START + (_nr))
-#define S3C64XX_GPQ(_nr)	(S3C64XX_GPIO_Q_START + (_nr))
-
-/* the end of the S3C64XX specific gpios */
-#define S3C64XX_GPIO_END	(S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
-#define S3C_GPIO_END		S3C64XX_GPIO_END
-
-/* define the number of gpios we need to the one after the GPQ() range */
-#define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
-
-#endif /* GPIO_SAMSUNG */
-#endif /* GPIO_SAMSUNG_S3C64XX_H */
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
deleted file mode 100644
index c244e480e6b3..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - IRQ support
- */
-
-#ifndef __ASM_MACH_S3C64XX_IRQS_H
-#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- *
- * note, since we're using the VICs, our start must be a
- * mulitple of 32 to allow the common code to work
- */
-
-#define S3C_IRQ_OFFSET	(32)
-
-#define S3C_IRQ(x)	((x) + S3C_IRQ_OFFSET)
-
-#define IRQ_VIC0_BASE	S3C_IRQ(0)
-#define IRQ_VIC1_BASE	S3C_IRQ(32)
-
-/* VIC based IRQs */
-
-#define S3C64XX_IRQ_VIC0(x)	(IRQ_VIC0_BASE + (x))
-#define S3C64XX_IRQ_VIC1(x)	(IRQ_VIC1_BASE + (x))
-
-/* VIC0 */
-
-#define IRQ_EINT0_3		S3C64XX_IRQ_VIC0(0)
-#define IRQ_EINT4_11		S3C64XX_IRQ_VIC0(1)
-#define IRQ_RTC_TIC		S3C64XX_IRQ_VIC0(2)
-#define IRQ_CAMIF_C		S3C64XX_IRQ_VIC0(3)
-#define IRQ_CAMIF_P		S3C64XX_IRQ_VIC0(4)
-#define IRQ_CAMIF_MC		S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIC1	S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIS		S3C64XX_IRQ_VIC0(6)
-#define IRQ_S3C6400_CAMIF_MP	S3C64XX_IRQ_VIC0(6)
-#define IRQ_CAMIF_WE_C		S3C64XX_IRQ_VIC0(7)
-#define IRQ_S3C6410_G3D		S3C64XX_IRQ_VIC0(8)
-#define IRQ_S3C6400_CAMIF_WE_P	S3C64XX_IRQ_VIC0(8)
-#define IRQ_POST0		S3C64XX_IRQ_VIC0(9)
-#define IRQ_ROTATOR		S3C64XX_IRQ_VIC0(10)
-#define IRQ_2D			S3C64XX_IRQ_VIC0(11)
-#define IRQ_TVENC		S3C64XX_IRQ_VIC0(12)
-#define IRQ_SCALER		S3C64XX_IRQ_VIC0(13)
-#define IRQ_BATF		S3C64XX_IRQ_VIC0(14)
-#define IRQ_JPEG		S3C64XX_IRQ_VIC0(15)
-#define IRQ_MFC			S3C64XX_IRQ_VIC0(16)
-#define IRQ_SDMA0		S3C64XX_IRQ_VIC0(17)
-#define IRQ_SDMA1		S3C64XX_IRQ_VIC0(18)
-#define IRQ_ARM_DMAERR		S3C64XX_IRQ_VIC0(19)
-#define IRQ_ARM_DMA		S3C64XX_IRQ_VIC0(20)
-#define IRQ_ARM_DMAS		S3C64XX_IRQ_VIC0(21)
-#define IRQ_KEYPAD		S3C64XX_IRQ_VIC0(22)
-#define IRQ_TIMER0_VIC		S3C64XX_IRQ_VIC0(23)
-#define IRQ_TIMER1_VIC		S3C64XX_IRQ_VIC0(24)
-#define IRQ_TIMER2_VIC		S3C64XX_IRQ_VIC0(25)
-#define IRQ_WDT			S3C64XX_IRQ_VIC0(26)
-#define IRQ_TIMER3_VIC		S3C64XX_IRQ_VIC0(27)
-#define IRQ_TIMER4_VIC		S3C64XX_IRQ_VIC0(28)
-#define IRQ_LCD_FIFO		S3C64XX_IRQ_VIC0(29)
-#define IRQ_LCD_VSYNC		S3C64XX_IRQ_VIC0(30)
-#define IRQ_LCD_SYSTEM		S3C64XX_IRQ_VIC0(31)
-
-/* VIC1 */
-
-#define IRQ_EINT12_19		S3C64XX_IRQ_VIC1(0)
-#define IRQ_EINT20_27		S3C64XX_IRQ_VIC1(1)
-#define IRQ_PCM0		S3C64XX_IRQ_VIC1(2)
-#define IRQ_PCM1		S3C64XX_IRQ_VIC1(3)
-#define IRQ_AC97		S3C64XX_IRQ_VIC1(4)
-#define IRQ_UART0		S3C64XX_IRQ_VIC1(5)
-#define IRQ_UART1		S3C64XX_IRQ_VIC1(6)
-#define IRQ_UART2		S3C64XX_IRQ_VIC1(7)
-#define IRQ_UART3		S3C64XX_IRQ_VIC1(8)
-#define IRQ_DMA0		S3C64XX_IRQ_VIC1(9)
-#define IRQ_DMA1		S3C64XX_IRQ_VIC1(10)
-#define IRQ_ONENAND0		S3C64XX_IRQ_VIC1(11)
-#define IRQ_ONENAND1		S3C64XX_IRQ_VIC1(12)
-#define IRQ_NFC			S3C64XX_IRQ_VIC1(13)
-#define IRQ_CFCON		S3C64XX_IRQ_VIC1(14)
-#define IRQ_USBH		S3C64XX_IRQ_VIC1(15)
-#define IRQ_SPI0		S3C64XX_IRQ_VIC1(16)
-#define IRQ_SPI1		S3C64XX_IRQ_VIC1(17)
-#define IRQ_IIC			S3C64XX_IRQ_VIC1(18)
-#define IRQ_HSItx		S3C64XX_IRQ_VIC1(19)
-#define IRQ_HSIrx		S3C64XX_IRQ_VIC1(20)
-#define IRQ_RESERVED		S3C64XX_IRQ_VIC1(21)
-#define IRQ_MSM			S3C64XX_IRQ_VIC1(22)
-#define IRQ_HOSTIF		S3C64XX_IRQ_VIC1(23)
-#define IRQ_HSMMC0		S3C64XX_IRQ_VIC1(24)
-#define IRQ_HSMMC1		S3C64XX_IRQ_VIC1(25)
-#define IRQ_HSMMC2		IRQ_SPI1	/* shared with SPI1 */
-#define IRQ_OTG			S3C64XX_IRQ_VIC1(26)
-#define IRQ_IRDA		S3C64XX_IRQ_VIC1(27)
-#define IRQ_RTC_ALARM		S3C64XX_IRQ_VIC1(28)
-#define IRQ_SEC			S3C64XX_IRQ_VIC1(29)
-#define IRQ_PENDN		S3C64XX_IRQ_VIC1(30)
-#define IRQ_TC			IRQ_PENDN
-#define IRQ_ADC			S3C64XX_IRQ_VIC1(31)
-
-/* compatibility for device defines */
-
-#define IRQ_IIC1		IRQ_S3C6410_IIC1
-
-/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
- * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
- * which we place after the pair of VICs. */
-
-#define S3C_IRQ_EINT_BASE	S3C_IRQ(64+5)
-
-#define S3C_EINT(x)		((x) + S3C_IRQ_EINT_BASE)
-#define IRQ_EINT(x)		S3C_EINT(x)
-#define IRQ_EINT_BIT(x)		((x) - S3C_EINT(0))
-
-/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
- * that they are sourced from the GPIO pins but with a different scheme for
- * priority and source indication.
- *
- * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
- * interrupts, but for historical reasons they are kept apart from these
- * next interrupts.
- *
- * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
- * machine specific support files.
- */
-
-#define IRQ_EINT_GROUP1_NR	(15)
-#define IRQ_EINT_GROUP2_NR	(8)
-#define IRQ_EINT_GROUP3_NR	(5)
-#define IRQ_EINT_GROUP4_NR	(14)
-#define IRQ_EINT_GROUP5_NR	(7)
-#define IRQ_EINT_GROUP6_NR	(10)
-#define IRQ_EINT_GROUP7_NR	(16)
-#define IRQ_EINT_GROUP8_NR	(15)
-#define IRQ_EINT_GROUP9_NR	(9)
-
-#define IRQ_EINT_GROUP_BASE	S3C_EINT(28)
-#define IRQ_EINT_GROUP1_BASE	(IRQ_EINT_GROUP_BASE + 0x00)
-#define IRQ_EINT_GROUP2_BASE	(IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
-#define IRQ_EINT_GROUP3_BASE	(IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
-#define IRQ_EINT_GROUP4_BASE	(IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
-#define IRQ_EINT_GROUP5_BASE	(IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
-#define IRQ_EINT_GROUP6_BASE	(IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
-#define IRQ_EINT_GROUP7_BASE	(IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
-#define IRQ_EINT_GROUP8_BASE	(IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
-#define IRQ_EINT_GROUP9_BASE	(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
-
-#define IRQ_EINT_GROUP(group, no)	(IRQ_EINT_GROUP##group##_BASE + (no))
-
-/* Some boards have their own IRQs behind this */
-#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
-
-/* Set the default nr_irqs, boards can override if necessary */
-#define S3C64XX_NR_IRQS	IRQ_BOARD_START
-
-/* Compatibility */
-
-#define IRQ_ONENAND	IRQ_ONENAND0
-#define IRQ_I2S0	IRQ_S3C6410_IIS
-
-#endif /* __ASM_MACH_S3C64XX_IRQS_H */
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
deleted file mode 100644
index 9372a535b7ba..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - Memory map definitions
- */
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s3c.h>
-
-/*
- * Post-mux Chip Select Regions Xm0CSn_
- * These may be used by SROM, NAND or CF depending on settings
- */
-
-#define S3C64XX_PA_XM0CSN0 (0x10000000)
-#define S3C64XX_PA_XM0CSN1 (0x18000000)
-#define S3C64XX_PA_XM0CSN2 (0x20000000)
-#define S3C64XX_PA_XM0CSN3 (0x28000000)
-#define S3C64XX_PA_XM0CSN4 (0x30000000)
-#define S3C64XX_PA_XM0CSN5 (0x38000000)
-
-/* HSMMC units */
-#define S3C64XX_PA_HSMMC(x)	(0x7C200000 + ((x) * 0x100000))
-#define S3C64XX_PA_HSMMC0	S3C64XX_PA_HSMMC(0)
-#define S3C64XX_PA_HSMMC1	S3C64XX_PA_HSMMC(1)
-#define S3C64XX_PA_HSMMC2	S3C64XX_PA_HSMMC(2)
-
-#define S3C_PA_UART		(0x7F005000)
-#define S3C_PA_UART0		(S3C_PA_UART + 0x00)
-#define S3C_PA_UART1		(S3C_PA_UART + 0x400)
-#define S3C_PA_UART2		(S3C_PA_UART + 0x800)
-#define S3C_PA_UART3		(S3C_PA_UART + 0xC00)
-#define S3C_UART_OFFSET		(0x400)
-
-/* See notes on UART VA mapping in debug-macro.S */
-#define S3C_VA_UARTx(x)	(S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
-
-#define S3C_VA_UART0		S3C_VA_UARTx(0)
-#define S3C_VA_UART1		S3C_VA_UARTx(1)
-#define S3C_VA_UART2		S3C_VA_UARTx(2)
-#define S3C_VA_UART3		S3C_VA_UARTx(3)
-
-#define S3C64XX_PA_SROM		(0x70000000)
-
-#define S3C64XX_PA_ONENAND0	(0x70100000)
-#define S3C64XX_PA_ONENAND0_BUF	(0x20000000)
-#define S3C64XX_SZ_ONENAND0_BUF (SZ_64M)
-
-/* NAND and OneNAND1 controllers occupy the same register region
-   (depending on SoC POP version) */
-#define S3C64XX_PA_ONENAND1	(0x70200000)
-#define S3C64XX_PA_ONENAND1_BUF	(0x28000000)
-#define S3C64XX_SZ_ONENAND1_BUF	(SZ_64M)
-
-#define S3C64XX_PA_NAND		(0x70200000)
-#define S3C64XX_PA_FB		(0x77100000)
-#define S3C64XX_PA_USB_HSOTG	(0x7C000000)
-#define S3C64XX_PA_WATCHDOG	(0x7E004000)
-#define S3C64XX_PA_RTC		(0x7E005000)
-#define S3C64XX_PA_KEYPAD	(0x7E00A000)
-#define S3C64XX_PA_ADC		(0x7E00B000)
-#define S3C64XX_PA_SYSCON	(0x7E00F000)
-#define S3C64XX_PA_AC97		(0x7F001000)
-#define S3C64XX_PA_IIS0		(0x7F002000)
-#define S3C64XX_PA_IIS1		(0x7F003000)
-#define S3C64XX_PA_TIMER	(0x7F006000)
-#define S3C64XX_PA_IIC0		(0x7F004000)
-#define S3C64XX_PA_SPI0		(0x7F00B000)
-#define S3C64XX_PA_SPI1		(0x7F00C000)
-#define S3C64XX_PA_PCM0		(0x7F009000)
-#define S3C64XX_PA_PCM1		(0x7F00A000)
-#define S3C64XX_PA_IISV4	(0x7F00D000)
-#define S3C64XX_PA_IIC1		(0x7F00F000)
-
-#define S3C64XX_PA_GPIO		(0x7F008000)
-#define S3C64XX_SZ_GPIO		SZ_4K
-
-#define S3C64XX_PA_SDRAM	(0x50000000)
-
-#define S3C64XX_PA_CFCON	(0x70300000)
-
-#define S3C64XX_PA_VIC0		(0x71200000)
-#define S3C64XX_PA_VIC1		(0x71300000)
-
-#define S3C64XX_PA_MODEM	(0x74108000)
-
-#define S3C64XX_PA_USBHOST	(0x74300000)
-
-#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
-
-/* compatibility defines. */
-#define S3C_PA_TIMER		S3C64XX_PA_TIMER
-#define S3C_PA_HSMMC0		S3C64XX_PA_HSMMC0
-#define S3C_PA_HSMMC1		S3C64XX_PA_HSMMC1
-#define S3C_PA_HSMMC2		S3C64XX_PA_HSMMC2
-#define S3C_PA_IIC		S3C64XX_PA_IIC0
-#define S3C_PA_IIC1		S3C64XX_PA_IIC1
-#define S3C_PA_NAND		S3C64XX_PA_NAND
-#define S3C_PA_ONENAND		S3C64XX_PA_ONENAND0
-#define S3C_PA_ONENAND_BUF	S3C64XX_PA_ONENAND0_BUF
-#define S3C_SZ_ONENAND_BUF	S3C64XX_SZ_ONENAND0_BUF
-#define S3C_PA_FB		S3C64XX_PA_FB
-#define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
-#define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
-#define S3C_PA_RTC		S3C64XX_PA_RTC
-#define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
-#define S3C_PA_SPI0		S3C64XX_PA_SPI0
-#define S3C_PA_SPI1		S3C64XX_PA_SPI1
-
-#define SAMSUNG_PA_ADC		S3C64XX_PA_ADC
-#define SAMSUNG_PA_CFCON	S3C64XX_PA_CFCON
-#define SAMSUNG_PA_KEYPAD	S3C64XX_PA_KEYPAD
-#define SAMSUNG_PA_TIMER	S3C64XX_PA_TIMER
-
-#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
deleted file mode 100644
index 33cf242734a0..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
- */
-
-#ifndef __MACH_S3C64XX_PM_CORE_H
-#define __MACH_S3C64XX_PM_CORE_H __FILE__
-
-#include <linux/serial_s3c.h>
-#include <linux/delay.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <mach/map.h>
-
-static inline void s3c_pm_debug_init_uart(void)
-{
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-	u32 tmp = __raw_readl(S3C_PCLK_GATE);
-
-	/* As a note, since the S3C64XX UARTs generally have multiple
-	 * clock sources, we simply enable PCLK at the moment and hope
-	 * that the resume settings for the UART are suitable for the
-	 * use with PCLK.
-	 */
-
-	tmp |= S3C_CLKCON_PCLK_UART0;
-	tmp |= S3C_CLKCON_PCLK_UART1;
-	tmp |= S3C_CLKCON_PCLK_UART2;
-	tmp |= S3C_CLKCON_PCLK_UART3;
-
-	__raw_writel(tmp, S3C_PCLK_GATE);
-	udelay(10);
-#endif
-}
-
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-	/* VIC should have already been taken care of */
-
-	/* clear any pending EINT0 interrupts */
-	__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
-}
-
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-}
-
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-}
-
-/* make these defines, we currently do not have any need to change
- * the IRQ wake controls depending on the CPU we are running on */
-#ifdef CONFIG_PM_SLEEP
-#define s3c_irqwake_eintallow	((1 << 28) - 1)
-#define s3c_irqwake_intallow	(~0)
-#else
-#define s3c_irqwake_eintallow 0
-#define s3c_irqwake_intallow  0
-#endif
-
-static inline void s3c_pm_restored_gpios(void)
-{
-	/* ensure sleep mode has been cleared from the system */
-
-	__raw_writel(0, S3C64XX_SLPEN);
-}
-
-static inline void samsung_pm_saved_gpios(void)
-{
-	/* turn on the sleep mode and keep it there, as it seems that during
-	 * suspend the xCON registers get re-set and thus you can end up with
-	 * problems between going to sleep and resuming.
-	 */
-
-	__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
-}
-#endif /* __MACH_S3C64XX_PM_CORE_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
deleted file mode 100644
index 35a68767b318..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	Ben Dooks <ben@simtec.co.uk>
- *	http://armlinux.simtec.co.uk/
- *
- * S3C64XX clock register definitions
- */
-
-#ifndef __PLAT_REGS_CLOCK_H
-#define __PLAT_REGS_CLOCK_H __FILE__
-
-/*
- * FIXME: Remove remaining definitions
- */
-
-#define S3C_CLKREG(x)		(S3C_VA_SYS + (x))
-
-#define S3C_PCLK_GATE		S3C_CLKREG(0x34)
-#define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)
-#define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)
-
-/* PCLK GATE Registers */
-#define S3C_CLKCON_PCLK_UART3		(1<<4)
-#define S3C_CLKCON_PCLK_UART2		(1<<3)
-#define S3C_CLKCON_PCLK_UART1		(1<<2)
-#define S3C_CLKCON_PCLK_UART0		(1<<1)
-
-/* MEM_SYS_CFG */
-#define MEM_SYS_CFG_INDEP_CF		0x4000
-#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30
-
-#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
deleted file mode 100644
index 592a2be3d2aa..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - GPIO register definitions
- */
-
-#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
-#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
-
-/* Base addresses for each of the banks */
-
-#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))
-
-#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
-#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
-#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
-#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
-#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
-#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
-#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
-#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
-#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
-#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
-#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
-#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
-#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
-#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
-#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
-#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
-#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)
-
-/* SPCON */
-
-#define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)
-
-#define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
-#define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
-#define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
-#define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
-#define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
-#define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)
-
-#define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
-#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
-#define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
-#define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
-#define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
-#define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)
-
-#define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
-#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
-#define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
-#define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
-#define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
-#define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)
-
-#define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
-#define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
-#define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
-#define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
-#define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
-#define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)
-
-#define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
-#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
-#define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
-#define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
-#define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
-#define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)
-
-#define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)
-
-#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
-#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
-#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
-#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
-#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
-#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)
-
-#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
-#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
-#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
-#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
-#define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)
-
-#define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
-#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
-#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
-#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
-#define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)
-
-#define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
-#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
-#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
-#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
-#define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)
-
-#define S3C64XX_SPCON_MEM0_D_PUD_MASK		(0x3 << 8)
-#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT		(8)
-#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED	(0x0 << 8)
-#define S3C64XX_SPCON_MEM0_D_PUD_DOWN		(0x1 << 8)
-#define S3C64XX_SPCON_MEM0_D_PUD_UP		(0x2 << 8)
-
-#define S3C64XX_SPCON_USBH_DMPD			(1 << 7)
-#define S3C64XX_SPCON_USBH_DPPD			(1 << 6)
-#define S3C64XX_SPCON_USBH_PUSW2		(1 << 5)
-#define S3C64XX_SPCON_USBH_PUSW1		(1 << 4)
-#define S3C64XX_SPCON_USBH_SUSPND		(1 << 3)
-
-#define S3C64XX_SPCON_LCD_SEL_MASK		(0x3 << 0)
-#define S3C64XX_SPCON_LCD_SEL_SHIFT		(0)
-#define S3C64XX_SPCON_LCD_SEL_HOST		(0x0 << 0)
-#define S3C64XX_SPCON_LCD_SEL_RGB		(0x1 << 0)
-#define S3C64XX_SPCON_LCD_SEL_606_656		(0x2 << 0)
-
-
-/* External interrupt registers */
-
-#define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
-#define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
-#define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
-#define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
-#define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)
-
-#define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
-#define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
-#define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
-#define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
-#define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)
-
-#define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
-#define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
-#define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
-#define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
-#define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)
-
-#define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
-#define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
-#define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
-#define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
-#define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)
-
-#define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
-#define S3C64XX_PRIORITY_ARB(x)	(1 << (x))
-
-#define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
-#define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)
-
-#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
-#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
-#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
-#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
-#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
-#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)
-
-#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
-#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)
-
-/* GPIO sleep configuration */
-
-#define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)
-
-#define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
-#define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)
-
-#define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
-#define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
-#define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
-#define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)
-
-#define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
-#define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
-#define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
-#define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)
-
-
-#define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)
-
-#define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
-#define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)
-
-#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
deleted file mode 100644
index b18c7bcb61c5..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *	http://armlinux.simtec.co.uk/
- *	Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - IRQ register definitions
- */
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-
-#endif /* __ASM_ARCH_6400_REGS_IRQ_H */