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| author | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-03 03:57:03 +0400 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-07 13:36:33 +0400 |
| commit | 880bcd4a8363f24375027f9ded4670960dcfa70a (patch) | |
| tree | 31894d9dc2c29f31234e479de520a50858cce54c /arch/arm/mach-s3c24xx/include/mach/regs-power.h | |
| parent | a5f17d1f4c2831b9b9bf8b1a537cdbac995d6e13 (diff) | |
| parent | 8c3d7c30c306d83ff9c303f42307765a5a7bc254 (diff) | |
| download | linux-880bcd4a8363f24375027f9ded4670960dcfa70a.tar.xz | |
Merge branch 'topic/cleanup-s3c24xx' into next/cleanup-s3c24xx
Conflicts:
arch/arm/mach-s3c24xx/include/mach/system.h
Diffstat (limited to 'arch/arm/mach-s3c24xx/include/mach/regs-power.h')
| -rw-r--r-- | arch/arm/mach-s3c24xx/include/mach/regs-power.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h new file mode 100644 index 000000000000..4932b87bdf3d --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/regs-power.h @@ -0,0 +1,40 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-power.h + * + * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24XX power control register definitions +*/ + +#ifndef __ASM_ARM_REGS_PWR +#define __ASM_ARM_REGS_PWR __FILE__ + +#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) + +#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) +#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) + +#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) +#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) +#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) +#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) + +#define S3C2412_PWRCFG_BATF_IRQ (1<<0) +#define S3C2412_PWRCFG_BATF_IGNORE (2<<0) +#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) +#define S3C2412_PWRCFG_BATF_MASK (3<<0) + +#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) +#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) +#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) +#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) +#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) + +#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) +#define S3C2412_PWRCFG_NAND_NORST (1<<9) + +#endif /* __ASM_ARM_REGS_PWR */ |