Merge branch 'next/cleanup-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

* 'next/cleanup-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits)
  ARM: S3C24XX: remove call to s3c24xx_setup_clocks
  ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
  ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
  ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
  ARM: S3C24XX: remove obsolete S3C2416_DMA option
  ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
  ARM: S3C24XX: Fix indentation of dma-s3c2443
  ARM: S3C24XX: Move device setup files to mach directory
  ARM: S3C24XX: Consolidate Simtec extensions
  ARM: S3C24XX: move simtec-specific code to mach directory
  ARM: S3C24XX: Move common-smdk code to mach directory
  ARM: S3C24XX: Move s3c2443-clock.c to mach-s3c24xx
  ARM: s3c2410_defconfig: update s3c2410_defconfig
  ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/
  ARM: S3C2440: move mach-s3c2440/* into mach-s3c24xx/
  ARM: S3C2416: move mach-s3c2416/* into mach-s3c24xx/
  ARM: S3C2412: move mach-s3c2412/* into mach-s3c24xx/
  ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
  ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX
  ARM: S3C2410: move s3c2410_baseclk_add to clock.h
  ...

1 files changed, 70 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7615a14773fa
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/mach-s3c2410/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for S3C2410-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+/* We have a problem that the INTOFFSET register does not always
+ * show one interrupt. Occasionally we get two interrupts through
+ * the prioritiser, and this causes the INTOFFSET register to show
+ * what looks like the logical-or of the two interrupt numbers.
+ *
+ * Thanks to Klaus, Shannon, et al for helping to debug this problem
+*/
+
+#define INTPND		(0x10)
+#define INTOFFSET	(0x14)
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+	.macro  get_irqnr_preamble, base, tmp
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		mov	\base, #S3C24XX_VA_IRQ
+
+		@@ try the interrupt offset register, since it is there
+
+		ldr	\irqstat, [ \base, #INTPND ]
+		teq	\irqstat, #0
+		beq	1002f
+		ldr	\irqnr, [ \base, #INTOFFSET ]
+		mov	\tmp, #1
+		tst	\irqstat, \tmp, lsl \irqnr
+		bne	1001f
+
+		@@ the number specified is not a valid irq, so try
+		@@ and work it out for ourselves
+
+		mov	\irqnr, #0		@@ start here
+
+		@@ work out which irq (if any) we got
+
+		movs	\tmp, \irqstat, lsl#16
+		addeq	\irqnr, \irqnr, #16
+		moveq	\irqstat, \irqstat, lsr#16
+		tst	\irqstat, #0xff
+		addeq	\irqnr, \irqnr, #8
+		moveq	\irqstat, \irqstat, lsr#8
+		tst	\irqstat, #0xf
+		addeq	\irqnr, \irqnr, #4
+		moveq	\irqstat, \irqstat, lsr#4
+		tst	\irqstat, #0x3
+		addeq	\irqnr, \irqnr, #2
+		moveq	\irqstat, \irqstat, lsr#2
+		tst	\irqstat, #0x1
+		addeq	\irqnr, \irqnr, #1
+
+		@@ we have the value
+1001:
+		adds	\irqnr, \irqnr, #IRQ_EINT0
+1002:
+		@@ exit here, Z flag unset if IRQ
+
+	.endm