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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-19 18:53:54 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 03:49:57 +0400
commit39b53458cc635f103365ef09e9db6980fa01e3fb (patch)
treeb1a95af72dd28f79e1b16c94fe624c0b2217c8e9 /arch/arm/mach-realview/realview_eb.c
parent918197be3992801054ff02fc8183bf9429bab98b (diff)
downloadlinux-39b53458cc635f103365ef09e9db6980fa01e3fb.tar.xz
ARM: l2c: realview: improve commentry about the L2 cache requirements
Add better commentry about the L2 cache requirements on these platforms. Unfortunately, the auxiliary control register is not pre-set to indicate the correct cache parameters, so we have to manually program these. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-realview/realview_eb.c')
-rw-r--r--arch/arm/mach-realview/realview_eb.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index c85ddb2a0ad0..b575895037b8 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -442,8 +442,13 @@ static void __init realview_eb_init(void)
realview_eb11mp_fixup();
#ifdef CONFIG_CACHE_L2X0
- /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
- * Bits: .... ...0 0111 1001 0000 .... .... .... */
+ /*
+ * The PL220 needs to be manually configured as the hardware
+ * doesn't report the correct sizes.
+ * 1MB (128KB/way), 8-way associativity, event monitor and
+ * parity enabled, ignore share bit, no force write allocate
+ * Bits: .... ...0 0111 1001 0000 .... .... ....
+ */
l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
#endif
platform_device_register(&pmu_device);