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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-09 17:09:29 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-09 17:09:29 +0400 |
| commit | 054d5c9238f3c577ad51195c3ee7803613f322cc (patch) | |
| tree | ff7d9f5c0e0ddf14230ba28f28ef69a2c0a0debf /arch/arm/mach-pxa/sleep.S | |
| parent | 11e4afb49b7fa1fc8e1ffd850c1806dd86a08204 (diff) | |
| parent | 2192482ee5ce5d5d4a6cec0c351b2d3a744606eb (diff) | |
| download | linux-054d5c9238f3c577ad51195c3ee7803613f322cc.tar.xz | |
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/arm/mach-pxa/sleep.S')
| -rw-r--r-- | arch/arm/mach-pxa/sleep.S | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 2ed95f369cfc..52c30b01a671 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -339,10 +339,6 @@ ENTRY(pxa_cpu_resume) mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB -#ifdef CONFIG_XSCALE_CACHE_ERRATA - bic r9, r9, #0x0004 @ see cpu_xscale_proc_init -#endif - mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. mcr p15, 0, r4, c15, c1, 0 @ CP access reg mcr p15, 0, r5, c13, c0, 0 @ PID @@ -368,9 +364,6 @@ sleep_save_sp: .text resume_after_mmu: -#ifdef CONFIG_XSCALE_CACHE_ERRATA - bl cpu_xscale_proc_init -#endif ldmfd sp!, {r2, r3} #ifndef CONFIG_IWMMXT mar acc0, r2, r3 |