summaryrefslogtreecommitdiff
path: root/arch/arm/mach-pxa/pxa3xx.c
diff options
context:
space:
mode:
authorDaniel Mack <zonque@gmail.com>2012-07-22 21:50:22 +0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2012-08-16 12:14:50 +0400
commit089d03629b04ebe8163905a2398742b426e35085 (patch)
tree4fbca59c4c1af98d901f8eca8a651801f2025a6f /arch/arm/mach-pxa/pxa3xx.c
parent9450be76d0e3ebedf301aa09e4f98b4d3a175229 (diff)
downloadlinux-089d03629b04ebe8163905a2398742b426e35085.tar.xz
ARM: pxa: add devicetree code for irq handling
Properly register on-chip interrupt using the irqdomain logic. The number of interrupts is taken from the devicetree node. That includes the following changes: - cpu_has_ipr() was converted from an inline function to a static bool variable, so it can be set using the "marvell,intc-priority" property inside the device node of the tree. - IRQ_BASE was converted from a macro to a runtime variable so that it can be initialized dynamically from the DT init code. - irq_base() now uses pxa_irq_base and just adds an offset. Hence, there are now no compile-time fixed values used in case of DT initialization. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa/pxa3xx.c')
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e813d98..1827d3ce2d5b 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -40,6 +40,8 @@
#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
+
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +384,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
pxa_ext_wakeup_chip.irq_set_wake = fn;
}
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
{
/* enable CP6 access */
u32 value;
@@ -390,10 +392,21 @@ void __init pxa3xx_init_irq(void)
value |= (1 << 6);
__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
- pxa_init_irq(56, pxa3xx_set_wake);
pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}
+void __init pxa3xx_init_irq(void)
+{
+ __pxa3xx_init_irq();
+ pxa_init_irq(56, pxa3xx_set_wake);
+}
+
+void __init pxa3xx_dt_init_irq(void)
+{
+ __pxa3xx_init_irq();
+ pxa_dt_irq_init(pxa3xx_set_wake);
+}
+
static struct map_desc pxa3xx_io_desc[] __initdata = {
{ /* Mem Ctl */
.virtual = (unsigned long)SMEMC_VIRT,