diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-08 22:31:16 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-08 22:31:16 +0400 |
| commit | 3f17ea6dea8ba5668873afa54628a91aaa3fb1c0 (patch) | |
| tree | afbeb2accd4c2199ddd705ae943995b143a0af02 /arch/arm/mach-omap2 | |
| parent | 1860e379875dfe7271c649058aeddffe5afd9d0d (diff) | |
| parent | 1a5700bc2d10cd379a795fd2bb377a190af5acd4 (diff) | |
| download | linux-3f17ea6dea8ba5668873afa54628a91aaa3fb1c0.tar.xz | |
Merge branch 'next' (accumulated 3.16 merge window patches) into master
Now that 3.15 is released, this merges the 'next' branch into 'master',
bringing us to the normal situation where my 'master' branch is the
merge window.
* accumulated work in next: (6809 commits)
ufs: sb mutex merge + mutex_destroy
powerpc: update comments for generic idle conversion
cris: update comments for generic idle conversion
idle: remove cpu_idle() forward declarations
nbd: zero from and len fields in NBD_CMD_DISCONNECT.
mm: convert some level-less printks to pr_*
MAINTAINERS: adi-buildroot-devel is moderated
MAINTAINERS: add linux-api for review of API/ABI changes
mm/kmemleak-test.c: use pr_fmt for logging
fs/dlm/debug_fs.c: replace seq_printf by seq_puts
fs/dlm/lockspace.c: convert simple_str to kstr
fs/dlm/config.c: convert simple_str to kstr
mm: mark remap_file_pages() syscall as deprecated
mm: memcontrol: remove unnecessary memcg argument from soft limit functions
mm: memcontrol: clean up memcg zoneinfo lookup
mm/memblock.c: call kmemleak directly from memblock_(alloc|free)
mm/mempool.c: update the kmemleak stack trace for mempool allocations
lib/radix-tree.c: update the kmemleak stack trace for radix tree allocations
mm: introduce kmemleak_update_trace()
mm/kmemleak.c: use %u to print ->checksum
...
Diffstat (limited to 'arch/arm/mach-omap2')
78 files changed, 875 insertions, 646 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d4390d52..0ba482638ebf 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -65,6 +65,7 @@ config SOC_AM43XX select ARCH_HAS_OPP select ARM_GIC select MACH_OMAP_GENERIC + select MIGHT_HAVE_CACHE_L2X0 config SOC_DRA7XX bool "TI DRA7XX" diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 543d9a882de3..4f9383cecf76 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -262,12 +262,7 @@ static struct usbhs_phy_data phy_data[] __initdata = { static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, -#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ - defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) - .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, -#else .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, -#endif }; #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index b6885e42c0a0..e87f2a83d6bf 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void) if (!fpga_map_addr) return -ENOMEM; - if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV))) + if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV))) /* we dont have an DEBUG FPGA??? */ /* Depend on #defines!! default to strata boot return param */ goto unmap; /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ - cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; + cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ if (omap_rev() >= OMAP3430_REV_ES1_0) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index b8920b6bc104..9480997ba616 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -43,7 +43,7 @@ static void __init omap_generic_init(void) } #ifdef CONFIG_SOC_OMAP2420 -static const char *omap242x_boards_compat[] __initdata = { +static const char *omap242x_boards_compat[] __initconst = { "ti,omap2420", NULL, }; @@ -62,7 +62,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP2430 -static const char *omap243x_boards_compat[] __initdata = { +static const char *omap243x_boards_compat[] __initconst = { "ti,omap2430", NULL, }; @@ -81,7 +81,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 -static const char *omap3_boards_compat[] __initdata = { +static const char *omap3_boards_compat[] __initconst = { "ti,omap3430", "ti,omap3", NULL, @@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap36xx_boards_compat[] __initdata = { +static const char *omap36xx_boards_compat[] __initconst = { "ti,omap36xx", NULL, }; @@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap3_gp_boards_compat[] __initdata = { +static const char *omap3_gp_boards_compat[] __initconst = { "ti,omap3-beagle", "timll,omap3-devkit8000", NULL, @@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *am3517_boards_compat[] __initdata = { +static const char *am3517_boards_compat[] __initconst = { "ti,am3517", NULL, }; @@ -157,7 +157,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM33XX -static const char *am33xx_boards_compat[] __initdata = { +static const char *am33xx_boards_compat[] __initconst = { "ti,am33xx", NULL, }; @@ -177,7 +177,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 -static const char *omap4_boards_compat[] __initdata = { +static const char *omap4_boards_compat[] __initconst = { "ti,omap4460", "ti,omap4430", "ti,omap4", @@ -199,7 +199,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP5 -static const char *omap5_boards_compat[] __initdata = { +static const char *omap5_boards_compat[] __initconst = { "ti,omap5432", "ti,omap5430", "ti,omap5", @@ -221,7 +221,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM43XX -static const char *am43_boards_compat[] __initdata = { +static const char *am43_boards_compat[] __initconst = { "ti,am4372", "ti,am43", NULL, @@ -240,13 +240,13 @@ MACHINE_END #endif #ifdef CONFIG_SOC_DRA7XX -static const char *dra7xx_boards_compat[] __initdata = { - "ti,dra7xx", +static const char *dra74x_boards_compat[] __initconst = { + "ti,dra742", "ti,dra7", NULL, }; -DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") +DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") .reserve = omap_reserve, .smp = smp_ops(omap4_smp_ops), .map_io = omap5_map_io, @@ -255,7 +255,24 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_time = omap5_realtime_timer_init, - .dt_compat = dra7xx_boards_compat, + .dt_compat = dra74x_boards_compat, + .restart = omap44xx_restart, +MACHINE_END + +static const char *dra72x_boards_compat[] __initconst = { + "ti,dra722", + NULL, +}; + +DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = omap5_map_io, + .init_early = dra7xx_init_early, + .init_late = dra7xx_init_late, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap5_realtime_timer_init, + .dt_compat = dra72x_boards_compat, .restart = omap44xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index d6ed819ff15c..660bfc5a70d7 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,6 @@ #include <linux/mtd/nand.h> #include <linux/mmc/host.h> #include <linux/usb/phy.h> -#include <linux/usb/usb_phy_gen_xceiv.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 119efaf5808a..a2e035e0792a 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -121,11 +121,7 @@ static struct platform_device omap3stalker_tfp410_device = { static struct connector_atv_platform_data omap3stalker_tv_pdata = { .name = "tv", .source = "venc.0", -#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) - .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, -#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, -#endif .invert_polarity = false, }; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 3ff32543493c..59cf310bc1e9 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; - tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); + tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg); tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index 19f54d433490..0717dff1bc04 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk) { u32 pcc; - pcc = __raw_readl(prcm_clksrc_ctrl); + pcc = readl_relaxed(prcm_clksrc_ctrl); - __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); return 0; } @@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk) { u32 pcc; - pcc = __raw_readl(prcm_clksrc_ctrl); + pcc = readl_relaxed(prcm_clksrc_ctrl); - __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); + writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); } unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index f467d072cd02..58dd3a9b726c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void) { u32 div; - div = __raw_readl(prcm_clksrc_ctrl); + div = readl_relaxed(prcm_clksrc_ctrl); div &= OMAP_SYSCLKDIV_MASK; div >>= OMAP_SYSCLKDIV_SHIFT; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index f17f00697cc0..82c37b1becc4 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -18,7 +18,6 @@ #include "powerdomain.h" #include "clock.h" -#include "omap_hwmod.h" /* * Clockdomain flags @@ -98,6 +97,8 @@ struct clkdm_dep { /* Possible flags for struct clockdomain._flags */ #define _CLKDM_FLAG_HWSUP_ENABLED BIT(0) +struct omap_hwmod; + /** * struct clockdomain - OMAP clockdomain * @name: clockdomain name diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index ce25abbcffae..8be6ea50c092 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -18,9 +18,6 @@ #include <linux/err.h> #include <linux/io.h> -#include "soc.h" -#include "iomap.h" -#include "common.h" #include "prm2xxx.h" #include "cm.h" #include "cm2xxx.h" @@ -390,7 +387,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); - if (cpu_is_omap2430()) + if (mdm) omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL); } @@ -405,19 +402,11 @@ static struct cm_ll_data omap2xxx_cm_ll_data = { int __init omap2xxx_cm_init(void) { - if (!cpu_is_omap24xx()) - return 0; - return cm_register(&omap2xxx_cm_ll_data); } static void __exit omap2xxx_cm_exit(void) { - if (!cpu_is_omap24xx()) - return; - - /* Should never happen */ - WARN(cm_unregister(&omap2xxx_cm_ll_data), - "%s: cm_ll_data function pointer mismatch\n", __func__); + cm_unregister(&omap2xxx_cm_ll_data); } __exitcall(omap2xxx_cm_exit); diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index bfbd16fe9151..72928a3ce2aa 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -52,12 +52,12 @@ static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) { - return __raw_readl(cm_base + module + idx); + return readl_relaxed(cm_base + module + idx); } static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) { - __raw_writel(val, cm_base + module + idx); + writel_relaxed(val, cm_base + module + idx); } /* Read-modify-write a register in a CM module. Caller must lock */ diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 40a22e5649ae..b3f99e93def0 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -50,13 +50,13 @@ /* Read a register in a CM instance */ static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) { - return __raw_readl(cm_base + inst + idx); + return readl_relaxed(cm_base + inst + idx); } /* Write into a register in a CM */ static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) { - __raw_writel(val, cm_base + inst + idx); + writel_relaxed(val, cm_base + inst + idx); } /* Read-modify-write a register in CM */ diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index cfb8891b0c0e..15a778ce7707 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -17,11 +17,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H -#include "common.h" - #include "cm.h" #include "cm-regbits-33xx.h" -#include "iomap.h" /* CM base address */ #define AM33XX_CM_BASE 0x44e00000 diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index f6f028867bfe..129a4e7f6ef5 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -18,9 +18,6 @@ #include <linux/err.h> #include <linux/io.h> -#include "soc.h" -#include "iomap.h" -#include "common.h" #include "prm2xxx_3xxx.h" #include "cm.h" #include "cm3xxx.h" @@ -388,7 +385,8 @@ void omap3_cm_save_context(void) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); cm_context.iva2_cm_clksel2 = omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); - cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); + cm_context.cm_sysconfig = + omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG); cm_context.sgx_cm_clksel = omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); cm_context.dss_cm_clksel = @@ -418,7 +416,8 @@ void omap3_cm_save_context(void) omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); cm_context.pll_cm_clken2 = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); - cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); + cm_context.cm_polctrl = + omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL); cm_context.iva2_cm_fclken = omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); cm_context.iva2_cm_clken_pll = @@ -519,7 +518,8 @@ void omap3_cm_restore_context(void) CM_CLKSEL1); omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, CM_CLKSEL2); - __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); + omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD, + OMAP3430_CM_SYSCONFIG); omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, CM_CLKSEL); omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, @@ -547,7 +547,8 @@ void omap3_cm_restore_context(void) OMAP3430ES2_CM_CLKSEL5); omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, OMAP3430ES2_CM_CLKEN2); - __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); + omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD, + OMAP3430_CM_POLCTRL); omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, CM_FCLKEN); omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, @@ -669,19 +670,11 @@ static struct cm_ll_data omap3xxx_cm_ll_data = { int __init omap3xxx_cm_init(void) { - if (!cpu_is_omap34xx()) - return 0; - return cm_register(&omap3xxx_cm_ll_data); } static void __exit omap3xxx_cm_exit(void) { - if (!cpu_is_omap34xx()) - return; - - /* Should never happen */ - WARN(cm_unregister(&omap3xxx_cm_ll_data), - "%s: cm_ll_data function pointer mismatch\n", __func__); + cm_unregister(&omap3xxx_cm_ll_data); } __exitcall(omap3xxx_cm_exit); diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h index 8224c91b4d7a..7a16b5598127 100644 --- a/arch/arm/mach-omap2/cm3xxx.h +++ b/arch/arm/mach-omap2/cm3xxx.h @@ -29,9 +29,8 @@ * These registers appear once per CM module. */ -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) +#define OMAP3430_CM_SYSCONFIG 0x0010 +#define OMAP3430_CM_POLCTRL 0x009c #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c index 535d66e2822c..fe5cc7bae489 100644 --- a/arch/arm/mach-omap2/cm44xx.c +++ b/arch/arm/mach-omap2/cm44xx.c @@ -18,35 +18,32 @@ #include <linux/err.h> #include <linux/io.h> -#include "iomap.h" -#include "common.h" #include "cm.h" #include "cm1_44xx.h" #include "cm2_44xx.h" -#include "cm-regbits-44xx.h" /* CM1 hardware module low-level functions */ /* Read a register in CM1 */ u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg)); + return readl_relaxed(cm_base + inst + reg); } /* Write into a register in CM1 */ void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg)); + writel_relaxed(val, cm_base + inst + reg); } /* Read a register in CM2 */ u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg)); + return readl_relaxed(cm2_base + inst + reg); } /* Write into a register in CM2 */ void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg)); + writel_relaxed(val, cm2_base + inst + reg); } diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index 40b3b5a84458..8f6c4710877e 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -14,11 +14,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/errno.h> +#include <linux/bug.h> #include "cm2xxx.h" #include "cm3xxx.h" #include "cm44xx.h" -#include "common.h" /* * cm_ll_data: function pointers to SoC-specific implementations of diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index f5c4731b6f06..12aca56942c0 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -21,8 +21,6 @@ #include <linux/err.h> #include <linux/io.h> -#include "iomap.h" -#include "common.h" #include "clockdomain.h" #include "cm.h" #include "cm1_44xx.h" @@ -30,12 +28,18 @@ #include "cm44xx.h" #include "cminst44xx.h" #include "cm-regbits-34xx.h" -#include "cm-regbits-44xx.h" #include "prcm44xx.h" #include "prm44xx.h" #include "prcm_mpu44xx.h" #include "prcm-common.h" +#define OMAP4430_IDLEST_SHIFT 16 +#define OMAP4430_IDLEST_MASK (0x3 << 16) +#define OMAP4430_CLKTRCTRL_SHIFT 0 +#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) +#define OMAP4430_MODULEMODE_SHIFT 0 +#define OMAP4430_MODULEMODE_MASK (0x3 << 0) + /* * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: * @@ -116,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_cm_bases[part]); - return __raw_readl(_cm_bases[part] + inst + idx); + return readl_relaxed(_cm_bases[part] + inst + idx); } /* Write into a register in a CM instance */ @@ -125,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_cm_bases[part]); - __raw_writel(val, _cm_bases[part] + inst + idx); + writel_relaxed(val, _cm_bases[part] + inst + idx); } /* Read-modify-write a register in CM1. Caller must lock */ diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index d88aff7baff8..ff029737c8f0 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -91,6 +91,7 @@ extern void omap3_sync32k_timer_init(void); extern void omap3_secure_sync32k_timer_init(void); extern void omap3_gptimer_timer_init(void); extern void omap4_local_timer_init(void); +int omap_l2_cache_init(void); extern void omap5_realtime_timer_init(void); void omap2420_init_early(void); diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 44bb4d544dcf..751f3549bf6f 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -151,32 +151,32 @@ void __iomem *omap_ctrl_base_get(void) u8 omap_ctrl_readb(u16 offset) { - return __raw_readb(OMAP_CTRL_REGADDR(offset)); + return readb_relaxed(OMAP_CTRL_REGADDR(offset)); } u16 omap_ctrl_readw(u16 offset) { - return __raw_readw(OMAP_CTRL_REGADDR(offset)); + return readw_relaxed(OMAP_CTRL_REGADDR(offset)); } u32 omap_ctrl_readl(u16 offset) { - return __raw_readl(OMAP_CTRL_REGADDR(offset)); + return readl_relaxed(OMAP_CTRL_REGADDR(offset)); } void omap_ctrl_writeb(u8 val, u16 offset) { - __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); + writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); } void omap_ctrl_writew(u16 val, u16 offset) { - __raw_writew(val, OMAP_CTRL_REGADDR(offset)); + writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); } void omap_ctrl_writel(u32 val, u16 offset) { - __raw_writel(val, OMAP_CTRL_REGADDR(offset)); + writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); } /* @@ -188,12 +188,12 @@ void omap_ctrl_writel(u32 val, u16 offset) u32 omap4_ctrl_pad_readl(u16 offset) { - return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); + return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); } void omap4_ctrl_pad_writel(u32 val, u16 offset) { - __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); + writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); } #ifdef CONFIG_ARCH_OMAP3 @@ -222,7 +222,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode) * * XXX This should use some omap_ctrl_writel()-type function */ - __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); + writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); } #endif @@ -285,7 +285,7 @@ void omap3_clear_scratchpad_contents(void) if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & OMAP3430_GLOBAL_COLD_RST_MASK) { for ( ; offset <= max_offset; offset += 0x4) - __raw_writel(0x0, (v_addr + offset)); + writel_relaxed(0x0, (v_addr + offset)); omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 16d33d831287..bf852d7ae951 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -279,6 +279,8 @@ static enum omapdss_version __init omap_display_get_version(void) return OMAPDSS_VER_OMAP4; else if (soc_is_omap54xx()) return OMAPDSS_VER_OMAP5; + else if (soc_is_am43xx()) + return OMAPDSS_VER_AM43xx; else return OMAPDSS_VER_UNKNOWN; } @@ -555,65 +557,9 @@ int omap_dss_reset(struct omap_hwmod *oh) return r; } -/* list of 'compatible' nodes to convert to omapdss specific */ -static const char * const dss_compat_conv_list[] __initconst = { - "composite-connector", - "dvi-connector", - "hdmi-connector", - "panel-dpi", - "panel-dsi-cm", - "sony,acx565akm", - "svideo-connector", - "ti,tfp410", - "ti,tpd12s015", -}; - -/* prepend compatible string with "omapdss," */ -static __init void omapdss_omapify_node(struct device_node *node, - const char *compat) -{ - char *new_compat; - struct property *prop; - - new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat); - - prop = kzalloc(sizeof(*prop), GFP_KERNEL); - - if (!prop) { - pr_err("omapdss_omapify_node: kzalloc failed\n"); - return; - } - - prop->name = "compatible"; - prop->value = new_compat; - prop->length = strlen(new_compat) + 1; - - of_update_property(node, prop); -} - -/* - * As omapdss panel drivers are omapdss specific, but we want to define the - * DT-data in generic manner, we convert the compatible strings of the panel - * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both - * correct DT data and omapdss specific drivers. - * - * When we get generic panel drivers to the kernel, this will be removed. - */ void __init omapdss_early_init_of(void) { - int i; - - for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) { - const char *compat = dss_compat_conv_list[i]; - struct device_node *node = NULL; - - while ((node = of_find_compatible_node(node, NULL, compat))) { - if (!of_device_is_available(node)) - continue; - omapdss_omapify_node(node, compat); - } - } } struct device_node * __init omapdss_find_dss_of_node(void) @@ -632,6 +578,10 @@ struct device_node * __init omapdss_find_dss_of_node(void) if (node) return node; + node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss"); + if (node) + return node; + return NULL; } diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 5689c88d986d..a6d2cf1f8d02 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -91,7 +91,7 @@ static inline void dma_write(u32 val, int reg, int lch) addr += reg_map[reg].offset; addr += reg_map[reg].stride * lch; - __raw_writel(val, addr); + writel_relaxed(val, addr); } static inline u32 dma_read(int reg, int lch) @@ -101,7 +101,7 @@ static inline u32 dma_read(int reg, int lch) addr += reg_map[reg].offset; addr += reg_map[reg].stride * lch; - return __raw_readl(addr); + return readl_relaxed(addr); } static void omap2_clear_dma(int lch) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 4349e82debfe..17cd39360afe 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -46,7 +46,7 @@ static struct platform_device gpmc_nand_device = { static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* platforms which support all ECC schemes */ - if (soc_is_am33xx() || cpu_is_omap44xx() || + if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) return 1; diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 9fe8c949305c..852b19a367f0 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev); static void gpmc_write_reg(int idx, u32 val) { - __raw_writel(val, gpmc_base + idx); + writel_relaxed(val, gpmc_base + idx); } static u32 gpmc_read_reg(int idx) { - return __raw_readl(gpmc_base + idx); + return readl_relaxed(gpmc_base + idx); } void gpmc_cs_write_reg(int cs, int idx, u32 val) @@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val) void __iomem *reg_addr; reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; - __raw_writel(val, reg_addr); + writel_relaxed(val, reg_addr); } static u32 gpmc_cs_read_reg(int cs, int idx) @@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx) void __iomem *reg_addr; reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; - return __raw_readl(reg_addr); + return readl_relaxed(reg_addr); } /* TODO: Add support for gpmc_fck to clock framework and use it */ diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index cbc8e3c480e0..f78b4a161959 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -76,6 +76,7 @@ int omap_hdq1w_reset(struct omap_hwmod *oh) return 0; } +#ifndef CONFIG_OF static int __init omap_init_hdq(void) { int id = -1; @@ -95,3 +96,4 @@ static int __init omap_init_hdq(void) return 0; } omap_arch_initcall(omap_init_hdq); +#endif diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 157412e4273a..43969da5d50b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -94,7 +94,7 @@ EXPORT_SYMBOL(omap_type); #define OMAP_TAP_DIE_ID_44XX_2 0x020c #define OMAP_TAP_DIE_ID_44XX_3 0x0210 -#define read_tap_reg(reg) __raw_readl(tap_base + (reg)) +#define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) struct omap_id { u16 hawkeye; /* Silicon type (Hawkeye id) */ @@ -628,6 +628,41 @@ void __init omap5xxx_check_revision(void) pr_info("%s %s\n", soc_name, soc_rev); } +void __init dra7xxx_check_revision(void) +{ + u32 idcode; + u16 hawkeye; + u8 rev; + + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; + rev = (idcode >> 28) & 0xff; + switch (hawkeye) { + case 0xb990: + switch (rev) { + case 0: + omap_revision = DRA752_REV_ES1_0; + break; + case 1: + default: + omap_revision = DRA752_REV_ES1_1; + } + break; + + default: + /* Unknown default to latest silicon rev as default*/ + pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", + __func__, idcode, hawkeye, rev); + omap_revision = DRA752_REV_ES1_1; + } + + sprintf(soc_name, "DRA%03x", omap_rev() >> 16); + sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, + (omap_rev() >> 8) & 0xf); + + pr_info("%s %s\n", soc_name, soc_rev); +} + /* * Set up things for map_io and processor detection later on. Gets called * pretty much first thing from board init. For multi-omap, this gets @@ -669,6 +704,8 @@ static const char * __init omap_get_family(void) return kasprintf(GFP_KERNEL, "OMAP5"); else if (soc_is_am43xx()) return kasprintf(GFP_KERNEL, "AM43xx"); + else if (soc_is_dra7xx()) + return kasprintf(GFP_KERNEL, "DRA7"); else return kasprintf(GFP_KERNEL, "Unknown"); } diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index f14f9ac2dca1..8f559450c876 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -609,6 +609,7 @@ void __init am43xx_init_early(void) am43xx_clockdomains_init(); am43xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; } @@ -640,6 +641,7 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_l2_cache_init(); omap_clk_soc_init = omap4xxx_dt_clk_init; } @@ -693,6 +695,7 @@ void __init dra7xx_init_early(void) omap_prm_base_init(); omap_cm_base_init(); omap44xx_prm_init(); + dra7xxx_check_revision(); dra7xx_powerdomains_init(); dra7xx_clockdomains_init(); dra7xx_hwmod_init(); diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 6037a9a01ed5..35b8590c322e 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -83,12 +83,12 @@ struct omap3_intc_regs { static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) { - __raw_writel(val, bank->base_reg + reg); + writel_relaxed(val, bank->base_reg + reg); } static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) { - return __raw_readl(bank->base_reg + reg); + return readl_relaxed(bank->base_reg + reg); } /* XXX: FIQ and additional INTC support (only MPU at the moment) */ diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 48094b58c88f..fd88edeb027f 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name) u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg) { if (partition->flags & OMAP_MUX_REG_8BIT) - return __raw_readb(partition->base + reg); + return readb_relaxed(partition->base + reg); else - return __raw_readw(partition->base + reg); + return readw_relaxed(partition->base + reg); } void omap_mux_write(struct omap_mux_partition *partition, u16 val, u16 reg) { if (partition->flags & OMAP_MUX_REG_8BIT) - __raw_writeb(val, partition->base + reg); + writeb_relaxed(val, partition->base + reg); else - __raw_writew(val, partition->base + reg); + writew_relaxed(val, partition->base + reg); } void omap_mux_write_array(struct omap_mux_partition *partition, diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 40c5d5f1451c..4993d4bfe9b2 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -31,10 +31,6 @@ * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) -.arm -THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. -THUMB( bx r9 ) @ If this is a Thumb-2 kernel, -THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 @@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 cmp r0, r4 bne wait b secondary_startup -END(omap5_secondary_startup) +ENDPROC(omap5_secondary_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 458f72f9dc8f..971791fe9a3f 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu) if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) pr_err("Secure clear status failed\n"); } else { - __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0); + writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0); } @@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu) boot_cpu = omap_read_auxcoreboot0(); else boot_cpu = - __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5; + readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5; if (boot_cpu == smp_processor_id()) { /* diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 667915d236f3..4001325f90fb 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - __raw_writel(addr, pm_info->wkup_sar_addr); + writel_relaxed(addr, pm_info->wkup_sar_addr); } /* @@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) break; } - __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); + writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); } /* Helper functions for MPUSS OSWR */ @@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - __raw_writel(save_state, pm_info->l2x0_sar_addr); + writel_relaxed(save_state, pm_info->l2x0_sar_addr); } /* @@ -187,19 +187,15 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) * in every restore MPUSS OFF path. */ #ifdef CONFIG_CACHE_L2X0 -static void save_l2x0_context(void) +static void __init save_l2x0_context(void) { - u32 val; - void __iomem *l2x0_base = omap4_get_l2cache_base(); - if (l2x0_base) { - val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); - __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); - val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); - __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); - } + writel_relaxed(l2x0_saved_regs.aux_ctrl, + sar_base + L2X0_AUXCTRL_OFFSET); + writel_relaxed(l2x0_saved_regs.prefetch_ctrl, + sar_base + L2X0_PREFETCH_CTRL_OFFSET); } #else -static void save_l2x0_context(void) +static void __init save_l2x0_context(void) {} #endif @@ -386,9 +382,9 @@ int __init omap4_mpuss_init(void) /* Save device type on scratchpad for low level code to use */ if (omap_type() != OMAP2_DEVICE_TYPE_GP) - __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); + writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET); else - __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); + writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET); save_l2x0_context(); diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 17550aa39d0f..256e84ef0f67 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -99,7 +99,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) if (omap_secure_apis_support()) omap_modify_auxcoreboot0(0x200, 0xfffffdff); else - __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); + writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0); if (!cpu1_clkdm && !cpu1_pwrdm) { cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); @@ -227,8 +227,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) if (omap_secure_apis_support()) omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else - __raw_writel(virt_to_phys(omap5_secondary_startup), - base + OMAP_AUX_CORE_BOOT_1); + writel_relaxed(virt_to_phys(omap5_secondary_startup), + base + OMAP_AUX_CORE_BOOT_1); } diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 693fe486e917..37843a7d3639 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -60,19 +60,19 @@ static unsigned int omap_secure_apis; */ static inline u32 wakeupgen_readl(u8 idx, u32 cpu) { - return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 + + return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 + (cpu * CPU_ENA_OFFSET) + (idx * 4)); } static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) { - __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + + writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + (cpu * CPU_ENA_OFFSET) + (idx * 4)); } static inline void sar_writel(u32 val, u32 offset, u8 idx) { - __raw_writel(val, sar_base + offset + (idx * 4)); + writel_relaxed(val, sar_base + offset + (idx * 4)); } static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index) @@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void) } /* Save AuxBoot* registers */ - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); - __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); + writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); /* Save SyncReq generation logic */ - val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); - __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN); - __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); + writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); + writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); /* Set the Backup Bit Mask status */ - val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); + val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); val |= SAR_BACKUP_STATUS_WAKEUPGEN; - __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); + writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); } @@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void) } /* Save AuxBoot* registers */ - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); + val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); /* Set the Backup Bit Mask status */ - val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); + val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); val |= SAR_BACKUP_STATUS_WAKEUPGEN; - __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); + writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); } @@ -306,9 +306,9 @@ static void irq_sar_clear(void) if (soc_is_omap54xx()) offset = OMAP5_SAR_BACKUP_STATUS_OFFSET; - val = __raw_readl(sar_base + offset); + val = readl_relaxed(sar_base + offset); val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; - __raw_writel(val, sar_base + offset); + writel_relaxed(val, sar_base + offset); } /* diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 95e171a055f3..326cd982a3cb 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -125,25 +125,25 @@ void __init gic_init_irq(void) void gic_dist_disable(void) { if (gic_dist_base_addr) - __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL); + writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); } void gic_dist_enable(void) { if (gic_dist_base_addr) - __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL); + writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); } bool gic_dist_disabled(void) { - return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); + return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); } void gic_timer_retrigger(void) { - u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT); - u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET); - u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); + u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); + u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); + u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { /* @@ -151,11 +151,11 @@ void gic_timer_retrigger(void) * disabled. Ack the pending interrupt, and retrigger it. */ pr_warn("%s: lost localtimer interrupt\n", __func__); - __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); + writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { - __raw_writel(1, twd_base + TWD_TIMER_COUNTER); + writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; - __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL); + writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); } } } @@ -167,75 +167,57 @@ void __iomem *omap4_get_l2cache_base(void) return l2cache_base; } -static void omap4_l2x0_disable(void) +static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) { - outer_flush_all(); - /* Disable PL310 L2 Cache controller */ - omap_smc1(0x102, 0x0); -} + unsigned smc_op; -static void omap4_l2x0_set_debug(unsigned long val) -{ - /* Program PL310 L2 Cache controller debug register */ - omap_smc1(0x100, val); + switch (reg) { + case L2X0_CTRL: + smc_op = OMAP4_MON_L2X0_CTRL_INDEX; + break; + + case L2X0_AUX_CTRL: + smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX; + break; + + case L2X0_DEBUG_CTRL: + smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX; + break; + + case L310_PREFETCH_CTRL: + smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; + break; + + default: + WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); + return; + } + + omap_smc1(smc_op, val); } -static int __init omap_l2_cache_init(void) +int __init omap_l2_cache_init(void) { - u32 aux_ctrl = 0; - - /* - * To avoid code running on other OMAPs in - * multi-omap builds - */ - if (!cpu_is_omap44xx()) - return -ENODEV; + u32 aux_ctrl; /* Static mapping, never released */ l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); if (WARN_ON(!l2cache_base)) return -ENOMEM; - /* - * 16-way associativity, parity disabled - * Way size - 32KB (es1.0) - * Way size - 64KB (es2.0 +) - */ - aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | - (0x1 << 25) | - (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | - (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); - - if (omap_rev() == OMAP4430_REV_ES1_0) { - aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; - } else { - aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | - (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | - (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | - (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); - } - if (omap_rev() != OMAP4430_REV_ES1_0) - omap_smc1(0x109, aux_ctrl); - - /* Enable PL310 L2 Cache controller */ - omap_smc1(0x102, 0x1); + /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ + aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE | + L310_AUX_CTRL_DATA_PREFETCH | + L310_AUX_CTRL_INSTR_PREFETCH; + outer_cache.write_sec = omap4_l2c310_write_sec; if (of_have_populated_dt()) - l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); + l2x0_of_init(aux_ctrl, 0xcf9fffff); else - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); - - /* - * Override default outer_cache.disable with a OMAP4 - * specific one - */ - outer_cache.disable = omap4_l2x0_disable; - outer_cache.set_debug = omap4_l2x0_set_debug; + l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff); return 0; } -omap_early_initcall(omap_l2_cache_init); #endif void __iomem *omap4_get_sar_ram_base(void) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 66c60fe1104c..f7bb435bb543 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -72,7 +72,7 @@ * | (../mach-omap2/omap_hwmod*) | * +-------------------------------+ * | OMAP clock/PRCM/register fns | - * | (__raw_{read,write}l, clk*) | + * | ({read,write}l_relaxed, clk*) | * +-------------------------------+ * * Device drivers should not contain any OMAP-specific code or data in @@ -3230,17 +3230,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) { if (oh->flags & HWMOD_16BIT_REG) - return __raw_readw(oh->_mpu_rt_va + reg_offs); + return readw_relaxed(oh->_mpu_rt_va + reg_offs); else - return __raw_readl(oh->_mpu_rt_va + reg_offs); + return readl_relaxed(oh->_mpu_rt_va + reg_offs); } void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) { if (oh->flags & HWMOD_16BIT_REG) - __raw_writew(v, oh->_mpu_rt_va + reg_offs); + writew_relaxed(v, oh->_mpu_rt_va + reg_offs); else - __raw_writel(v, oh->_mpu_rt_va + reg_offs); + writel_relaxed(v, oh->_mpu_rt_va + reg_offs); } /** diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 0f178623e7da..a579b89ce9b7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -24,6 +24,7 @@ #include "prm33xx.h" #include "omap_hwmod_33xx_43xx_common_data.h" #include "prcm43xx.h" +#include "common.h" #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 71ac7d5f3385..1cd0cfdc03e0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -3689,12 +3689,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | - SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 1219280bb976..41e54f759934 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3635,15 +3635,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_dmic_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> dmic (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* dsp -> iva */ @@ -4209,15 +4201,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp1_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> mcbsp1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_abe -> mcbsp2 */ @@ -4225,15 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp2_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> mcbsp2 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_abe -> mcbsp3 */ @@ -4241,15 +4217,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp3_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> mcbsp3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_per -> mcbsp4 */ @@ -4265,15 +4233,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcpdm_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> mcpdm (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_per -> mcspi1 */ @@ -4575,15 +4535,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer5_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer5 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_abe -> timer6 */ @@ -4591,15 +4543,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer6_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer6 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_abe -> timer7 */ @@ -4607,15 +4551,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer7_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer7 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_abe -> timer8 */ @@ -4623,15 +4559,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer8_hwmod, .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU, -}; - -/* l4_abe -> timer8 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_SDMA, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4_per -> timer9 */ @@ -4831,7 +4759,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_instr__debugss, &omap44xx_l4_cfg__dma_system, &omap44xx_l4_abe__dmic, - &omap44xx_l4_abe__dmic_dma, &omap44xx_dsp__iva, /* &omap44xx_dsp__sl2if, */ &omap44xx_l4_cfg__dsp, @@ -4874,14 +4801,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_abe__mcasp, &omap44xx_l4_abe__mcasp_dma, &omap44xx_l4_abe__mcbsp1, - &omap44xx_l4_abe__mcbsp1_dma, &omap44xx_l4_abe__mcbsp2, - &omap44xx_l4_abe__mcbsp2_dma, &omap44xx_l4_abe__mcbsp3, - &omap44xx_l4_abe__mcbsp3_dma, &omap44xx_l4_per__mcbsp4, &omap44xx_l4_abe__mcpdm, - &omap44xx_l4_abe__mcpdm_dma, &omap44xx_l4_per__mcspi1, &omap44xx_l4_per__mcspi2, &omap44xx_l4_per__mcspi3, @@ -4913,13 +4836,9 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__timer3, &omap44xx_l4_per__timer4, &omap44xx_l4_abe__timer5, - &omap44xx_l4_abe__timer5_dma, &omap44xx_l4_abe__timer6, - &omap44xx_l4_abe__timer6_dma, &omap44xx_l4_abe__timer7, - &omap44xx_l4_abe__timer7_dma, &omap44xx_l4_abe__timer8, - &omap44xx_l4_abe__timer8_dma, &omap44xx_l4_per__timer9, &omap44xx_l4_per__timer10, &omap44xx_l4_per__timer11, diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index e829664e6a6c..290213f2cbe3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -334,6 +334,235 @@ static struct omap_hwmod omap54xx_dmic_hwmod = { }; /* + * 'dss' class + * display sub-system + */ +static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = { + .rev_offs = 0x0000, + .syss_offs = 0x0014, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class omap54xx_dss_hwmod_class = { + .name = "dss", + .sysc = &omap54xx_dss_sysc, + .reset = omap_dss_reset, +}; + +/* dss */ +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "32khz_clk", .clk = "dss_32khz_clk" }, + { .role = "sys_clk", .clk = "dss_sys_clk" }, + { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, +}; + +static struct omap_hwmod omap54xx_dss_hwmod = { + .name = "dss_core", + .class = &omap54xx_dss_hwmod_class, + .clkdm_name = "dss_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap54xx_dispc_sysc, +}; + +/* dss_dispc */ +static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + +/* dss_dispc dev_attr */ +static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = { + .has_framedonetv_irq = 1, + .manager_count = 4, +}; + +static struct omap_hwmod omap54xx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap54xx_dispc_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_dispc_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks), + .dev_attr = &dss_dispc_dev_attr, +}; + +/* + * 'dsi1' class + * display serial interface controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = { + .name = "dsi1", + .sysc = &omap54xx_dsi1_sysc, +}; + +/* dss_dsi1_a */ +static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + +static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = { + .name = "dss_dsi1", + .class = &omap54xx_dsi1_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_dsi1_a_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks), +}; + +/* dss_dsi1_c */ +static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + +static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = { + .name = "dss_dsi2", + .class = &omap54xx_dsi1_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_dsi1_c_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks), +}; + +/* + * 'hdmi' class + * hdmi controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = { + .name = "hdmi", + .sysc = &omap54xx_hdmi_sysc, +}; + +static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, +}; + +static struct omap_hwmod omap54xx_dss_hdmi_hwmod = { + .name = "dss_hdmi", + .class = &omap54xx_hdmi_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_48mhz_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_hdmi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap54xx_rfbi_sysc, +}; + +/* dss_rfbi */ +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "l3_iclk_div" }, +}; + +static struct omap_hwmod omap54xx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap54xx_rfbi_hwmod_class, + .clkdm_name = "dss_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), +}; + +/* * 'emif' class * external memory interface no1 (wrapper) */ @@ -1974,6 +2203,54 @@ static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = { .user = OCP_USER_MPU, }; +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_dispc_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> dss_dsi1_a */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_dsi1_a_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> dss_dsi1_c */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_dsi1_c_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_hdmi_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_dss_rfbi_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* mpu -> emif1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { .master = &omap54xx_mpu_hwmod, @@ -2427,6 +2704,12 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_cfg__dma_system, &omap54xx_l4_abe__dmic, &omap54xx_l4_cfg__mmu_dsp, + &omap54xx_l3_main_2__dss, + &omap54xx_l3_main_2__dss_dispc, + &omap54xx_l3_main_2__dss_dsi1_a, + &omap54xx_l3_main_2__dss_dsi1_c, + &omap54xx_l3_main_2__dss_hdmi, + &omap54xx_l3_main_2__dss_rfbi, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, &omap54xx_l4_wkup__gpio1, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 810c205d668b..20b4398cec05 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2318,21 +2318,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = { - { - .pa_start = 0x4a080000, - .pa_end = 0x4a08001f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> ocp2scp1 */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { .master = &dra7xx_l4_cfg_hwmod, .slave = &dra7xx_ocp2scp1_hwmod, .clk = "l4_root_clk_div", - .addr = dra7xx_ocp2scp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index eb8a25de67ed..50640b38f0bf 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void) } /* Power down the phy */ - __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); + writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF); iounmap(ctrl_base); @@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on) return; } - usbphycfg = __raw_readl(scm_base + USBCTRL0); + usbphycfg = readl_relaxed(scm_base + USBCTRL0); if (on) { if (cpu_is_ti816x()) { @@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on) usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; } - __raw_writel(usbphycfg, scm_base + USBCTRL0); + writel_relaxed(usbphycfg, scm_base + USBCTRL0); iounmap(scm_base); } diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 615e5b1fb025..6bf626700557 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -46,15 +46,8 @@ static bool is_offset_valid; static u8 smps_offset; -/* - * Flag to ensure Smartreflex bit in TWL - * being cleared in board file is not overwritten. - */ -static bool __initdata twl_sr_enable_autoinit; -#define TWL4030_DCDC_GLOBAL_CFG 0x06 #define REG_SMPS_OFFSET 0xE0 -#define SMARTREFLEX_ENABLE BIT(3) static unsigned long twl4030_vsel_to_uv(const u8 vsel) { @@ -251,18 +244,6 @@ int __init omap3_twl_init(void) if (!cpu_is_omap34xx()) return -ENODEV; - /* - * The smartreflex bit on twl4030 specifies if the setting of voltage - * is done over the I2C_SR path. Since this setting is independent of - * the actual usage of smartreflex AVS module, we enable TWL SR bit - * by default irrespective of whether smartreflex AVS module is enabled - * on the OMAP side or not. This is because without this bit enabled, - * the voltage scaling through vp forceupdate/bypass mechanism of - * voltage scaling will not function on TWL over I2C_SR. - */ - if (!twl_sr_enable_autoinit) - omap3_twl_set_sr_bit(true); - voltdm = voltdm_lookup("mpu_iva"); omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); @@ -271,44 +252,3 @@ int __init omap3_twl_init(void) return 0; } - -/** - * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL - * @enable: enable SR mode in twl or not - * - * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure - * voltage scaling through OMAP SR works. Else, the smartreflex bit - * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but - * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct - * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, - * in those scenarios this bit is to be cleared (enable = false). - * - * Returns 0 on success, error is returned if I2C read/write fails. - */ -int __init omap3_twl_set_sr_bit(bool enable) -{ - u8 temp; - int ret; - if (twl_sr_enable_autoinit) - pr_warning("%s: unexpected multiple calls\n", __func__); - - ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp, - TWL4030_DCDC_GLOBAL_CFG); - if (ret) - goto err; - - if (enable) - temp |= SMARTREFLEX_ENABLE; - else - temp &= ~SMARTREFLEX_ENABLE; - - ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp, - TWL4030_DCDC_GLOBAL_CFG); - if (!ret) { - twl_sr_enable_autoinit = true; - return 0; - } -err: - pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); - return ret; -} diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index c3b73351cb7a..90c88d498485 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -226,6 +226,14 @@ static void __init am3517_evm_legacy_init(void) am35xx_emac_reset(); } +static struct platform_device omap3_rom_rng_device = { + .name = "omap3-rom-rng", + .id = -1, + .dev = { + .platform_data = rx51_secure_rng_call, + }, +}; + static void __init nokia_n900_legacy_init(void) { hsmmc2_internal_input_clk(); @@ -239,6 +247,10 @@ static void __init nokia_n900_legacy_init(void) pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); pr_warning("Thumb binaries may crash randomly without this workaround\n"); } + + pr_info("RX-51: Registring OMAP3 HWRNG device\n"); + platform_device_register(&omap3_rom_rng_device); + } } #endif /* CONFIG_ARCH_OMAP3 */ @@ -254,6 +266,11 @@ static void __init omap4_panda_legacy_init(void) { legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); } + +static void __init var_som_om44_legacy_init(void) +{ + legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41); +} #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) @@ -364,6 +381,8 @@ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_ARCH_OMAP4 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, { "ti,omap4-panda", omap4_panda_legacy_init, }, + { "variscite,var-dvk-om44", var_som_om44_legacy_init, }, + { "variscite,var-stk-om44", var_som_om44_legacy_init, }, #endif #ifdef CONFIG_SOC_AM33XX { "ti,am335x-evmsk", am335x_evmsk_legacy_init, }, diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index e1b41416fbf1..828aee9ea6a8 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -32,11 +32,13 @@ #include "pm.h" #include "twl-common.h" +#ifdef CONFIG_SUSPEND /* * omap_pm_suspend: points to a function that does the SoC-specific * suspend work */ -int (*omap_pm_suspend)(void); +static int (*omap_pm_suspend)(void); +#endif #ifdef CONFIG_PM /** @@ -243,6 +245,15 @@ static const struct platform_suspend_ops omap_pm_ops = { .valid = suspend_valid_only_mem, }; +/** + * omap_common_suspend_init - Set common suspend routines for OMAP SoCs + * @pm_suspend: function pointer to SoC specific suspend function + */ +void omap_common_suspend_init(void *pm_suspend) +{ + omap_pm_suspend = pm_suspend; + suspend_set_ops(&omap_pm_ops); +} #endif /* CONFIG_SUSPEND */ static void __init omap3_init_voltages(void) @@ -287,32 +298,24 @@ omap_postcore_initcall(omap2_common_pm_init); int __init omap2_common_pm_late_init(void) { - /* - * In the case of DT, the PMIC and SR initialization will be done using - * a completely different mechanism. - * Disable this part if a DT blob is available. - */ - if (!of_have_populated_dt()) { - - /* Init the voltage layer */ - omap_pmic_late_init(); - omap_voltage_late_init(); + if (of_have_populated_dt()) { + omap3_twl_init(); + omap4_twl_init(); + } - /* Initialize the voltages */ - omap3_init_voltages(); - omap4_init_voltages(); + /* Init the voltage layer */ + omap_pmic_late_init(); + omap_voltage_late_init(); - /* Smartreflex device init */ - omap_devinit_smartreflex(); + /* Initialize the voltages */ + omap3_init_voltages(); + omap4_init_voltages(); - } + /* Smartreflex device init */ + omap_devinit_smartreflex(); /* cpufreq dummy device instantiation */ omap_init_cpufreq(); -#ifdef CONFIG_SUSPEND - suspend_set_ops(&omap_pm_ops); -#endif - return 0; } diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index d4d0fce325c7..e150102d6c06 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -34,7 +34,6 @@ extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); -extern int (*omap_pm_suspend)(void); #if defined(CONFIG_PM_OPP) extern int omap3_opp_init(void); @@ -147,4 +146,11 @@ static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = * static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { } #endif +#ifdef CONFIG_SUSPEND +void omap_common_suspend_init(void *pm_suspend); +#else +static inline void omap_common_suspend_init(void *pm_suspend) +{ +} +#endif /* CONFIG_SUSPEND */ #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 8c0759496c8d..a5ea988ff340 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -229,9 +229,7 @@ static void __init prcm_setup_regs(void) clkdm_for_each(omap_pm_clkdms_setup, NULL); clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); -#ifdef CONFIG_SUSPEND - omap_pm_suspend = omap2_enter_full_retention; -#endif + omap_common_suspend_init(omap2_enter_full_retention); /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 87099bb6de69..507d8eeaab95 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -50,6 +50,7 @@ #include "sdrc.h" #include "sram.h" #include "control.h" +#include "vc.h" /* pm34xx errata defined in pm.h */ u16 pm34xx_errata; @@ -288,6 +289,9 @@ void omap_sram_idle(void) } } + /* Configure PMIC signaling for I2C4 or sys_off_mode */ + omap3_vc_set_pmic_signaling(core_next_state); + omap3_intc_prepare_idle(); /* @@ -391,7 +395,8 @@ restore: return ret; } - +#else +#define omap3_pm_suspend NULL #endif /* CONFIG_SUSPEND */ @@ -705,9 +710,7 @@ int __init omap3_pm_init(void) per_clkdm = clkdm_lookup("per_clkdm"); wkup_clkdm = clkdm_lookup("wkup_clkdm"); -#ifdef CONFIG_SUSPEND - omap_pm_suspend = omap3_pm_suspend; -#endif + omap_common_suspend_init(omap3_pm_suspend); arm_pm_idle = omap3_pm_idle; omap3_idle_init(); diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index eefb30cfcabd..0dda6cf8b855 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -96,6 +96,8 @@ static int omap4_pm_suspend(void) return 0; } +#else +#define omap4_pm_suspend NULL #endif /* CONFIG_SUSPEND */ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) @@ -251,9 +253,7 @@ int __init omap4_pm_init(void) (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); -#ifdef CONFIG_SUSPEND - omap_pm_suspend = omap4_pm_suspend; -#endif + omap_common_suspend_init(omap4_pm_suspend); /* Overwrite the default cpu_do_idle() */ arm_pm_idle = omap_default_idle; diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c index c0aeabfcf009..c40e5f009826 100644 --- a/arch/arm/mach-omap2/powerdomain-common.c +++ b/arch/arm/mach-omap2/powerdomain-common.c @@ -17,7 +17,6 @@ #include "pm.h" #include "cm.h" #include "cm-regbits-34xx.h" -#include "cm-regbits-44xx.h" #include "prm-regbits-34xx.h" #include "prm-regbits-44xx.h" diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 93a2a6e4260f..faebd5f076af 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -32,6 +32,7 @@ #include "powerdomain.h" #include "clockdomain.h" +#include "voltage.h" #include "soc.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index da5a59ae77b6..f4727117f6cc 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -21,8 +21,6 @@ #include <linux/list.h> #include <linux/spinlock.h> -#include "voltage.h" - /* Powerdomain basic power states */ #define PWRDM_POWER_OFF 0x0 #define PWRDM_POWER_RET 0x1 @@ -75,6 +73,7 @@ struct clockdomain; struct powerdomain; +struct voltagedomain; /** * struct powerdomain - OMAP powerdomain diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 0e841fd9498a..a8e4b582c527 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -428,6 +428,28 @@ #define MAX_IOPAD_LATCH_TIME 100 # ifndef __ASSEMBLER__ +#include <linux/delay.h> + +/** + * omap_test_timeout - busy-loop, testing a condition + * @cond: condition to test until it evaluates to true + * @timeout: maximum number of microseconds in the timeout + * @index: loop index (integer) + * + * Loop waiting for @cond to become true or until at least @timeout + * microseconds have passed. To use, define some integer @index in the + * calling code. After running, if @index == @timeout, then the loop has + * timed out. + */ +#define omap_test_timeout(cond, timeout, index) \ +({ \ + for (index = 0; index < timeout; index++) { \ + if (cond) \ + break; \ + udelay(1); \ + } \ +}) + /** * struct omap_prcm_irq - describes a PRCM interrupt bit * @name: a short name describing the interrupt type, e.g. "wkup" or "io" @@ -458,6 +480,7 @@ struct omap_prcm_irq { * @ocp_barrier: fn ptr to force buffered PRM writes to complete * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs * @restore_irqen: fn ptr to save and clear IRQENABLE regs + * @reconfigure_io_chain: fn ptr to reconfigure IO chain * @saved_mask: IRQENABLE regs are saved here during suspend * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init @@ -479,6 +502,7 @@ struct omap_prcm_irq_setup { void (*ocp_barrier)(void); void (*save_and_clear_irqen)(u32 *saved_mask); void (*restore_irqen)(u32 *saved_mask); + void (*reconfigure_io_chain)(void); u32 *saved_mask; u32 *priority_mask; int base_irq; diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c index c30e44a7fab0..cdbee6326d29 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.c +++ b/arch/arm/mach-omap2/prcm_mpu44xx.c @@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base; u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); + return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); } void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); + writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); } u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index 059bd4f49035..ac9cb4550239 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -26,7 +26,6 @@ #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #include "prcm_mpu_44xx_54xx.h" -#include "common.h" #define OMAP4430_PRCM_MPU_BASE 0x48243000 diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index cebad565ed37..106132db532b 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -123,8 +123,15 @@ #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) -#define OMAP3430_SEL_OFF_MASK (1 << 3) -#define OMAP3430_AUTO_OFF_MASK (1 << 2) +#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE (1 << 4) +#define OMAP3430_PRM_VOLTCTRL_SEL_OFF (1 << 3) +#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF (1 << 2) +#define OMAP3430_PRM_VOLTCTRL_AUTO_RET (1 << 1) +#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP (1 << 0) #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) +#define OMAP3430_PRM_POLCTRL_OFFMODE_POL (1 << 3) +#define OMAP3430_PRM_POLCTRL_CLKOUT_POL (1 << 2) +#define OMAP3430_PRM_POLCTRL_CLKREQ_POL (1 << 1) +#define OMAP3430_PRM_POLCTRL_EXTVOL_POL (1 << 0) #endif diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 623db40fdbbd..48480d557b61 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -17,10 +17,18 @@ # ifndef __ASSEMBLER__ extern void __iomem *prm_base; +extern u16 prm_features; extern void omap2_set_globals_prm(void __iomem *prm); int of_prcm_init(void); # endif +/* + * prm_features flag values + * + * PRM_HAS_IO_WAKEUP: has IO wakeup capability + * PRM_HAS_VOLTAGE: has voltage domains + */ +#define PRM_HAS_IO_WAKEUP (1 << 0) /* * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP @@ -118,6 +126,7 @@ struct prm_reset_src_map { * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn + * @late_init: ptr to the late init function * * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are * deprecated. @@ -126,6 +135,7 @@ struct prm_ll_data { u32 (*read_reset_sources)(void); bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); + int (*late_init)(void); }; extern int prm_register(struct prm_ll_data *pld); diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index 418de9c3b319..a3a3cca2bcc4 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -18,9 +18,6 @@ #include <linux/io.h> #include <linux/irq.h> -#include "soc.h" -#include "common.h" -#include "vp.h" #include "powerdomain.h" #include "clockdomain.h" #include "prm2xxx.h" @@ -201,19 +198,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = { int __init omap2xxx_prm_init(void) { - if (!cpu_is_omap24xx()) - return 0; - return prm_register(&omap2xxx_prm_ll_data); } static void __exit omap2xxx_prm_exit(void) { - if (!cpu_is_omap24xx()) - return; - - /* Should never happen */ - WARN(prm_unregister(&omap2xxx_prm_ll_data), - "%s: prm_ll_data function pointer mismatch\n", __func__); + prm_unregister(&omap2xxx_prm_ll_data); } __exitcall(omap2xxx_prm_exit); diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h index 3194dd87e0e4..d2cb6365716f 100644 --- a/arch/arm/mach-omap2/prm2xxx.h +++ b/arch/arm/mach-omap2/prm2xxx.h @@ -27,7 +27,7 @@ /* * OMAP2-specific global PRM registers - * Use __raw_{read,write}l() with these registers. + * Use {read,write}l_relaxed() with these registers. * * With a few exceptions, these are the register names beginning with * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 947f6adfed0c..c13b4e293ffa 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -16,7 +16,6 @@ #include <linux/err.h> #include <linux/io.h> -#include "common.h" #include "powerdomain.h" #include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index 9624b40836d4..1a3a96392b97 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -55,12 +55,12 @@ /* Power/reset management domain register get/set */ static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { - return __raw_readl(prm_base + module + idx); + return readl_relaxed(prm_base + module + idx); } static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) { - __raw_writel(val, prm_base + module + idx); + writel_relaxed(val, prm_base + module + idx); } /* Read-modify-write a register in a PRM module. Caller must lock */ diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index 720440737744..62709cd2f9c5 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -19,7 +19,6 @@ #include <linux/err.h> #include <linux/io.h> -#include "common.h" #include "powerdomain.h" #include "prm33xx.h" #include "prm-regbits-33xx.h" @@ -27,13 +26,13 @@ /* Read a register in a PRM instance */ u32 am33xx_prm_read_reg(s16 inst, u16 idx) { - return __raw_readl(prm_base + inst + idx); + return readl_relaxed(prm_base + inst + idx); } /* Write into a register in a PRM instance */ void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) { - __raw_writel(val, prm_base + inst + idx); + writel_relaxed(val, prm_base + inst + idx); } /* Read-modify-write a register in PRM. Caller must lock */ diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 7721990d2006..4bd7a2dca8af 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -43,6 +43,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { .ocp_barrier = &omap3xxx_prm_ocp_barrier, .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, .restore_irqen = &omap3xxx_prm_restore_irqen, + .reconfigure_io_chain = &omap3xxx_prm_reconfigure_io_chain, }; /* @@ -246,7 +247,7 @@ void omap3xxx_prm_reconfigure_io_chain(void) */ static void __init omap3xxx_prm_enable_io_wakeup(void) { - if (omap3_has_io_wakeup()) + if (prm_features & PRM_HAS_IO_WAKEUP) omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); } @@ -400,23 +401,26 @@ struct pwrdm_ops omap3_pwrdm_operations = { * */ +static int omap3xxx_prm_late_init(void); + static struct prm_ll_data omap3xxx_prm_ll_data = { .read_reset_sources = &omap3xxx_prm_read_reset_sources, + .late_init = &omap3xxx_prm_late_init, }; int __init omap3xxx_prm_init(void) { - if (!cpu_is_omap34xx()) - return 0; + if (omap3_has_io_wakeup()) + prm_features |= PRM_HAS_IO_WAKEUP; return prm_register(&omap3xxx_prm_ll_data); } -static int __init omap3xxx_prm_late_init(void) +static int omap3xxx_prm_late_init(void) { int ret; - if (!cpu_is_omap34xx()) + if (!(prm_features & PRM_HAS_IO_WAKEUP)) return 0; omap3xxx_prm_enable_io_wakeup(); @@ -427,15 +431,9 @@ static int __init omap3xxx_prm_late_init(void) return ret; } -omap_subsys_initcall(omap3xxx_prm_late_init); static void __exit omap3xxx_prm_exit(void) { - if (!cpu_is_omap34xx()) - return; - - /* Should never happen */ - WARN(prm_unregister(&omap3xxx_prm_ll_data), - "%s: prm_ll_data function pointer mismatch\n", __func__); + prm_unregister(&omap3xxx_prm_ll_data); } __exitcall(omap3xxx_prm_exit); diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index f8eb83323b1a..1dacfc5b1959 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -26,7 +26,7 @@ /* * OMAP3-specific global PRM registers - * Use __raw_{read,write}l() with these registers. + * Use {read,write}l_relaxed() with these registers. * * With a few exceptions, these are the register names beginning with * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 03a603476cfc..a7f6ea27180a 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .ocp_barrier = &omap44xx_prm_ocp_barrier, .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, .restore_irqen = &omap44xx_prm_restore_irqen, + .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain, }; /* @@ -81,13 +82,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(prm_base + inst + reg); + return readl_relaxed(prm_base + inst + reg); } /* Write into a register in a CM/PRM instance in the PRM module */ void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, prm_base + inst + reg); + writel_relaxed(val, prm_base + inst + reg); } /* Read-modify-write a register in a PRM module. Caller must lock */ @@ -649,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_has_voltdm = omap4_check_vcvp, }; +static int omap44xx_prm_late_init(void); + /* * XXX document */ @@ -656,34 +659,29 @@ static struct prm_ll_data omap44xx_prm_ll_data = { .read_reset_sources = &omap44xx_prm_read_reset_sources, .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, + .late_init = &omap44xx_prm_late_init, }; int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx()) - return 0; + if (cpu_is_omap44xx()) + prm_features |= PRM_HAS_IO_WAKEUP; return prm_register(&omap44xx_prm_ll_data); } -static int __init omap44xx_prm_late_init(void) +static int omap44xx_prm_late_init(void) { - if (!cpu_is_omap44xx()) + if (!(prm_features & PRM_HAS_IO_WAKEUP)) return 0; omap44xx_prm_enable_io_wakeup(); return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); } -omap_subsys_initcall(omap44xx_prm_late_init); static void __exit omap44xx_prm_exit(void) { - if (!cpu_is_omap44xx()) - return; - - /* Should never happen */ - WARN(prm_unregister(&omap44xx_prm_ll_data), - "%s: prm_ll_data function pointer mismatch\n", __func__); + prm_unregister(&omap44xx_prm_ll_data); } __exitcall(omap44xx_prm_exit); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index b4c4ab9c8044..25e8b8232115 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup; /* prm_base: base virtual address of the PRM IP block */ void __iomem *prm_base; +u16 prm_features; + /* * prm_ll_data: function pointers to SoC-specific implementations of * common PRM functions @@ -330,12 +332,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) if (of_have_populated_dt()) { int irq = omap_prcm_event_to_irq("io"); - if (cpu_is_omap34xx()) - omap_pcs_legacy_init(irq, - omap3xxx_prm_reconfigure_io_chain); - else - omap_pcs_legacy_init(irq, - omap44xx_prm_reconfigure_io_chain); + omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain); } return 0; @@ -530,3 +527,11 @@ int __init of_prcm_init(void) return 0; } + +static int __init prm_late_init(void) +{ + if (prm_ll_data->late_init) + return prm_ll_data->late_init(); + return 0; +} +subsys_initcall(prm_late_init); diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index 05fcf6de44ee..69f0dd08629c 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -49,7 +49,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_prm_bases[part]); - return __raw_readl(_prm_bases[part] + inst + idx); + return readl_relaxed(_prm_bases[part] + inst + idx); } /* Write into a register in a PRM instance */ @@ -58,7 +58,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || !_prm_bases[part]); - __raw_writel(val, _prm_bases[part] + inst + idx); + writel_relaxed(val, _prm_bases[part] + inst + idx); } /* Read-modify-write a register in PRM. Caller must lock */ diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 446aa13511fd..645a2a46b213 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base; static inline void sdrc_write_reg(u32 val, u16 reg) { - __raw_writel(val, OMAP_SDRC_REGADDR(reg)); + writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); } static inline u32 sdrc_read_reg(u16 reg) { - return __raw_readl(OMAP_SDRC_REGADDR(reg)); + return readl_relaxed(OMAP_SDRC_REGADDR(reg)); } /* SMS global register get/set */ static inline void sms_write_reg(u32 val, u16 reg) { - __raw_writel(val, OMAP_SMS_REGADDR(reg)); + writel_relaxed(val, OMAP_SMS_REGADDR(reg)); } static inline u32 sms_read_reg(u16 reg) { - return __raw_readl(OMAP_SMS_REGADDR(reg)); + return readl_relaxed(OMAP_SMS_REGADDR(reg)); } extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms); diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 907291714643..ae3f1553158d 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) * prm2xxx.c function */ if (cpu_is_omap2420()) - __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); + writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP); else - __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP); + writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP); omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); curr_perf_level = level; local_irq_restore(flags); diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 30abcc8b20e0..de2a34c423a7 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -459,10 +459,15 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) +#define DRA7XX_CLASS 0x07000000 +#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8)) +#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8)) + void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); void omap4xxx_check_revision(void); void omap5xxx_check_revision(void); +void dra7xxx_check_revision(void); void omap3xxx_check_features(void); void ti81xx_check_features(void); void am33xx_check_features(void); diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index d7bc33f15344..1b91ef0c182a 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data, /* * In OMAP4 the efuse registers are 24 bit aligned. - * A __raw_readl will fail for non-32 bit aligned address + * A readl_relaxed will fail for non-32 bit aligned address * and hence the 8-bit read and shift. */ if (cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c index 4bd096836235..ddf1818af228 100644 --- a/arch/arm/mach-omap2/sram.c +++ b/arch/arm/mach-omap2/sram.c @@ -70,16 +70,16 @@ static int is_sram_locked(void) if (OMAP2_DEVICE_TYPE_GP == omap_type()) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { - __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ - __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ - __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ + writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ + writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ + writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ } if (cpu_is_omap34xx()) { - __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ - __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ - __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ - __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2); - __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); + writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ + writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ + writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ + writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2); + writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); } return 0; } else diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b62de9f9d05c..43d03fbf4c0b 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -361,7 +361,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, /* Clocksource code */ static struct omap_dm_timer clksrc; -static bool use_gptimer_clksrc; +static bool use_gptimer_clksrc __initdata; /* * clocksource @@ -546,15 +546,15 @@ static void __init realtime_counter_init(void) } /* Program numerator and denumerator registers */ - reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= num; - __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); + writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); - reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & + reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= den; - __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); arch_timer_freq = (rate / den) * num; set_cntfreq(); diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 10855eb4ccc1..745367c0c2bb 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,7 +28,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/usb/phy.h> -#include <linux/usb/usb_phy_gen_xceiv.h> +#include <linux/usb/usb_phy_generic.h> #include "soc.h" #include "omap_device.h" @@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = { /* .init_data filled later */ }; -static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */ +static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */ static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ /** @@ -435,7 +435,7 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) struct platform_device *pdev; char *phy_id; struct platform_device_info pdevinfo; - struct usb_phy_gen_xceiv_platform_data nop_pdata; + struct usb_phy_generic_platform_data nop_pdata; for (i = 0; i < num_phys; i++) { @@ -469,8 +469,8 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) pdevinfo.id = phy->port; pdevinfo.data = &nop_pdata; pdevinfo.size_data = - sizeof(struct usb_phy_gen_xceiv_platform_data); - scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", + sizeof(struct usb_phy_generic_platform_data); + scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d", phy->port); pdev = platform_device_register_full(&pdevinfo); if (IS_ERR(pdev)) { diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 49ac7977e03e..a4628a9e760c 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -220,10 +220,126 @@ static inline u32 omap_usec_to_32k(u32 usec) return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); } -/* Set oscillator setup time for omap3 */ -static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm) +struct omap3_vc_timings { + u32 voltsetup1; + u32 voltsetup2; +}; + +struct omap3_vc { + struct voltagedomain *vd; + u32 voltctrl; + u32 voltsetup1; + u32 voltsetup2; + struct omap3_vc_timings timings[2]; +}; +static struct omap3_vc vc; + +void omap3_vc_set_pmic_signaling(int core_next_state) +{ + struct voltagedomain *vd = vc.vd; + struct omap3_vc_timings *c = vc.timings; + u32 voltctrl, voltsetup1, voltsetup2; + + voltctrl = vc.voltctrl; + voltsetup1 = vc.voltsetup1; + voltsetup2 = vc.voltsetup2; + + switch (core_next_state) { + case PWRDM_POWER_OFF: + voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | + OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); + voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; + if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) + voltsetup2 = c->voltsetup2; + else + voltsetup1 = c->voltsetup1; + break; + case PWRDM_POWER_RET: + default: + c++; + voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | + OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); + voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; + voltsetup1 = c->voltsetup1; + break; + } + + if (voltctrl != vc.voltctrl) { + vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); + vc.voltctrl = voltctrl; + } + if (voltsetup1 != vc.voltsetup1) { + vd->write(c->voltsetup1, + OMAP3_PRM_VOLTSETUP1_OFFSET); + vc.voltsetup1 = voltsetup1; + } + if (voltsetup2 != vc.voltsetup2) { + vd->write(c->voltsetup2, + OMAP3_PRM_VOLTSETUP2_OFFSET); + vc.voltsetup2 = voltsetup2; + } +} + +#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \ + OMAP3430_PRM_POLCTRL_CLKREQ_POL) +#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL + +/* + * Configure signal polarity for sys_clkreq and sys_off_mode pins + * as the default values are wrong and can cause the system to hang + * if any twl4030 scripts are loaded. + */ +static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) +{ + u32 val; + + if (vc.vd) + return; + + vc.vd = voltdm; + + val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); + if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || + (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) { + val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; + val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; + pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", + val); + voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); + } + + /* + * By default let's use I2C4 signaling for retention idle + * and sys_off_mode pin signaling for off idle. This way we + * have sys_clk_req pin go down for retention and both + * sys_clk_req and sys_off_mode pins will go down for off + * idle. And we can also scale voltages to zero for off-idle. + * Note that no actual voltage scaling during off-idle will + * happen unless the board specific twl4030 PMIC scripts are + * loaded. + */ + val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); + if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { + val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; + pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", + val); + voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); + } + vc.voltctrl = val; + + omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); +} + +static void omap3_init_voltsetup1(struct voltagedomain *voltdm, + struct omap3_vc_timings *c, u32 idle) { - voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET); + unsigned long val; + + val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; + val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; + val <<= __ffs(voltdm->vfsm->voltsetup_mask); + c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; + c->voltsetup1 |= val; } /** @@ -236,37 +352,21 @@ static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm) * or retention. Off mode has additionally an option to use sys_off_mode * pad, which uses a global signal to program the whole power IC to * off-mode. + * + * Note that pmic is not controlling the voltage scaling during + * retention signaled over I2C4, so we can keep voltsetup2 as 0. + * And the oscillator is not shut off over I2C4, so no need to + * set clksetup. */ -static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) +static void omap3_set_i2c_timings(struct voltagedomain *voltdm) { - unsigned long voltsetup1; - u32 tgt_volt; - - /* - * Oscillator is shut down only if we are using sys_off_mode pad, - * thus we set a minimal setup time here - */ - omap3_set_clksetup(1, voltdm); + struct omap3_vc_timings *c = vc.timings; - if (off_mode) - tgt_volt = voltdm->vc_param->off; - else - tgt_volt = voltdm->vc_param->ret; - - voltsetup1 = (voltdm->vc_param->on - tgt_volt) / - voltdm->pmic->slew_rate; - - voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1; - - voltdm->rmw(voltdm->vfsm->voltsetup_mask, - voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask), - voltdm->vfsm->voltsetup_reg); - - /* - * pmic is not controlling the voltage scaling during retention, - * thus set voltsetup2 to 0 - */ - voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET); + /* Configure PRWDM_POWER_OFF over I2C4 */ + omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); + c++; + /* Configure PRWDM_POWER_RET over I2C4 */ + omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); } /** @@ -275,69 +375,49 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) * * Calculates and sets up off-mode timings for a channel. Off-mode * can use either I2C based voltage scaling, or alternatively - * sys_off_mode pad can be used to send a global command to power IC. - * This function first checks which mode is being used, and calls - * omap3_set_i2c_timings() if the system is using I2C control mode. + * sys_off_mode pad can be used to send a global command to power IC.n, * sys_off_mode has the additional benefit that voltages can be * scaled to zero volt level with TWL4030 / TWL5030, I2C can only * scale to 600mV. + * + * Note that omap is not controlling the voltage scaling during + * off idle signaled by sys_off_mode, so we can keep voltsetup1 + * as 0. */ static void omap3_set_off_timings(struct voltagedomain *voltdm) { - unsigned long clksetup; - unsigned long voltsetup2; - unsigned long voltsetup2_old; - u32 val; - u32 tstart, tshut; + struct omap3_vc_timings *c = vc.timings; + u32 tstart, tshut, clksetup, voltoffset; - /* check if sys_off_mode is used to control off-mode voltages */ - val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); - if (!(val & OMAP3430_SEL_OFF_MASK)) { - /* No, omap is controlling them over I2C */ - omap3_set_i2c_timings(voltdm, true); + if (c->voltsetup2) return; - } omap_pm_get_oscillator(&tstart, &tshut); - omap3_set_clksetup(tstart, voltdm); - - clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET); - - /* voltsetup 2 in us */ - voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate; - - /* convert to 32k clk cycles */ - voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000); - - voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET); - - /* - * Update voltsetup2 if higher than current value (needed because - * we have multiple channels with different ramp times), also - * update voltoffset always to value recommended by TRM - */ - if (voltsetup2 > voltsetup2_old) { - voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET); - voltdm->write(clksetup - voltsetup2, - OMAP3_PRM_VOLTOFFSET_OFFSET); - } else - voltdm->write(clksetup - voltsetup2_old, - OMAP3_PRM_VOLTOFFSET_OFFSET); + if (tstart == ULONG_MAX) { + pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); + clksetup = omap_usec_to_32k(10000); + } else { + clksetup = omap_usec_to_32k(tstart); + } /* - * omap is not controlling voltage scaling during off-mode, - * thus set voltsetup1 to 0 + * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to + * switch from HFCLKIN to internal oscillator. That means timings + * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And + * that means we can calculate the value based on the oscillator + * start-up time since voltoffset2 = clksetup - voltoffset. */ - voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0, - voltdm->vfsm->voltsetup_reg); - - /* voltoffset must be clksetup minus voltsetup2 according to TRM */ - voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET); + voltoffset = omap_usec_to_32k(488); + c->voltsetup2 = clksetup - voltoffset; + voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); + voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); } static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) { + omap3_vc_init_pmic_signaling(voltdm); omap3_set_off_timings(voltdm); + omap3_set_i2c_timings(voltdm); } /** @@ -462,7 +542,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, OMAP4_DOWNTIME_MASK); - __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME); + writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); } /* OMAP4 specific voltage init functions */ @@ -584,7 +664,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ - __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + + writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); /* HSSCLH can always be zero */ diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index 91c8d75bf2ea..cdbdd78e755e 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -117,6 +117,9 @@ extern struct omap_vc_param omap4_mpu_vc_data; extern struct omap_vc_param omap4_iva_vc_data; extern struct omap_vc_param omap4_core_vc_data; +void omap3_vc_set_pmic_signaling(int core_next_state); + + void omap_vc_init_channel(struct voltagedomain *voltdm); int omap_vc_pre_scale(struct voltagedomain *voltdm, unsigned long target_volt, diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index d15c7bbab8e2..97d6607d447a 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh) } /* sequence required to disable watchdog */ - __raw_writel(0xAAAA, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + writel_relaxed(0xAAAA, base + OMAP_WDT_SPR); + while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) cpu_relax(); - __raw_writel(0x5555, base + OMAP_WDT_SPR); - while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + writel_relaxed(0x5555, base + OMAP_WDT_SPR); + while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) cpu_relax(); return 0; |