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| author | Rajendra Nayak <rnayak@ti.com> | 2012-11-07 02:41:08 +0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-11-13 06:10:20 +0400 |
| commit | cb26867ee24a7e32ab72ec28e43456c7571c059a (patch) | |
| tree | aaa2d1e32d51014b2a5b7ed32602be8f5178b490 /arch/arm/mach-omap2/clock44xx_data.c | |
| parent | 8c725dcd2246e8500a6fdd394ef4cb0cf96f2217 (diff) | |
| download | linux-cb26867ee24a7e32ab72ec28e43456c7571c059a.tar.xz | |
ARM: OMAP4: clock: Add 44xx data using common struct clk
This patch is output from updated omap hw data autogeneration scripts
mostly contributed by Mike Turquette, with some later fixes from me.
All data is added into a new cclock44xx_data.c file which will be
switched with clock44xx_data.c file in a later patch.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: replace omap2_init_clksel_parent() with
omap2_clksel_find_parent_index(); reflowed macros; updated
DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name;
use macros for clksel mux+gate clocks; many other fixes]
[mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro; trace_clk_div_ck
has clkdm ops]
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: fixed the omap-gpmc.fck alias per commit a2e5b90b; fixed
several checkpatch issues; moved the dpll3xxx.c clockdomain modifications to
another patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 2a450c9b9a7b..ef6d09e9a938 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = { .recalc = &omap_fixed_divisor_recalc, }; -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - static const struct clksel abe_clk_div[] = { { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = { .min_divider = 1, }; - static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", .parent = &sys_clkin_ck, |